asm/arch-sunxi/clock_sun50i_h6.h

13 	u32 pll1_cfg;		/* 0x000 pll1 (cpux) control */
15 	u32 pll5_cfg;		/* 0x010 pll5 (ddr) control */
17 	u32 pll6_cfg;		/* 0x020 pll6 (periph0) control */
19 	u32 pll_periph1_cfg;	/* 0x028 pll periph1 control */
21 	u32 pll7_cfg;		/* 0x030 pll7 (gpu) control */
23 	u32 pll3_cfg;		/* 0x040 pll3 (video0) control */
25 	u32 pll_video1_cfg;	/* 0x048 pll video1 control */
27 	u32 pll4_cfg;		/* 0x058 pll4 (ve) control */
29 	u32 pll10_cfg;		/* 0x060 pll10 (de) control */
31 	u32 pll9_cfg;		/* 0x070 pll9 (hsic) control */
33 	u32 pll2_cfg;		/* 0x078 pll2 (audio) control */
81 	u32 cpu_axi_cfg;	/* 0x500 CPUX/AXI clock control*/
83 	u32 psi_ahb1_ahb2_cfg;	/* 0x510 PSI/AHB1/AHB2 clock control */
85 	u32 ahb3_cfg;		/* 0x51c AHB3 clock control */
86 	u32 apb1_cfg;		/* 0x520 APB1 clock control */
87 	u32 apb2_cfg;		/* 0x524 APB2 clock control */
89 	u32 mbus_cfg;		/* 0x540 MBUS clock control */
91 	u32 de_clk_cfg;		/* 0x600 DE clock control */
93 	u32 de_gate_reset;	/* 0x60c DE gate/reset control */
95 	u32 di_clk_cfg;		/* 0x620 DI clock control */
97 	u32 di_gate_reset;	/* 0x62c DI gate/reset control */
99 	u32 gpu_clk_cfg;	/* 0x670 GPU clock control */
101 	u32 gpu_gate_reset;	/* 0x67c GPU gate/reset control */
102 	u32 ce_clk_cfg;		/* 0x680 CE clock control */
104 	u32 ce_gate_reset;	/* 0x68c CE gate/reset control */
105 	u32 ve_clk_cfg;		/* 0x690 VE clock control */
107 	u32 ve_gate_reset;	/* 0x69c VE gate/reset control */
109 	u32 emce_clk_cfg;	/* 0x6b0 EMCE clock control */
111 	u32 emce_gate_reset;	/* 0x6bc EMCE gate/reset control */
112 	u32 vp9_clk_cfg;	/* 0x6c0 VP9 clock control */
114 	u32 vp9_gate_reset;	/* 0x6cc VP9 gate/reset control */
116 	u32 dma_gate_reset;	/* 0x70c DMA gate/reset control */
118 	u32 msgbox_gate_reset;	/* 0x71c Message Box gate/reset control */
120 	u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */
122 	u32 hstimer_gate_reset;	/* 0x73c HS Timer gate/reset control */
123 	u32 avs_gate_reset;	/* 0x740 AVS gate/reset control */
125 	u32 dbgsys_gate_reset;	/* 0x78c Debugging system gate/reset control */
127 	u32 psi_gate_reset;	/* 0x79c PSI gate/reset control */
129 	u32 pwm_gate_reset;	/* 0x7ac PWM gate/reset control */
131 	u32 iommu_gate_reset;	/* 0x7bc IOMMU gate/reset control */
133 	u32 dram_clk_cfg;		/* 0x800 DRAM clock control */
134 	u32 mbus_gate;		/* 0x804 MBUS gate control */
136 	u32 dram_gate_reset;	/* 0x80c DRAM gate/reset control */
137 	u32 nand0_clk_cfg;	/* 0x810 NAND0 clock control */
138 	u32 nand1_clk_cfg;	/* 0x814 NAND1 clock control */
140 	u32 nand_gate_reset;	/* 0x82c NAND gate/reset control */
141 	u32 sd0_clk_cfg;	/* 0x830 MMC0 clock control */
142 	u32 sd1_clk_cfg;	/* 0x834 MMC1 clock control */
143 	u32 sd2_clk_cfg;	/* 0x838 MMC2 clock control */
145 	u32 sd_gate_reset;	/* 0x84c MMC gate/reset control */
147 	u32 uart_gate_reset;	/* 0x90c UART gate/reset control */
149 	u32 twi_gate_reset;	/* 0x91c I2C gate/reset control */
151 	u32 scr_gate_reset;	/* 0x93c SCR gate/reset control */
152 	u32 spi0_clk_cfg;	/* 0x940 SPI0 clock control */
153 	u32 spi1_clk_cfg;	/* 0x944 SPI1 clock control */
155 	u32 spi_gate_reset;	/* 0x96c SPI gate/reset control */
157 	u32 emac_gate_reset;	/* 0x97c EMAC gate/reset control */
159 	u32 ts_clk_cfg;		/* 0x9b0 TS clock control */
161 	u32 ts_gate_reset;	/* 0x9bc TS gate/reset control */
162 	u32 irtx_clk_cfg;	/* 0x9c0 IR TX clock control */
164 	u32 irtx_gate_reset;	/* 0x9cc IR TX gate/reset control */
166 	u32 ths_gate_reset;	/* 0x9fc THS gate/reset control */
168 	u32 i2s3_clk_cfg;	/* 0xa0c I2S3 clock control */
169 	u32 i2s0_clk_cfg;	/* 0xa10 I2S0 clock control */
170 	u32 i2s1_clk_cfg;	/* 0xa14 I2S1 clock control */
171 	u32 i2s2_clk_cfg;	/* 0xa18 I2S2 clock control */
172 	u32 i2s_gate_reset;	/* 0xa1c I2S gate/reset control */
173 	u32 spdif_clk_cfg;	/* 0xa20 SPDIF clock control */
175 	u32 spdif_gate_reset;	/* 0xa2c SPDIF gate/reset control */
177 	u32 dmic_clk_cfg;	/* 0xa40 DMIC clock control */
179 	u32 dmic_gate_reset;	/* 0xa4c DMIC gate/reset control */
181 	u32 ahub_clk_cfg;	/* 0xa60 Audio HUB clock control */
183 	u32 ahub_gate_reset;	/* 0xa6c Audio HUB gate/reset control */
184 	u32 usb0_clk_cfg;	/* 0xa70 USB0(OTG) clock control */
185 	u32 usb1_clk_cfg;	/* 0xa74 USB1(XHCI) clock control */
187 	u32 usb3_clk_cfg;	/* 0xa78 USB3 clock control */
189 	u32 usb_gate_reset;	/* 0xa8c USB gate/reset control */
191 	u32 pcie_ref_clk_cfg;	/* 0xab0 PCIE REF clock control */
192 	u32 pcie_axi_clk_cfg;	/* 0xab4 PCIE AXI clock control */
193 	u32 pcie_aux_clk_cfg;	/* 0xab8 PCIE AUX clock control */
194 	u32 pcie_gate_reset;	/* 0xabc PCIE gate/reset control */
196 	u32 hdmi_clk_cfg;	/* 0xb00 HDMI clock control */
197 	u32 hdmi_slow_clk_cfg;	/* 0xb04 HDMI slow clock control */
199 	u32 hdmi_cec_clk_cfg;	/* 0xb10 HDMI CEC clock control */
201 	u32 hdmi_gate_reset;	/* 0xb1c HDMI gate/reset control */
203 	u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */
204 	u32 tcon_lcd0_clk_cfg;	/* 0xb60 TCON LCD0 clock control */
206 	u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */
207 	u32 tcon_tv0_clk_cfg;	/* 0xb80 TCON TV0 clock control */
209 	u32 tcon_tv_gate_reset;	/* 0xb9c TCON TV gate/reset control */
211 	u32 csi_misc_clk_cfg;	/* 0xc00 CSI MISC clock control */
212 	u32 csi_top_clk_cfg;	/* 0xc04 CSI TOP clock control */
213 	u32 csi_mclk_cfg;	/* 0xc08 CSI Master clock control */
215 	u32 csi_gate_reset;	/* 0xc2c CSI gate/reset control */
217 	u32 hdcp_clk_cfg;	/* 0xc40 HDCP clock control */
219 	u32 hdcp_gate_reset;	/* 0xc4c HDCP gate/reset control */
222 	u32 pll_lock_dbg_ctrl;	/* 0xf04 PLL lock debugging control */