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/openbmc/linux/sound/core/seq/
H A Dseq_ump_convert.c1 // SPDX-License-Identifier: GPL-2.0-or-later
68 return port->ump_group ? (port->ump_group - 1) : 0; in get_ump_group()
76 * UMP -> MIDI1 sequencer event
85 ev->data.note.channel = val->note.channel; in ump_midi1_to_note_ev()
86 ev->data.note.note = val->note.note; in ump_midi1_to_note_ev()
87 ev->data.note.velocity = val->note.velocity; in ump_midi1_to_note_ev()
94 ev->data.control.channel = val->caf.channel; in ump_midi1_to_ctrl_ev()
95 ev->data.control.value = val->caf.data; in ump_midi1_to_ctrl_ev()
102 ev->data.control.channel = val->pb.channel; in ump_midi1_to_pitchbend_ev()
103 ev->data.control.value = (val->pb.data_msb << 7) | val->pb.data_lsb; in ump_midi1_to_pitchbend_ev()
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/openbmc/linux/sound/soc/codecs/
H A Dssm2602.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
49 /*Left ADC Volume Control (SSM2602_REG_LEFT_ADC_VOL)*/
50 #define LINVOL_LIN_VOL 0x01F /* Left Channel PGA Volume control …
51 #define LINVOL_LIN_ENABLE_MUTE 0x080 /* Left Channel Input Mute …
52 #define LINVOL_LRIN_BOTH 0x100 /* Left Channel Line Input Volume update …
54 /*Right ADC Volume Control (SSM2602_REG_RIGHT_ADC_VOL)*/
55 #define RINVOL_RIN_VOL 0x01F /* Right Channel PGA Volume control …
56 #define RINVOL_RIN_ENABLE_MUTE 0x080 /* Right Channel Input Mute …
57 #define RINVOL_RLIN_BOTH 0x100 /* Right Channel Line Input Volume update …
59 /*Left DAC Volume Control (SSM2602_REG_LEFT_DAC_VOL)*/
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/openbmc/linux/include/sound/
H A Dseq_midi_emul.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Midi channel definition for optional channel management.
15 * channel. All drivers for hardware that does not understand midi
20 int number; /* The channel number */
21 int client; /* The client associated with this channel */
22 int port; /* The port associated with this channel */
26 drum_channel:1, /* Drum channel */
31 unsigned char midi_pressure; /* Channel pressure */
35 unsigned char control[128]; /* Current value of all controls */ member
48 * The channel set consists of information describing the client and
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/openbmc/u-boot/include/
H A Dw83c553f.h1 /* SPDX-License-Identifier: GPL-2.0+ */
9 /* from the winbond data sheet -
10 The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
19 #define WINBOND_PCICONTR 0x40 /*pci control reg*/
21 #define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/
22 #define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/
23 #define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/
25 #define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/
26 #define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/
30 #define WINBOND_CSCR 0x4d /*Chip Select Control Register*/
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H A DSA-1100.h2 * FILE SA-1100.h
8 * System StrongARM SA-1100
11 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
13 * StrongARM SA-1100 data sheet version 2.2.
15 * Language-specific definitions are selected by the
33 #include <asm/arch-sa1100/bitfield.h>
181 * Universal Serial Bus (USB) Device Controller (UDC) control registers
185 * Controller (UDC) Control Register (read/write).
195 * Controller (UDC) Control/Status register end-point 0
198 * Controller (UDC) Control/Status register end-point 1
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H A DMCD_dma.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
62 * multi-channel DMA
70 u16 ptdControl; /* ptd control */
73 u16 taskControl[16]; /* task control */
75 u32 initiatorMux; /* initiator mux control */
76 u32 taskSize0; /* task size control 0. */
77 u32 taskSize1; /* task size control 1. */
82 u32 debugControl; /* debug control */
95 /* Task Control reg bits and field masks */
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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Daudio-iio-aux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/audio-iio-aux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
16 - $ref: dai-common.yaml#
20 const: audio-iio-aux
22 io-channels:
26 io-channel-names:
28 Industrial I/O channel names related to io-channels.
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/openbmc/linux/drivers/dma/
H A Dep93xx_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * arch/arm/mach-ep93xx/dma-m2p.c which has following copyrights:
14 * This driver is based on dw_dmac and amba-pl08x drivers.
26 #include <linux/platform_data/dma-ep93xx.h>
113 * struct ep93xx_dma_desc - EP93xx specific transaction descriptor
120 * @node: link used for putting this into a channel queue
133 * struct ep93xx_dma_chan - an EP93xx DMA M2P/M2M channel
134 * @chan: dmaengine API channel
137 * @irq: interrupt number of the channel
138 * @clk: clock used by this channel
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/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
12 * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
13 * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
22 /* FIXME hack so that SA-1111.h will work [cb] */
96 #define DCSR0 0x40000000 /* DMA Control / Status Register for Channel 0 */
97 #define DCSR1 0x40000004 /* DMA Control / Status Register for Channel 1 */
98 #define DCSR2 0x40000008 /* DMA Control / Status Register for Channel 2 */
99 #define DCSR3 0x4000000c /* DMA Control / Status Register for Channel 3 */
100 #define DCSR4 0x40000010 /* DMA Control / Status Register for Channel 4 */
101 #define DCSR5 0x40000014 /* DMA Control / Status Register for Channel 5 */
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/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dbrcmu_d11.h1 // SPDX-License-Identifier: ISC
13 /* A chanspec (channel specification) holds the channel number, band,
14 * bandwidth and control sideband
20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
38 #define BRCMU_CHSPEC_D11N_SB_L 0x0100 /* control lower */
39 #define BRCMU_CHSPEC_D11N_SB_U 0x0200 /* control upper */
100 BRCMU_CHAN_SB_NONE = -1,
118 * struct brcmu_chan - stores channel formats
121 * channel info and the other way.
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/openbmc/linux/sound/pci/
H A Dad1889.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2004, Kyle McMartin <kyle@parisc-linux.org>
9 #define AD_DS_WSMC 0x00 /* wave/synthesis channel mixer control */
10 #define AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */
12 #define AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */
13 #define AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */
14 #define AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */
17 #define AD_DS_RAMC 0x02 /* resampler/ADC channel mixer control */
18 #define AD_DS_RAMC_AD16 0x0001 /* ADC channel 16bit select */
19 #define AD_DS_RAMC_ADST 0x0002 /* ADC channel stereo select */
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/openbmc/qemu/docs/devel/
H A Ds390-dasd-ipl.rst1 Booting from real channel-attached devices on s390x
5 -----------------
18 IPL ccw it read the 24-bytes of IPL1 to be read into memory starting at
22 and the TIC (Transfer In Channel) will transfer control to the channel
23 program contained in the IPL2 data. The TIC channel command is the
24 equivalent of a branch/jump/goto instruction for channel programs.
29 The TIC ccw instruction at the end of the IPL1 channel program will begin
30 the execution of the IPL2 channel program. IPL2 is stage-2 of the boot
31 process and will contain a larger channel program than IPL1. The point of
35 control over to the guest operating system. At this point the guest
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/openbmc/linux/sound/pci/emu10k1/
H A Dp16v.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
11 /* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers …
15 …* The sample rate is also controlled by the same registers that control the rate of the EMU10K2 sa…
25 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
41 /* [0:1] Capture input 0 channel select. 0 = Capture output 0.
45 * [3:2] Capture input 1 channel select. 0 = Capture output 0.
49 * [5:4] Capture input 2 channel select. 0 = Capture output 0.
53 * [7:6] Capture input 3 channel select. 0 = Capture output 0.
57 * [9:8] Playback input 0 channel select. 0 = Play output 0.
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/openbmc/qemu/hw/dma/
H A Dxlnx_dpdma.c102 * Descriptor control field.
136 uint32_t control; member
162 return ((desc->control & DSCR_CTRL_LAST_DESCRIPTOR) != 0); in xlnx_dpdma_desc_is_last()
167 return ((desc->control & DSCR_CTRL_LAST_DESCRIPTOR_OF_FRAME) != 0); in xlnx_dpdma_desc_is_last_of_frame()
178 addr = (uint64_t)desc->source_address in xlnx_dpdma_desc_get_source_address()
179 + (extract64(desc->address_extension, 16, 16) << 32); in xlnx_dpdma_desc_get_source_address()
182 addr = (uint64_t)desc->source_address2 in xlnx_dpdma_desc_get_source_address()
183 + (extract64(desc->address_extension_23, 0, 16) << 32); in xlnx_dpdma_desc_get_source_address()
186 addr = (uint64_t)desc->source_address3 in xlnx_dpdma_desc_get_source_address()
187 + (extract64(desc->address_extension_23, 16, 16) << 32); in xlnx_dpdma_desc_get_source_address()
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/openbmc/linux/Documentation/sound/designs/
H A Dchannel-mapping-api.rst2 ALSA PCM channel-mapping API
10 The channel mapping API allows user to query the possible channel maps
11 and the current channel map, also optionally to modify the channel map
14 A channel map is an array of position for each PCM channel.
15 Typically, a stereo PCM stream has a channel map of
17 while a 4.0 surround PCM stream has a channel map of
20 The problem, so far, was that we had no standard channel map
21 explicitly, and applications had no way to know which channel
29 was no way to specify this because of lack of channel map
30 specification. These are the main motivations for the new channel
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/openbmc/linux/drivers/hwmon/
H A Dpcf8591.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2001-2004 Aurelien Jarno <aurelien@aurel32.net>
31 * The PCF8591 control byte
52 * Channel selection
53 * 0x00 = channel 0
54 * 0x01 = channel 1
55 * 0x02 = channel 2
56 * 0x03 = channel 3
65 #define REG_TO_SIGNED(reg) (((reg) & 0x80) ? ((reg) - 256) : (reg))
71 u8 control; member
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/openbmc/linux/drivers/tty/serial/
H A Dip22zilog.c1 // SPDX-License-Identifier: GPL-2.0
6 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the
13 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)
51 #define ZS_WSYNC(channel) do { } while (0) argument
87 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
90 (UART_ZILOG(PORT)->curregs[REGNUM])
92 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
93 #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
94 #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
95 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS)
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H A Dsunzilog.c1 // SPDX-License-Identifier: GPL-2.0
48 /* On 32-bit sparcs we need to delay after register accesses
50 * On 64-bit sparc we only need to flush single writes to ensure
56 #define ZS_WSYNC(channel) do { } while (0) argument
61 readb(&((__channel)->control))
105 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase))
108 #define ZS_IS_KEYB(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
109 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
110 #define ZS_IS_CONS(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
111 #define ZS_IS_KGDB(UP) ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
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/openbmc/linux/Documentation/networking/
H A Dppp_generic.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PPP Generic Driver and Channel Interface
12 The generic PPP driver in linux-2.4 provides an implementation of the
26 the services of PPP ``channels``. A PPP channel encapsulates a
28 PPP channel implementation can be arbitrarily complex internally but
31 handle ioctl requests. Currently there are PPP channel
36 natural and straightforward way, by allowing more than one channel to
42 PPP channel API
43 ---------------
49 Each channel has to provide two functions to the generic PPP layer,
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H A Dcdc_mbim.rst1 .. SPDX-License-Identifier: GPL-2.0
4 cdc_mbim - Driver for CDC MBIM Mobile Broadband modems
11 Network Control Model Devices" [2] optimized for Mobile Broadband
24 -----------
26 :Valid Range: N/Y (0-1)
44 provides a userspace interface to the MBIM control channel, and will
51 - mbimcli (included with the libmbim [3] library), and
52 - ModemManager [4]
57 - open the control channel
58 - configure network connection settings
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/openbmc/linux/Documentation/sound/hd-audio/
H A Dcontrols.rst2 HD-Audio Codec-Specific Mixer Controls
6 This file explains the codec-specific mixer controls.
9 --------------
11 Channel Mode
12 This is an enum control to change the surround-channel setup,
16 jack-retasking of multi-I/O jacks.
18 Auto-Mute Mode
19 This is an enum control to change the auto-mute behavior of the
20 headphone and line-out jacks. If built-in speakers and headphone
21 and/or line-out jacks are available on a machine, this controls
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/openbmc/linux/drivers/video/fbdev/
H A Dpxa3xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define LCCR0 (0x000) /* LCD Controller Control Register 0 */
9 #define LCCR1 (0x004) /* LCD Controller Control Register 1 */
10 #define LCCR2 (0x008) /* LCD Controller Control Register 2 */
11 #define LCCR3 (0x00C) /* LCD Controller Control Register 3 */
12 #define LCCR4 (0x010) /* LCD Controller Control Register 4 */
13 #define LCCR5 (0x014) /* LCD Controller Control Register 5 */
18 #define TMEDCR (0x044) /* TMED Control Register */
20 #define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */
21 #define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */
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/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dxor.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define MV_IS_POWER_OF_2(num) (((num) != 0) && (((num) & ((num) - 1)) == 0))
36 * This enumerator describes the type of functionality the XOR channel
40 MV_XOR, /* XOR channel functions as XOR accelerator */
41 MV_DMA, /* XOR channel functions as IDMA channel */
42 MV_CRC32 /* XOR channel functions as CRC 32 calculator */
70 SRC_ADDR0, /* Source Address #0 Control */
71 SRC_ADDR1, /* Source Address #1 Control */
72 SRC_ADDR2, /* Source Address #2 Control */
73 SRC_ADDR3, /* Source Address #3 Control */
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/openbmc/linux/Documentation/hwmon/
H A Dltc2947.rst1 Kernel drivers ltc2947-i2c and ltc2947-spi
10 Addresses scanned: -
14 https://www.analog.com/media/en/technical-documentation/data-sheets/LTC2947.pdf
29 to control a fan as a function of measured temperature. Then, the GPIO becomes
31 temp2 channel is used to control this thresholds and to read the respective
37 The following attributes are supported. Limits are read-write, reset_history
38 is write-only and all the other attributes are read-only.
41 in0_input VP-VM voltage (mV).
49 in0_label Channel label (VP-VM)
59 in1_label Channel label (DVCC)
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/openbmc/linux/Documentation/leds/
H A Dleds-lp5523.rst9 Contact: Samu Onkalo (samu.p.onkalo-at-nokia.com)
12 -----------
14 the led class control interface.
15 The name of each channel is configurable in the platform data - name and label.
16 There are three options to make the channel name.
20 To make specific channel name, then use 'name' platform data.
22 - /sys/class/leds/R1 (name: 'R1')
23 - /sys/class/leds/B1 (name: 'B1')
27 For one device name with channel number, then use 'label'.
28 - /sys/class/leds/RGB:channelN (label: 'RGB', N: 0 ~ 8)
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