183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2f1df9364SStefan Roese /* 3f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 4f1df9364SStefan Roese */ 5f1df9364SStefan Roese 6f1df9364SStefan Roese #ifndef _XOR_H 7f1df9364SStefan Roese #define _XOR_H 8f1df9364SStefan Roese 9f1df9364SStefan Roese #define SRAM_BASE 0x40000000 10f1df9364SStefan Roese 11f1df9364SStefan Roese #define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */ 12f1df9364SStefan Roese #define MV_XOR_MAX_CHAN 4 /* total channels for all units */ 13f1df9364SStefan Roese #define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ 14f1df9364SStefan Roese 15f1df9364SStefan Roese #define MV_IS_POWER_OF_2(num) (((num) != 0) && (((num) & ((num) - 1)) == 0)) 16f1df9364SStefan Roese 17f1df9364SStefan Roese /* 18f1df9364SStefan Roese * This structure describes address space window. Window base can be 19f1df9364SStefan Roese * 64 bit, window size up to 4GB 20f1df9364SStefan Roese */ 21f1df9364SStefan Roese struct addr_win { 22f1df9364SStefan Roese u32 base_low; /* 32bit base low */ 23f1df9364SStefan Roese u32 base_high; /* 32bit base high */ 24f1df9364SStefan Roese u32 size; /* 32bit size */ 25f1df9364SStefan Roese }; 26f1df9364SStefan Roese 27f1df9364SStefan Roese /* This structure describes SoC units address decode window */ 28f1df9364SStefan Roese struct unit_win_info { 29f1df9364SStefan Roese struct addr_win addr_win; /* An address window */ 30f1df9364SStefan Roese int enable; /* Address decode window is enabled/disabled */ 31f1df9364SStefan Roese u8 attrib; /* chip select attributes */ 32f1df9364SStefan Roese u8 target_id; /* Target Id of this MV_TARGET */ 33f1df9364SStefan Roese }; 34f1df9364SStefan Roese 35f1df9364SStefan Roese /* 36f1df9364SStefan Roese * This enumerator describes the type of functionality the XOR channel 37f1df9364SStefan Roese * can have while using the same data structures. 38f1df9364SStefan Roese */ 39f1df9364SStefan Roese enum xor_type { 40f1df9364SStefan Roese MV_XOR, /* XOR channel functions as XOR accelerator */ 41f1df9364SStefan Roese MV_DMA, /* XOR channel functions as IDMA channel */ 42f1df9364SStefan Roese MV_CRC32 /* XOR channel functions as CRC 32 calculator */ 43f1df9364SStefan Roese }; 44f1df9364SStefan Roese 45f1df9364SStefan Roese enum mv_state { 46f1df9364SStefan Roese MV_IDLE, 47f1df9364SStefan Roese MV_ACTIVE, 48f1df9364SStefan Roese MV_PAUSED, 49f1df9364SStefan Roese MV_UNDEFINED_STATE 50f1df9364SStefan Roese }; 51f1df9364SStefan Roese 52f1df9364SStefan Roese /* 53f1df9364SStefan Roese * This enumerator describes the set of commands that can be applied on 54f1df9364SStefan Roese * an engine (e.g. IDMA, XOR). Appling a comman depends on the current 55f1df9364SStefan Roese * status (see MV_STATE enumerator) 56f1df9364SStefan Roese * 57f1df9364SStefan Roese * Start can be applied only when status is IDLE 58f1df9364SStefan Roese * Stop can be applied only when status is IDLE, ACTIVE or PAUSED 59f1df9364SStefan Roese * Pause can be applied only when status is ACTIVE 60f1df9364SStefan Roese * Restart can be applied only when status is PAUSED 61f1df9364SStefan Roese */ 62f1df9364SStefan Roese enum mv_command { 63f1df9364SStefan Roese MV_START, /* Start */ 64f1df9364SStefan Roese MV_STOP, /* Stop */ 65f1df9364SStefan Roese MV_PAUSE, /* Pause */ 66f1df9364SStefan Roese MV_RESTART /* Restart */ 67f1df9364SStefan Roese }; 68f1df9364SStefan Roese 69f1df9364SStefan Roese enum xor_override_target { 70f1df9364SStefan Roese SRC_ADDR0, /* Source Address #0 Control */ 71f1df9364SStefan Roese SRC_ADDR1, /* Source Address #1 Control */ 72f1df9364SStefan Roese SRC_ADDR2, /* Source Address #2 Control */ 73f1df9364SStefan Roese SRC_ADDR3, /* Source Address #3 Control */ 74f1df9364SStefan Roese SRC_ADDR4, /* Source Address #4 Control */ 75f1df9364SStefan Roese SRC_ADDR5, /* Source Address #5 Control */ 76f1df9364SStefan Roese SRC_ADDR6, /* Source Address #6 Control */ 77f1df9364SStefan Roese SRC_ADDR7, /* Source Address #7 Control */ 78f1df9364SStefan Roese XOR_DST_ADDR, /* Destination Address Control */ 79f1df9364SStefan Roese XOR_NEXT_DESC /* Next Descriptor Address Control */ 80f1df9364SStefan Roese }; 81f1df9364SStefan Roese 82f1df9364SStefan Roese enum mv_state mv_xor_state_get(u32 chan); 83f1df9364SStefan Roese void mv_xor_hal_init(u32 xor_chan_num); 84f1df9364SStefan Roese int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl); 85f1df9364SStefan Roese int mv_xor_command_set(u32 chan, enum mv_command command); 86f1df9364SStefan Roese int mv_xor_override_set(u32 chan, enum xor_override_target target, u32 win_num, 87f1df9364SStefan Roese int enable); 88*2b4ffbf6SChris Packham int mv_xor_transfer(u32 chan, enum xor_type type, u32 xor_chain_ptr); 89f1df9364SStefan Roese 90f1df9364SStefan Roese #endif 91