| /openbmc/linux/tools/memory-model/Documentation/ |
| H A D | glossary.txt | 42 Coherence (co): When one CPU's store to a given variable overwrites
44 there is said to be a coherence link from the second CPU to
47 It is also possible to have a coherence link within a CPU, which
48 is a "coherence internal" (coi) link. The term "coherence
115 See also "Coherence" and "Reads-from".
149 coherence and from-reads links.
156 See also Coherence" and "From-reads".
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| H A D | explanation.txt | 19 11. CACHE COHERENCE AND THE COHERENCE ORDER RELATION: co, coi, and coe
608 CACHE COHERENCE AND THE COHERENCE ORDER RELATION: co, coi, and coe
611 Cache coherence is a general principle requiring that in a
615 ordering which all the CPUs agree on (the coherence order), and this
619 To put it another way, for any variable x, the coherence order (co) of
622 comes first in the coherence order; the store which directly
626 You can think of the coherence order as being the order in which the
630 coherence order, that is, if the value stored by W gets overwritten,
633 Coherence order is required to be consistent with program order. This
636 Write-write coherence: If W ->po-loc W' (i.e., W comes before
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| /openbmc/linux/arch/mips/kernel/ |
| H A D | pm-cps.c | 393 * because they're needed in both the enable & disable coherence steps in cps_gen_entry_code()
412 * If this is the last VPE to become ready for non-coherence in cps_gen_entry_code()
421 * for non-coherence. It needs to wait until coherence in cps_gen_entry_code()
462 * disable coherence. At this point we *must* be sure that no other in cps_gen_entry_code()
489 /* Barrier to ensure write to coherence control is complete */ in cps_gen_entry_code()
494 /* Disable coherence */ in cps_gen_entry_code()
552 * VPEs which did not disable coherence will continue in cps_gen_entry_code()
553 * executing, after coherence has been disabled, from this in cps_gen_entry_code()
563 * Re-enable coherence. Note that for CPS_PM_NC_WAIT all coupled VPEs in cps_gen_entry_code()
564 * will run this. The first will actually re-enable coherence & the in cps_gen_entry_code()
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| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-firmware-sgi_uv | 35 The coherence_id entry contains the coherence id.
36 A partitioned UV system can have one or more coherence
37 domains. The coherence id indicates which coherence domain
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| /openbmc/linux/arch/mips/include/asm/ |
| H A D | mips-cm.h | 27 * This function returns the physical base address of the Coherence Manager
28 * global control block, or 0 if no Coherence Manager is present. It provides
60 * mips_cm_probe - probe for a Coherence Manager
62 * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
75 * mips_cm_present - determine whether a Coherence Manager is present
151 /* GCR_REV - Indicates the Coherence Manager revision */
290 /* GCR_Cx_COHERENCE - Controls core coherence */
291 GCR_CX_ACCESSOR_RW(32, 0x008, coherence)
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| H A D | mips-cps.h | 161 * zero if no Coherence Manager is present.
178 * if no Coherence Manager is present.
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| H A D | pm-cps.h | 11 * The CM & CPC can only handle coherence & power control on a per-core basis,
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| /openbmc/linux/tools/memory-model/litmus-tests/ |
| H A D | README | 6 Test of read-read coherence, that is, whether or not two
10 Test of read-write coherence, that is, whether or not a read
15 Test of write-read coherence, that is, whether or not a write
20 Test of write-write coherence, that is, whether or not two
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| H A D | CoWW+poonceonce.litmus | 6 * Test of write-write coherence, that is, whether or not two successive
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| H A D | CoRR+poonceonce+Once.litmus | 6 * Test of read-read coherence, that is, whether or not two successive
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| H A D | CoWR+poonceonce+Once.litmus | 6 * Test of write-read coherence, that is, whether or not a write to a
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| H A D | CoRW+poonceonce+Once.litmus | 6 * Test of read-write coherence, that is, whether or not a read from
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| H A D | Z6.0+pooncerelease+poacquirerelease+fencembonceonce.litmus | 10 * is a write-to-write link (AKA a "coherence" or just "co" link) and P2()
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| /openbmc/linux/arch/arm64/include/asm/ |
| H A D | cache.h | 103 * instruction to data coherence.
107 * 1 - dcache clean to PoU is not required for i-to-d coherence.
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| /openbmc/linux/tools/memory-model/ |
| H A D | linux-kernel.cat | 65 (* Fundamental coherence ordering *)
70 acyclic po-loc | com as coherence
204 (* Coherence requirements for plain accesses *)
208 empty (wr-incoh | rw-incoh | ww-incoh) as plain-coherence
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| H A D | README | 183 satisfy the model's "coherence", "atomic", "happens-before",
217 for generation of the possible reads-from and coherence order
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| /openbmc/linux/drivers/soc/hisilicon/ |
| H A D | Kconfig | 12 The Huawei Cache Coherence System (HCCS) is a multi-chip
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| /openbmc/u-boot/arch/mips/cpu/ |
| H A D | cm_init.S | 3 * MIPS Coherence Manager (CM) Initialisation
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| /openbmc/u-boot/arch/mips/include/asm/ |
| H A D | cm.h | 3 * MIPS Coherence Manager (CM) Register Definitions
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| /openbmc/u-boot/doc/ |
| H A D | README.mpc85xx-spin-table | 26 cache coherence.
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| /openbmc/u-boot/arch/powerpc/dts/ |
| H A D | e6500_power_isa.dtsi | 27 power-isa-mmc; // Memory Coherence
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| /openbmc/linux/arch/arm/mach-mvebu/ |
| H A D | coherency.c | 72 * The "Shared L2 Present" bit affects the "level of coherence" value
75 * that included in the defined level of coherence. When HW I/O
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| /openbmc/linux/Documentation/devicetree/bindings/perf/ |
| H A D | marvell-cn10k-tad.yaml | 13 The Tag-and-Data units (TADs) maintain coherence and contain CN10K
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| /openbmc/u-boot/arch/riscv/cpu/ax25/ |
| H A D | cache.c | 12 * Andes' AX25 does not have a coherence agent. U-Boot must use data in flush_dcache_all()
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| /openbmc/u-boot/arch/mips/ |
| H A D | Kconfig | 250 The physical base address at which to map the MIPS Coherence Manager
453 Select this if your system contains a MIPS Coherence Manager and you
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