xref: /openbmc/u-boot/arch/mips/Kconfig (revision 7e40d0a3)
1menu "MIPS architecture"
2	depends on MIPS
3
4config SYS_ARCH
5	default "mips"
6
7config SYS_CPU
8	default "mips32" if CPU_MIPS32
9	default "mips64" if CPU_MIPS64
10
11choice
12	prompt "Target select"
13	optional
14
15config TARGET_QEMU_MIPS
16	bool "Support qemu-mips"
17	select ROM_EXCEPTION_VECTORS
18	select SUPPORTS_BIG_ENDIAN
19	select SUPPORTS_CPU_MIPS32_R1
20	select SUPPORTS_CPU_MIPS32_R2
21	select SUPPORTS_CPU_MIPS64_R1
22	select SUPPORTS_CPU_MIPS64_R2
23	select SUPPORTS_LITTLE_ENDIAN
24
25config TARGET_MALTA
26	bool "Support malta"
27	select DM
28	select DM_SERIAL
29	select DYNAMIC_IO_PORT_BASE
30	select MIPS_CM
31	select MIPS_INSERT_BOOT_CONFIG
32	select MIPS_L1_CACHE_SHIFT_6
33	select MIPS_L2_CACHE
34	select OF_CONTROL
35	select OF_ISA_BUS
36	select ROM_EXCEPTION_VECTORS
37	select SUPPORTS_BIG_ENDIAN
38	select SUPPORTS_CPU_MIPS32_R1
39	select SUPPORTS_CPU_MIPS32_R2
40	select SUPPORTS_CPU_MIPS32_R6
41	select SUPPORTS_CPU_MIPS64_R1
42	select SUPPORTS_CPU_MIPS64_R2
43	select SUPPORTS_CPU_MIPS64_R6
44	select SUPPORTS_LITTLE_ENDIAN
45	select SWAP_IO_SPACE
46	imply CMD_DM
47
48config TARGET_VCT
49	bool "Support vct"
50	select ROM_EXCEPTION_VECTORS
51	select SUPPORTS_BIG_ENDIAN
52	select SUPPORTS_CPU_MIPS32_R1
53	select SUPPORTS_CPU_MIPS32_R2
54	select SYS_MIPS_CACHE_INIT_RAM_LOAD
55
56config ARCH_ATH79
57	bool "Support QCA/Atheros ath79"
58	select DM
59	select OF_CONTROL
60	imply CMD_DM
61
62config ARCH_MSCC
63	bool "Support MSCC VCore-III"
64	select OF_CONTROL
65	select DM
66
67config ARCH_BMIPS
68	bool "Support BMIPS SoCs"
69	select CLK
70	select CPU
71	select DM
72	select OF_CONTROL
73	select RAM
74	select SYSRESET
75	imply CMD_DM
76
77config ARCH_MT7620
78	bool "Support MT7620/7688 SoCs"
79	imply CMD_DM
80	select DISPLAY_CPUINFO
81	select DM
82	imply DM_ETH
83	imply DM_GPIO
84	select DM_SERIAL
85	imply DM_SPI
86	imply DM_SPI_FLASH
87	select ARCH_MISC_INIT
88	select MIPS_TUNE_24KC
89	select OF_CONTROL
90	select ROM_EXCEPTION_VECTORS
91	select SUPPORTS_CPU_MIPS32_R1
92	select SUPPORTS_CPU_MIPS32_R2
93	select SUPPORTS_LITTLE_ENDIAN
94	select SYSRESET
95
96config ARCH_JZ47XX
97	bool "Support Ingenic JZ47xx"
98	select SUPPORT_SPL
99	select OF_CONTROL
100	select DM
101
102config MACH_PIC32
103	bool "Support Microchip PIC32"
104	select DM
105	select OF_CONTROL
106	imply CMD_DM
107
108config TARGET_BOSTON
109	bool "Support Boston"
110	select DM
111	select DM_SERIAL
112	select MIPS_CM
113	select MIPS_L1_CACHE_SHIFT_6
114	select MIPS_L2_CACHE
115	select OF_BOARD_SETUP
116	select OF_CONTROL
117	select ROM_EXCEPTION_VECTORS
118	select SUPPORTS_BIG_ENDIAN
119	select SUPPORTS_CPU_MIPS32_R1
120	select SUPPORTS_CPU_MIPS32_R2
121	select SUPPORTS_CPU_MIPS32_R6
122	select SUPPORTS_CPU_MIPS64_R1
123	select SUPPORTS_CPU_MIPS64_R2
124	select SUPPORTS_CPU_MIPS64_R6
125	select SUPPORTS_LITTLE_ENDIAN
126	imply CMD_DM
127
128config TARGET_XILFPGA
129	bool "Support Imagination Xilfpga"
130	select DM
131	select DM_ETH
132	select DM_GPIO
133	select DM_SERIAL
134	select MIPS_L1_CACHE_SHIFT_4
135	select OF_CONTROL
136	select ROM_EXCEPTION_VECTORS
137	select SUPPORTS_CPU_MIPS32_R1
138	select SUPPORTS_CPU_MIPS32_R2
139	select SUPPORTS_LITTLE_ENDIAN
140	imply CMD_DM
141	help
142	  This supports IMGTEC MIPSfpga platform
143
144endchoice
145
146source "board/imgtec/boston/Kconfig"
147source "board/imgtec/malta/Kconfig"
148source "board/imgtec/xilfpga/Kconfig"
149source "board/micronas/vct/Kconfig"
150source "board/qemu-mips/Kconfig"
151source "arch/mips/mach-ath79/Kconfig"
152source "arch/mips/mach-mscc/Kconfig"
153source "arch/mips/mach-bmips/Kconfig"
154source "arch/mips/mach-jz47xx/Kconfig"
155source "arch/mips/mach-pic32/Kconfig"
156source "arch/mips/mach-mt7620/Kconfig"
157
158if MIPS
159
160choice
161	prompt "Endianness selection"
162	help
163	  Some MIPS boards can be configured for either little or big endian
164	  byte order. These modes require different U-Boot images. In general there
165	  is one preferred byteorder for a particular system but some systems are
166	  just as commonly used in the one or the other endianness.
167
168config SYS_BIG_ENDIAN
169	bool "Big endian"
170	depends on SUPPORTS_BIG_ENDIAN
171
172config SYS_LITTLE_ENDIAN
173	bool "Little endian"
174	depends on SUPPORTS_LITTLE_ENDIAN
175
176endchoice
177
178choice
179	prompt "CPU selection"
180	default CPU_MIPS32_R2
181
182config CPU_MIPS32_R1
183	bool "MIPS32 Release 1"
184	depends on SUPPORTS_CPU_MIPS32_R1
185	select 32BIT
186	help
187	  Choose this option to build an U-Boot for release 1 through 5 of the
188	  MIPS32 architecture.
189
190config CPU_MIPS32_R2
191	bool "MIPS32 Release 2"
192	depends on SUPPORTS_CPU_MIPS32_R2
193	select 32BIT
194	help
195	  Choose this option to build an U-Boot for release 2 through 5 of the
196	  MIPS32 architecture.
197
198config CPU_MIPS32_R6
199	bool "MIPS32 Release 6"
200	depends on SUPPORTS_CPU_MIPS32_R6
201	select 32BIT
202	help
203	  Choose this option to build an U-Boot for release 6 or later of the
204	  MIPS32 architecture.
205
206config CPU_MIPS64_R1
207	bool "MIPS64 Release 1"
208	depends on SUPPORTS_CPU_MIPS64_R1
209	select 64BIT
210	help
211	  Choose this option to build a kernel for release 1 through 5 of the
212	  MIPS64 architecture.
213
214config CPU_MIPS64_R2
215	bool "MIPS64 Release 2"
216	depends on SUPPORTS_CPU_MIPS64_R2
217	select 64BIT
218	help
219	  Choose this option to build a kernel for release 2 through 5 of the
220	  MIPS64 architecture.
221
222config CPU_MIPS64_R6
223	bool "MIPS64 Release 6"
224	depends on SUPPORTS_CPU_MIPS64_R6
225	select 64BIT
226	help
227	  Choose this option to build a kernel for release 6 or later of the
228	  MIPS64 architecture.
229
230endchoice
231
232menu "General setup"
233
234config ROM_EXCEPTION_VECTORS
235	bool "Build U-Boot image with exception vectors"
236	help
237	  Enable this to include exception vectors in the U-Boot image. This is
238	  required if the U-Boot entry point is equal to the address of the
239	  CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
240	  U-Boot booted from parallel NOR flash).
241	  Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
242	  In that case the image size will be reduced by 0x500 bytes.
243
244config MIPS_CM_BASE
245	hex "MIPS CM GCR Base Address"
246	depends on MIPS_CM
247	default 0x16100000 if TARGET_BOSTON
248	default 0x1fbf8000
249	help
250	  The physical base address at which to map the MIPS Coherence Manager
251	  Global Configuration Registers (GCRs). This should be set such that
252	  the GCRs occupy a region of the physical address space which is
253	  otherwise unused, or at minimum that software doesn't need to access.
254
255config MIPS_CACHE_INDEX_BASE
256	hex "Index base address for cache initialisation"
257	default 0x80000000 if CPU_MIPS32
258	default 0xffffffff80000000 if CPU_MIPS64
259	help
260	  This is the base address for a memory block, which is used for
261	  initialising the cache lines. This is also the base address of a memory
262	  block which is used for loading and filling cache lines when
263	  SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
264	  Normally this is CKSEG0. If the MIPS system needs to move this block
265	  to some SRAM or ScratchPad RAM, adapt this option accordingly.
266
267config MIPS_RELOCATION_TABLE_SIZE
268	hex "Relocation table size"
269	range 0x100 0x10000
270	default "0x8000"
271	---help---
272	  A table of relocation data will be appended to the U-Boot binary
273	  and parsed in relocate_code() to fix up all offsets in the relocated
274	  U-Boot.
275
276	  This option allows the amount of space reserved for the table to be
277	  adjusted in a range from 256 up to 64k. The default is 32k and should
278	  be ok in most cases. Reduce this value to shrink the size of U-Boot
279	  binary.
280
281	  The build will fail and a valid size suggested if this is too small.
282
283	  If unsure, leave at the default value.
284
285endmenu
286
287menu "OS boot interface"
288
289config MIPS_BOOT_CMDLINE_LEGACY
290	bool "Hand over legacy command line to Linux kernel"
291	default y
292	help
293	  Enable this option if you want U-Boot to hand over the Yamon-style
294	  command line to the kernel. All bootargs will be prepared as argc/argv
295	  compatible list. The argument count (argc) is stored in register $a0.
296	  The address of the argument list (argv) is stored in register $a1.
297
298config MIPS_BOOT_ENV_LEGACY
299	bool "Hand over legacy environment to Linux kernel"
300	default y
301	help
302	  Enable this option if you want U-Boot to hand over the Yamon-style
303	  environment to the kernel. Information like memory size, initrd
304	  address and size will be prepared as zero-terminated key/value list.
305	  The address of the environment is stored in register $a2.
306
307config MIPS_BOOT_FDT
308	bool "Hand over a flattened device tree to Linux kernel"
309	default n
310	help
311	  Enable this option if you want U-Boot to hand over a flattened
312	  device tree to the kernel. According to UHI register $a0 will be set
313	  to -2 and the FDT address is stored in $a1.
314
315endmenu
316
317config SUPPORTS_BIG_ENDIAN
318	bool
319
320config SUPPORTS_LITTLE_ENDIAN
321	bool
322
323config SUPPORTS_CPU_MIPS32_R1
324	bool
325
326config SUPPORTS_CPU_MIPS32_R2
327	bool
328
329config SUPPORTS_CPU_MIPS32_R6
330	bool
331
332config SUPPORTS_CPU_MIPS64_R1
333	bool
334
335config SUPPORTS_CPU_MIPS64_R2
336	bool
337
338config SUPPORTS_CPU_MIPS64_R6
339	bool
340
341config CPU_MIPS32
342	bool
343	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
344
345config CPU_MIPS64
346	bool
347	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
348
349config MIPS_TUNE_4KC
350	bool
351
352config MIPS_TUNE_14KC
353	bool
354
355config MIPS_TUNE_24KC
356	bool
357
358config MIPS_TUNE_34KC
359	bool
360
361config MIPS_TUNE_74KC
362	bool
363
364config 32BIT
365	bool
366
367config 64BIT
368	bool
369
370config SWAP_IO_SPACE
371	bool
372
373config SYS_MIPS_CACHE_INIT_RAM_LOAD
374	bool
375
376config MIPS_INIT_STACK_IN_SRAM
377	bool
378	default n
379	help
380	  Select this if the initial stack frame could be setup in SRAM.
381	  Normally the initial stack frame is set up in DRAM which is often
382	  only available after lowlevel_init. With this option the initial
383	  stack frame and the early C environment is set up before
384	  lowlevel_init. Thus lowlevel_init does not need to be implemented
385	  in assembler.
386
387config SYS_DCACHE_SIZE
388	int
389	default 0
390	help
391	  The total size of the L1 Dcache, if known at compile time.
392
393config SYS_DCACHE_LINE_SIZE
394	int
395	default 0
396	help
397	  The size of L1 Dcache lines, if known at compile time.
398
399config SYS_ICACHE_SIZE
400	int
401	default 0
402	help
403	  The total size of the L1 ICache, if known at compile time.
404
405config SYS_ICACHE_LINE_SIZE
406	int
407	default 0
408	help
409	  The size of L1 Icache lines, if known at compile time.
410
411config SYS_CACHE_SIZE_AUTO
412	def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
413		SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
414	help
415	  Select this (or let it be auto-selected by not defining any cache
416	  sizes) in order to allow U-Boot to automatically detect the sizes
417	  of caches at runtime. This has a small cost in code size & runtime
418	  so if you know the cache configuration for your system at compile
419	  time it would be beneficial to configure it.
420
421config MIPS_L1_CACHE_SHIFT_4
422	bool
423
424config MIPS_L1_CACHE_SHIFT_5
425	bool
426
427config MIPS_L1_CACHE_SHIFT_6
428	bool
429
430config MIPS_L1_CACHE_SHIFT_7
431	bool
432
433config MIPS_L1_CACHE_SHIFT
434	int
435	default "7" if MIPS_L1_CACHE_SHIFT_7
436	default "6" if MIPS_L1_CACHE_SHIFT_6
437	default "5" if MIPS_L1_CACHE_SHIFT_5
438	default "4" if MIPS_L1_CACHE_SHIFT_4
439	default "5"
440
441config MIPS_L2_CACHE
442	bool
443	help
444	  Select this if your system includes an L2 cache and you want U-Boot
445	  to initialise & maintain it.
446
447config DYNAMIC_IO_PORT_BASE
448	bool
449
450config MIPS_CM
451	bool
452	help
453	  Select this if your system contains a MIPS Coherence Manager and you
454	  wish U-Boot to configure it or make use of it to retrieve system
455	  information such as cache configuration.
456
457config MIPS_INSERT_BOOT_CONFIG
458	bool
459	default n
460	help
461	  Enable this to insert some board-specific boot configuration in
462	  the U-Boot binary at offset 0x10.
463
464config MIPS_BOOT_CONFIG_WORD0
465	hex
466	depends on MIPS_INSERT_BOOT_CONFIG
467	default 0x420 if TARGET_MALTA
468	default 0x0
469	help
470	  Value which is inserted as boot config word 0.
471
472config MIPS_BOOT_CONFIG_WORD1
473	hex
474	depends on MIPS_INSERT_BOOT_CONFIG
475	default 0x0
476	help
477	  Value which is inserted as boot config word 1.
478
479endif
480
481endmenu
482