1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
5 */
6
7 #include <common.h>
8
flush_dcache_all(void)9 void flush_dcache_all(void)
10 {
11 /*
12 * Andes' AX25 does not have a coherence agent. U-Boot must use data
13 * cache flush and invalidate functions to keep data in the system
14 * coherent.
15 * The implementation of the fence instruction in the AX25 flushes the
16 * data cache and is used for this purpose.
17 */
18 asm volatile ("fence" ::: "memory");
19 }
20
flush_dcache_range(unsigned long start,unsigned long end)21 void flush_dcache_range(unsigned long start, unsigned long end)
22 {
23 flush_dcache_all();
24 }
25
invalidate_dcache_range(unsigned long start,unsigned long end)26 void invalidate_dcache_range(unsigned long start, unsigned long end)
27 {
28 flush_dcache_all();
29 }
30
icache_enable(void)31 void icache_enable(void)
32 {
33 #ifndef CONFIG_SYS_ICACHE_OFF
34 #ifdef CONFIG_RISCV_NDS_CACHE
35 asm volatile (
36 "csrr t1, mcache_ctl\n\t"
37 "ori t0, t1, 0x1\n\t"
38 "csrw mcache_ctl, t0\n\t"
39 );
40 #endif
41 #endif
42 }
43
icache_disable(void)44 void icache_disable(void)
45 {
46 #ifndef CONFIG_SYS_ICACHE_OFF
47 #ifdef CONFIG_RISCV_NDS_CACHE
48 asm volatile (
49 "fence.i\n\t"
50 "csrr t1, mcache_ctl\n\t"
51 "andi t0, t1, ~0x1\n\t"
52 "csrw mcache_ctl, t0\n\t"
53 );
54 #endif
55 #endif
56 }
57
dcache_enable(void)58 void dcache_enable(void)
59 {
60 #ifndef CONFIG_SYS_DCACHE_OFF
61 #ifdef CONFIG_RISCV_NDS_CACHE
62 asm volatile (
63 "csrr t1, mcache_ctl\n\t"
64 "ori t0, t1, 0x2\n\t"
65 "csrw mcache_ctl, t0\n\t"
66 );
67 #endif
68 #endif
69 }
70
dcache_disable(void)71 void dcache_disable(void)
72 {
73 #ifndef CONFIG_SYS_DCACHE_OFF
74 #ifdef CONFIG_RISCV_NDS_CACHE
75 asm volatile (
76 "fence\n\t"
77 "csrr t1, mcache_ctl\n\t"
78 "andi t0, t1, ~0x2\n\t"
79 "csrw mcache_ctl, t0\n\t"
80 );
81 #endif
82 #endif
83 }
84
icache_status(void)85 int icache_status(void)
86 {
87 int ret = 0;
88
89 #ifdef CONFIG_RISCV_NDS_CACHE
90 asm volatile (
91 "csrr t1, mcache_ctl\n\t"
92 "andi %0, t1, 0x01\n\t"
93 : "=r" (ret)
94 :
95 : "memory"
96 );
97 #endif
98
99 return ret;
100 }
101
dcache_status(void)102 int dcache_status(void)
103 {
104 int ret = 0;
105
106 #ifdef CONFIG_RISCV_NDS_CACHE
107 asm volatile (
108 "csrr t1, mcache_ctl\n\t"
109 "andi %0, t1, 0x02\n\t"
110 : "=r" (ret)
111 :
112 : "memory"
113 );
114 #endif
115
116 return ret;
117 }
118