/openbmc/linux/drivers/clk/ |
H A D | clk-fixed-factor.c | 1 // SPDX-License-Identifier: GPL-2.0 6 #include <linux/clk-provider.h> 13 * DOC: basic fixed multiplier and divider clock that cannot gate 15 * Traits of this clock: 16 * prepare - clk_prepare only ensures that parents are prepared 17 * enable - clk_enable only ensures that parents are enabled 18 * rate - rate is fixed. clk->rate = parent->rate / div * mult 19 * parent - fixed parent. No clk_set_parent support 28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate() 29 do_div(rate, fix->div); in clk_factor_recalc_rate() [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | am33xx-clocks.dtsi | 2 * Device Tree Source for AM33xx clock data 12 #clock-cells = <0>; 13 compatible = "ti,mux-clock"; 15 ti,bit-shift = <22>; 20 #clock-cells = <0>; 21 compatible = "fixed-factor-clock"; 23 clock-mult = <1>; 24 clock-div = <1>; 28 #clock-cells = <0>; 29 compatible = "fixed-factor-clock"; [all …]
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H A D | omap36xx-omap3430es2plus-clocks.dtsi | 2 * Device Tree Source for OMAP34xx/OMAP36xx clock data 12 #clock-cells = <0>; 13 compatible = "ti,composite-no-wait-gate-clock"; 15 ti,bit-shift = <0>; 20 #clock-cells = <0>; 21 compatible = "ti,composite-divider-clock"; 23 ti,bit-shift = <8>; 29 #clock-cells = <0>; 30 compatible = "ti,composite-clock"; 35 #clock-cells = <0>; [all …]
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H A D | am43xx-clocks.dtsi | 2 * Device Tree Source for AM43xx clock data 12 #clock-cells = <0>; 13 compatible = "ti,mux-clock"; 15 ti,bit-shift = <31>; 20 #clock-cells = <0>; 21 compatible = "ti,mux-clock"; 23 ti,bit-shift = <29>; 28 #clock-cells = <0>; 29 compatible = "ti,mux-clock"; 31 ti,bit-shift = <22>; [all …]
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H A D | keystone-clocks.dtsi | 2 * Device Tree Source for Keystone 2 clock tree 12 #address-cells = <1>; 13 #size-cells = <1>; 17 #clock-cells = <0>; 18 compatible = "ti,keystone,pll-mux-clock"; 21 bit-shift = <23>; 22 bit-mask = <1>; 23 clock-output-names = "mainmuxclk"; 27 #clock-cells = <0>; 28 compatible = "fixed-factor-clock"; [all …]
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H A D | omap3xxx-clocks.dtsi | 2 * Device Tree Source for OMAP3 clock data 12 #clock-cells = <0>; 13 compatible = "fixed-clock"; 14 clock-frequency = <16800000>; 18 #clock-cells = <0>; 19 compatible = "ti,mux-clock"; 25 #clock-cells = <0>; 26 compatible = "ti,divider-clock"; 28 ti,bit-shift = <6>; 29 ti,max-div = <3>; [all …]
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H A D | omap36xx-clocks.dtsi | 2 * Device Tree Source for OMAP36xx clock data 12 #clock-cells = <0>; 13 compatible = "ti,omap3-dpll-per-j-type-clock"; 19 #clock-cells = <0>; 20 compatible = "ti,hsdiv-gate-clock"; 22 ti,bit-shift = <0x1e>; 24 ti,set-rate-parent; 25 ti,set-bit-to-disable; 29 #clock-cells = <0>; 30 compatible = "ti,hsdiv-gate-clock"; [all …]
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H A D | omap36xx-am35xx-omap3430es2plus-clocks.dtsi | 2 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data 12 #clock-cells = <0>; 13 compatible = "fixed-factor-clock"; 15 clock-mult = <1>; 16 clock-div = <3>; 20 #clock-cells = <0>; 21 compatible = "fixed-factor-clock"; 23 clock-mult = <1>; 24 clock-div = <5>; 29 #clock-cells = <0>; [all …]
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/openbmc/linux/drivers/clk/renesas/ |
H A D | rcar-gen3-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * R-Car Gen3 Clock Pulse Generator 5 * Copyright (C) 2015-2018 Glider bvba 8 * Based on clk-rcar-gen3.c 16 #include <linux/clk-provider.h> 25 #include "renesas-cpg-mssr.h" 26 #include "rcar-cpg-lib.h" 27 #include "rcar-gen3-cpg.h" 37 #define CPG_PLLnCR_STC_MASK GENMASK(30, 24) /* PLL Circuit Mult. Ratio */ 39 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */ [all …]
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H A D | rcar-gen4-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * R-Car Gen4 Clock Pulse Generator 7 * Based on rcar-gen3-cpg.c 9 * Copyright (C) 2015-2018 Glider bvba 15 #include <linux/clk-provider.h> 23 #include "renesas-cpg-mssr.h" 24 #include "rcar-gen4-cpg.h" 25 #include "rcar-cpg-lib.h" 33 #define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \ 48 #define CPG_PLLxCR0_NI GENMASK(27, 20) /* Integer mult. factor */ [all …]
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H A D | rcar-gen2-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * R-Car Gen2 Clock Pulse Generator 10 #include <linux/clk-provider.h> 18 #include "renesas-cpg-mssr.h" 19 #include "rcar-gen2-cpg.h" 36 * Z Clock 38 * Traits of this clock: 39 * prepare - clk_prepare only ensures that parents are prepared 40 * enable - clk_enable only ensures that parents are enabled 41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32 [all …]
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/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | omap36xx-omap3430es2plus-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Device Tree Source for OMAP34xx/OMAP36xx clock data 8 clock@a00 { 11 #clock-cells = <2>; 12 #address-cells = <0>; 14 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 { 15 #clock-cells = <0>; 16 compatible = "ti,composite-no-wait-gate-clock"; 17 clock-output-names = "ssi_ssr_gate_fck_3430es2"; 19 ti,bit-shift = <0>; [all …]
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H A D | am33xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Device Tree Source for AM33xx clock data 8 sys_clkin_ck: clock-sys-clkin-22@40 { 9 #clock-cells = <0>; 10 compatible = "ti,mux-clock"; 11 clock-output-names = "sys_clkin_ck"; 13 ti,bit-shift = <22>; 17 adc_tsc_fck: clock-adc-tsc-fck { 18 #clock-cells = <0>; 19 compatible = "fixed-factor-clock"; [all …]
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H A D | am43xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Device Tree Source for AM43xx clock data 8 sys_clkin_ck: clock-sys-clkin-31@40 { 9 #clock-cells = <0>; 10 compatible = "ti,mux-clock"; 11 clock-output-names = "sys_clkin_ck"; 13 ti,bit-shift = <31>; 17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 { 18 #clock-cells = <0>; 19 compatible = "ti,mux-clock"; [all …]
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H A D | omap36xx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Device Tree Source for OMAP36xx clock data 9 #clock-cells = <0>; 10 compatible = "ti,omap3-dpll-per-j-type-clock"; 16 #clock-cells = <0>; 17 compatible = "ti,hsdiv-gate-clock"; 19 ti,bit-shift = <0x1e>; 21 ti,set-rate-parent; 22 ti,set-bit-to-disable; 26 #clock-cells = <0>; [all …]
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H A D | omap3xxx-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Device Tree Source for OMAP3 clock data 9 #clock-cells = <0>; 10 compatible = "fixed-clock"; 11 clock-frequency = <16800000>; 15 #clock-cells = <0>; 16 compatible = "ti,mux-clock"; 22 #clock-cells = <0>; 23 compatible = "ti,divider-clock"; 25 ti,bit-shift = <6>; [all …]
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H A D | omap36xx-am35xx-omap3430es2plus-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data 9 #clock-cells = <0>; 10 compatible = "fixed-factor-clock"; 12 clock-mult = <1>; 13 clock-div = <3>; 17 #clock-cells = <0>; 18 compatible = "fixed-factor-clock"; 20 clock-mult = <1>; 21 clock-div = <5>; [all …]
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/openbmc/linux/arch/arm64/boot/dts/broadcom/stingray/ |
H A D | stingray-clock.dtsi | 4 * Copyright(c) 2016-2017 Broadcom. All rights reserved. 33 #include <dt-bindings/clock/bcm-sr.h> 36 #clock-cells = <0>; 37 compatible = "fixed-clock"; 38 clock-frequency = <50000000>; 42 #clock-cells = <0>; 43 compatible = "fixed-factor-clock"; 45 clock-div = <2>; 46 clock-mult = <1>; 50 #clock-cells = <1>; [all …]
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/openbmc/linux/drivers/clk/sunxi/ |
H A D | clk-a10-pll2.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 7 * Maxime Ripard <maxime.ripard@free-electrons.com> 10 #include <linux/clk-provider.h> 16 #include <dt-bindings/clock/sun4i-a10-pll2.h> 22 #define SUN4I_PLL2_PRE_DIV_MASK GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0) 26 #define SUN4I_PLL2_N_MASK GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0) 30 #define SUN4I_PLL2_POST_DIV_MASK GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0) 41 const char *clk_name = node->name, *parent; in sun4i_pll2_setup() 44 struct clk_multiplier *mult; in sun4i_pll2_setup() local 62 prediv_clk = clk_register_divider(NULL, "pll2-prediv", in sun4i_pll2_setup() [all …]
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H A D | clk-sun4i-pll3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 5 * Maxime Ripard <maxime.ripard@free-electrons.com> 8 #include <linux/clk-provider.h> 23 const char *clk_name = node->name, *parent; in sun4i_a10_pll3_setup() 24 struct clk_multiplier *mult; in sun4i_a10_pll3_setup() local 31 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_pll3_setup() 36 pr_err("%s: Could not map the clock registers\n", clk_name); in sun4i_a10_pll3_setup() 44 gate->reg = reg; in sun4i_a10_pll3_setup() 45 gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT; in sun4i_a10_pll3_setup() 46 gate->lock = &sun4i_a10_pll3_lock; in sun4i_a10_pll3_setup() [all …]
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/openbmc/linux/arch/arm/boot/dts/ti/keystone/ |
H A D | keystone-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Device Tree Source for Keystone 2 clock tree 5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ 9 #address-cells = <1>; 10 #size-cells = <1>; 14 #clock-cells = <0>; 15 compatible = "ti,keystone,pll-mux-clock"; 18 bit-shift = <23>; 19 bit-mask = <1>; 20 clock-output-names = "mainmuxclk"; [all …]
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/openbmc/linux/drivers/clk/ti/ |
H A D | fixed-factor.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * TI Fixed Factor Clock 7 * Tero Kristo <t-kristo@ti.com> 10 #include <linux/clk-provider.h> 17 #include "clock.h" 23 * of_ti_fixed_factor_clk_setup - Setup function for TI fixed factor clock 24 * @node: device node for this clock 26 * Sets up a simple fixed factor clock based on device tree info. 33 u32 div, mult; in of_ti_fixed_factor_clk_setup() local 36 if (of_property_read_u32(node, "ti,clock-div", &div)) { in of_ti_fixed_factor_clk_setup() [all …]
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/openbmc/linux/drivers/clk/mvebu/ |
H A D | orion.c | 1 // SPDX-License-Identifier: GPL-2.0 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 12 #include <linux/clk-provider.h> 60 int *mult, int *div) in mv88f5181_get_clk_ratio() argument 65 *mult = 1; in mv88f5181_get_clk_ratio() 68 *mult = 1; in mv88f5181_get_clk_ratio() 71 *mult = 0; in mv88f5181_get_clk_ratio() 89 CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init); 128 int *mult, int *div) in mv88f5182_get_clk_ratio() argument 133 *mult = 1; in mv88f5182_get_clk_ratio() [all …]
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/openbmc/linux/arch/arm/boot/dts/arm/ |
H A D | mps2.dtsi | 6 * This file is dual-licensed: you can use it either under the terms 45 #include "../armv7-m.dtsi" 48 #address-cells = <1>; 49 #size-cells = <1>; 51 oscclk0: clk-osc0 { 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 clock-frequency = <50000000>; 57 oscclk1: clk-osc1 { 58 compatible = "fixed-clock"; [all …]
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/openbmc/linux/arch/arm/mach-omap2/ |
H A D | clkt2xxx_dpllcore.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * DPLL + CORE_CLK composite clock functions 5 * Copyright (C) 2005-2008 Texas Instruments, Inc. 6 * Copyright (C) 2004-2010 Nokia Corporation 9 * Richard Woodruff <r-woodruff2@ti.com> 15 * XXX The DPLL and CORE clocks should be split into two separate clock 26 #include "clock.h" 30 #include "cm-regbits-24xx.h" 38 * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set 44 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate [all …]
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