Home
last modified time | relevance | path

Searched +full:clock +full:- +full:controller (Results 1 – 25 of 1057) sorted by relevance

12345678910>>...43

/openbmc/linux/drivers/clk/qcom/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 tristate "Support for Qualcomm's clock controllers"
40 tristate "MSM8916 APCS Clock Controller"
43 Support for the APCS Clock Controller on msm8916 devices. The
49 tristate "MSM8996 CPU Clock Controller"
54 Support for the CPU clock controller on msm8996 devices.
55 Say Y if you want to support CPU clock scaling using CPUfreq
59 tristate "SDX55 and SDX65 APCS Clock Controller"
63 Support for the APCS Clock Controller on SDX55, SDX65 platforms. The
69 tristate "RPM based Clock Controller"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,mt8195-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Functional Clock Controller for MT8195
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The clock architecture in Mediatek like below
14 PLLs -->
15 dividers -->
17 -->
[all …]
H A Dmediatek,mt8192-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Functional Clock Controller for MT8192
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The Mediatek functional clock controller provides various clocks on MT8192.
18 - enum:
19 - mediatek,mt8192-scp_adsp
20 - mediatek,mt8192-imp_iic_wrap_c
[all …]
/openbmc/linux/drivers/clk/samsung/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 bool "Samsung Exynos clock controller support" if COMPILE_TEST
18 bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
21 Support for the clock controller present on the Samsung S3C64xx SoCs.
25 bool "Samsung S5Pv210 clock controller support" if COMPILE_TEST
28 Support for the clock controller present on the Samsung S5Pv210 SoCs.
32 bool "Samsung Exynos3250 clock controller support" if COMPILE_TEST
35 Support for the clock controller present on the Samsung
39 bool "Samsung Exynos4 clock controller support" if COMPILE_TEST
42 Support for the clock controller present on the Samsung
[all …]
/openbmc/linux/drivers/clk/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
2 # common clock support for ROCKCHIP SoC family.
5 bool "Rockchip clock controller common support"
9 Say y here to enable common clock controller for Rockchip platforms.
13 bool "Rockchip PX30 clock controller support"
17 Build the driver for PX30 Clock Driver.
20 bool "Rockchip RV110x clock controller support"
24 Build the driver for RV110x Clock Driver.
27 bool "Rockchip RV1126 clock controller support"
31 Build the driver for RV1126 Clock Driver.
[all …]
/openbmc/linux/arch/arm/boot/dts/hisilicon/
H A Dhisi-x5hd2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2014 Linaro Ltd.
4 * Copyright (c) 2013-2014 HiSilicon Limited.
7 #include <dt-bindings/clock/hix5hd2-clock.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
17 gic: interrupt-controller@f8a01000 {
18 compatible = "arm,cortex-a9-gic";
19 #interrupt-cells = <3>;
20 #address-cells = <0>;
[all …]
H A Dhi3620.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2013 HiSilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dpistachio-clock.txt1 Imagination Technologies Pistachio SoC clock controllers
4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
6 from the device-tree.
9 ----------------
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
[all …]
H A Dnuvoton,npcm750-clk.txt1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
30 Example: Clock controller node:
[all …]
H A Dsamsung,s3c64xx-clock.txt1 * Samsung S3C64xx Clock Controller
3 The S3C64xx clock controller generates and supplies clock to various controllers
4 within the SoC. The clock binding described here is applicable to all SoCs in
9 - compatible: should be one of the following.
10 - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
11 - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.
13 - reg: physical base address of the controller and length of memory mapped
16 - #clock-cells: should be 1.
18 Each clock is assigned an identifier and client nodes can use this identifier
19 to specify the clock which they consume. Some of the clocks are available only
[all …]
H A Drockchip,rk3328-cru.txt1 * Rockchip RK3328 Clock and Reset Unit
3 The RK3328 clock controller generates and supplies clock to various
4 controllers within the SoC and also implements a reset controller for SoC
9 - compatible: should be "rockchip,rk3328-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
20 Each clock is assigned an identifier and client nodes can use this identifier
21 to specify the clock which they consume. All available clocks are defined as
[all …]
/openbmc/u-boot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
7 - #address-cells: The number of cells used to represent physical base addresses
9 - #size-cells: The number of cells used to represent the size of an address
11 - ranges: The mapping of the host1x address space to the CPU address space.
12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
14 - resets: Must contain an entry for each entry in reset-names.
16 - reset-names: Must include the following entries:
[all …]
/openbmc/linux/include/soc/canaan/
H A Dk210-sysctl.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
10 * Kendryte K210 SoC system controller registers offsets.
11 * Taken from Kendryte SDK (kendryte-standalone-sdk).
15 #define K210_SYSCTL_PLL0 0x08 /* PLL0 controller */
16 #define K210_SYSCTL_PLL1 0x0C /* PLL1 controller */
17 #define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */
20 #define K210_SYSCTL_SEL0 0x20 /* Clock select controller 0 */
21 #define K210_SYSCTL_SEL1 0x24 /* Clock select controller 1 */
22 #define K210_SYSCTL_EN_CENT 0x28 /* Central clock enable */
[all …]
/openbmc/linux/drivers/clk/meson/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "Clock support for Amlogic platforms"
52 bool "Meson8 SoC Clock controller support"
62 Support for the clock controller on AmLogic S802 (Meson8),
67 tristate "GXBB and GXL SoC clock controllers support"
79 Support for the clock controller on AmLogic S905 devices, aka gxbb.
83 tristate "AXG SoC clock controllers support"
94 Support for the clock controller on AmLogic A113D devices, aka axg.
98 tristate "Meson AXG Audio Clock Controller Driver"
106 Support for the audio clock controller on AmLogic A113D devices,
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-lsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 lsio_mem_clk: clock-lsio-mem {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/hi3670-clock.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
27 cpu-map {
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6779.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/clock/mt6779-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/mt6779-pinfunc.h>
15 interrupt-parent = <&sysirq>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 compatible = "arm,psci-0.2";
25 #address-cells = <1>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/lg/
H A Dlg1312.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a53";
26 next-level-cache = <&L2_0>;
[all …]
H A Dlg1313.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a53";
26 next-level-cache = <&L2_0>;
[all …]
/openbmc/linux/Documentation/gpu/amdgpu/display/
H A Ddc-glossary.rst7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
34 * PCLK: Pixel Clock
35 * SYMCLK: Symbol Clock
36 * SOCCLK: GPU Engine Clock
37 * DISPCLK: Display Clock
38 * DPPCLK: DPP Clock
39 * DCFCLK: Display Controller Fabric Clock
40 * REFCLK: Real Time Reference Clock
42 * FCLK: Fabric Clock
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dcanaan,k210-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan Kendryte K210 System Controller
10 - Damien Le Moal <dlemoal@kernel.org>
13 Canaan Inc. Kendryte K210 SoC system controller which provides a
20 - const: canaan,k210-sysctl
21 - const: syscon
22 - const: simple-mfd
[all …]
/openbmc/linux/drivers/clk/starfive/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 bool "StarFive JH7100 clock support"
12 Say yes here to support the clock controller on the StarFive JH7100
16 tristate "StarFive JH7100 audio clock support"
25 bool "StarFive JH7110 PLL clock support"
29 Say yes here to support the PLL clock controller on the
33 bool "StarFive JH7110 system clock support"
41 Say yes here to support the system clock controller on the
45 tristate "StarFive JH7110 always-on clock support"
49 Say yes here to support the always-on clock controller on the
[all …]
/openbmc/linux/arch/mips/boot/dts/ingenic/
H A Djz4740.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
16 compatible = "ingenic,xburst-mxu1.0";
20 clock-names = "cpu";
24 cpuintc: interrupt-controller {
[all …]
H A Djz4770.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
20 clock-names = "cpu";
24 cpuintc: interrupt-controller {
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "../../armv7-m.dtsi"
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/imxrt1050-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <24000000>;
[all …]

12345678910>>...43