dts/freescale/imx8-ss-lsio.dtsi

1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 	compatible = "simple-bus";
12 	#address-cells = <1>;
13 	#size-cells = <1>;
17 	lsio_mem_clk: clock-lsio-mem {
18 		compatible = "fixed-clock";
19 		#clock-cells = <0>;
20 		clock-frequency = <200000000>;
21 		clock-output-names = "lsio_mem_clk";
24 	lsio_bus_clk: clock-lsio-bus {
25 		compatible = "fixed-clock";
26 		#clock-cells = <0>;
27 		clock-frequency = <100000000>;
28 		clock-output-names = "lsio_bus_clk";
32 		compatible = "fsl,imx27-pwm";
34 		clock-names = "ipg", "per";
37 		assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
38 		assigned-clock-rates = <24000000>;
39 		#pwm-cells = <3>;
45 		compatible = "fsl,imx27-pwm";
47 		clock-names = "ipg", "per";
50 		assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
51 		assigned-clock-rates = <24000000>;
52 		#pwm-cells = <3>;
58 		compatible = "fsl,imx27-pwm";
60 		clock-names = "ipg", "per";
63 		assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
64 		assigned-clock-rates = <24000000>;
65 		#pwm-cells = <3>;
71 		compatible = "fsl,imx27-pwm";
73 		clock-names = "ipg", "per";
76 		assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
77 		assigned-clock-rates = <24000000>;
78 		#pwm-cells = <3>;
86 		gpio-controller;
87 		#gpio-cells = <2>;
88 		interrupt-controller;
89 		#interrupt-cells = <2>;
90 		power-domains = <&pd IMX_SC_R_GPIO_0>;
96 		gpio-controller;
97 		#gpio-cells = <2>;
98 		interrupt-controller;
99 		#interrupt-cells = <2>;
100 		power-domains = <&pd IMX_SC_R_GPIO_1>;
106 		gpio-controller;
107 		#gpio-cells = <2>;
108 		interrupt-controller;
109 		#interrupt-cells = <2>;
110 		power-domains = <&pd IMX_SC_R_GPIO_2>;
116 		gpio-controller;
117 		#gpio-cells = <2>;
118 		interrupt-controller;
119 		#interrupt-cells = <2>;
120 		power-domains = <&pd IMX_SC_R_GPIO_3>;
126 		gpio-controller;
127 		#gpio-cells = <2>;
128 		interrupt-controller;
129 		#interrupt-cells = <2>;
130 		power-domains = <&pd IMX_SC_R_GPIO_4>;
136 		gpio-controller;
137 		#gpio-cells = <2>;
138 		interrupt-controller;
139 		#interrupt-cells = <2>;
140 		power-domains = <&pd IMX_SC_R_GPIO_5>;
146 		gpio-controller;
147 		#gpio-cells = <2>;
148 		interrupt-controller;
149 		#interrupt-cells = <2>;
150 		power-domains = <&pd IMX_SC_R_GPIO_6>;
156 		gpio-controller;
157 		#gpio-cells = <2>;
158 		interrupt-controller;
159 		#interrupt-cells = <2>;
160 		power-domains = <&pd IMX_SC_R_GPIO_7>;
164 		#address-cells = <1>;
165 		#size-cells = <0>;
166 		compatible = "nxp,imx8qxp-fspi";
168 		reg-names = "fspi_base", "fspi_mmap";
172 		clock-names = "fspi_en", "fspi";
173 		power-domains = <&pd IMX_SC_R_FSPI_0>;
180 		#mbox-cells = <2>;
187 		#mbox-cells = <2>;
193 		#mbox-cells = <2>;
200 		#mbox-cells = <2>;
207 		#mbox-cells = <2>;
214 		#mbox-cells = <2>;
215 		power-domains = <&pd IMX_SC_R_MU_5A>;
222 		#mbox-cells = <2>;
223 		power-domains = <&pd IMX_SC_R_MU_6A>;
230 		#mbox-cells = <2>;
231 		power-domains = <&pd IMX_SC_R_MU_13A>;
235 	pwm0_lpcg: clock-controller@5d400000 {
236 		compatible = "fsl,imx8qxp-lpcg";
238 		#clock-cells = <1>;
244 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
247 		clock-output-names = "pwm0_lpcg_ipg_clk",
252 		power-domains = <&pd IMX_SC_R_PWM_0>;
255 	pwm1_lpcg: clock-controller@5d410000 {
256 		compatible = "fsl,imx8qxp-lpcg";
258 		#clock-cells = <1>;
264 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
267 		clock-output-names = "pwm1_lpcg_ipg_clk",
272 		power-domains = <&pd IMX_SC_R_PWM_1>;
275 	pwm2_lpcg: clock-controller@5d420000 {
276 		compatible = "fsl,imx8qxp-lpcg";
278 		#clock-cells = <1>;
284 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
287 		clock-output-names = "pwm2_lpcg_ipg_clk",
292 		power-domains = <&pd IMX_SC_R_PWM_2>;
295 	pwm3_lpcg: clock-controller@5d430000 {
296 		compatible = "fsl,imx8qxp-lpcg";
298 		#clock-cells = <1>;
304 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
307 		clock-output-names = "pwm3_lpcg_ipg_clk",
312 		power-domains = <&pd IMX_SC_R_PWM_3>;
315 	pwm4_lpcg: clock-controller@5d440000 {
316 		compatible = "fsl,imx8qxp-lpcg";
318 		#clock-cells = <1>;
324 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
327 		clock-output-names = "pwm4_lpcg_ipg_clk",
332 		power-domains = <&pd IMX_SC_R_PWM_4>;
335 	pwm5_lpcg: clock-controller@5d450000 {
336 		compatible = "fsl,imx8qxp-lpcg";
338 		#clock-cells = <1>;
344 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
347 		clock-output-names = "pwm5_lpcg_ipg_clk",
352 		power-domains = <&pd IMX_SC_R_PWM_5>;
355 	pwm6_lpcg: clock-controller@5d460000 {
356 		compatible = "fsl,imx8qxp-lpcg";
358 		#clock-cells = <1>;
364 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
367 		clock-output-names = "pwm6_lpcg_ipg_clk",
372 		power-domains = <&pd IMX_SC_R_PWM_6>;
375 	pwm7_lpcg: clock-controller@5d470000 {
376 		compatible = "fsl,imx8qxp-lpcg";
378 		#clock-cells = <1>;
384 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
387 		clock-output-names = "pwm7_lpcg_ipg_clk",
392 		power-domains = <&pd IMX_SC_R_PWM_7>;