dts/hisilicon/hisi-x5hd2.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (c) 2013-2014 Linaro Ltd.
4  * Copyright (c) 2013-2014 HiSilicon Limited.
7 #include <dt-bindings/clock/hix5hd2-clock.h>
10 	#address-cells = <1>;
11 	#size-cells = <1>;
17 	gic: interrupt-controller@f8a01000 {
18 		compatible = "arm,cortex-a9-gic";
19 		#interrupt-cells = <3>;
20 		#address-cells = <0>;
21 		interrupt-controller;
27 		#address-cells = <1>;
28 		#size-cells = <1>;
29 		compatible = "simple-bus";
30 		interrupt-parent = <&gic>;
33 		amba-bus {
34 			#address-cells = <1>;
35 			#size-cells = <1>;
36 			compatible = "simple-bus";
44 				clocks = <&clock HIX5HD2_FIXED_24M>;
58 				clocks = <&clock HIX5HD2_FIXED_24M>;
67 				clocks = <&clock HIX5HD2_FIXED_24M>;
76 				clocks = <&clock HIX5HD2_FIXED_24M>;
85 				clocks = <&clock HIX5HD2_FIXED_24M>;
93 				clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
94 				clock-names = "uartclk", "apb_pclk";
102 				clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
103 				clock-names = "uartclk", "apb_pclk";
111 				clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
112 				clock-names = "uartclk", "apb_pclk";
120 				clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
121 				clock-names = "uartclk", "apb_pclk";
129 				clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>;
130 				clock-names = "uartclk", "apb_pclk";
138 				gpio-controller;
139 				#gpio-cells = <2>;
140 				clocks = <&clock HIX5HD2_FIXED_100M>;
141 				clock-names = "apb_pclk";
142 				interrupt-controller;
143 				#interrupt-cells = <2>;
151 				gpio-controller;
152 				#gpio-cells = <2>;
153 				clocks = <&clock HIX5HD2_FIXED_100M>;
154 				clock-names = "apb_pclk";
155 				interrupt-controller;
156 				#interrupt-cells = <2>;
164 				gpio-controller;
165 				#gpio-cells = <2>;
166 				clocks = <&clock HIX5HD2_FIXED_100M>;
167 				clock-names = "apb_pclk";
168 				interrupt-controller;
169 				#interrupt-cells = <2>;
177 				gpio-controller;
178 				#gpio-cells = <2>;
179 				clocks = <&clock HIX5HD2_FIXED_100M>;
180 				clock-names = "apb_pclk";
181 				interrupt-controller;
182 				#interrupt-cells = <2>;
190 				gpio-controller;
191 				#gpio-cells = <2>;
192 				clocks = <&clock HIX5HD2_FIXED_100M>;
193 				clock-names = "apb_pclk";
194 				interrupt-controller;
195 				#interrupt-cells = <2>;
203 				gpio-controller;
204 				#gpio-cells = <2>;
205 				clocks = <&clock HIX5HD2_FIXED_100M>;
206 				clock-names = "apb_pclk";
207 				interrupt-controller;
208 				#interrupt-cells = <2>;
216 				gpio-controller;
217 				#gpio-cells = <2>;
218 				clocks = <&clock HIX5HD2_FIXED_100M>;
219 				clock-names = "apb_pclk";
220 				interrupt-controller;
221 				#interrupt-cells = <2>;
229 				gpio-controller;
230 				#gpio-cells = <2>;
231 				clocks = <&clock HIX5HD2_FIXED_100M>;
232 				clock-names = "apb_pclk";
233 				interrupt-controller;
234 				#interrupt-cells = <2>;
242 				gpio-controller;
243 				#gpio-cells = <2>;
244 				clocks = <&clock HIX5HD2_FIXED_100M>;
245 				clock-names = "apb_pclk";
246 				interrupt-controller;
247 				#interrupt-cells = <2>;
255 				gpio-controller;
256 				#gpio-cells = <2>;
257 				clocks = <&clock HIX5HD2_FIXED_100M>;
258 				clock-names = "apb_pclk";
259 				interrupt-controller;
260 				#interrupt-cells = <2>;
268 				gpio-controller;
269 				#gpio-cells = <2>;
270 				clocks = <&clock HIX5HD2_FIXED_100M>;
271 				clock-names = "apb_pclk";
272 				interrupt-controller;
273 				#interrupt-cells = <2>;
281 				gpio-controller;
282 				#gpio-cells = <2>;
283 				clocks = <&clock HIX5HD2_FIXED_100M>;
284 				clock-names = "apb_pclk";
285 				interrupt-controller;
286 				#interrupt-cells = <2>;
294 				gpio-controller;
295 				#gpio-cells = <2>;
296 				clocks = <&clock HIX5HD2_FIXED_100M>;
297 				clock-names = "apb_pclk";
298 				interrupt-controller;
299 				#interrupt-cells = <2>;
307 				gpio-controller;
308 				#gpio-cells = <2>;
309 				clocks = <&clock HIX5HD2_FIXED_100M>;
310 				clock-names = "apb_pclk";
311 				interrupt-controller;
312 				#interrupt-cells = <2>;
320 				gpio-controller;
321 				#gpio-cells = <2>;
322 				clocks = <&clock HIX5HD2_FIXED_100M>;
323 				clock-names = "apb_pclk";
324 				interrupt-controller;
325 				#interrupt-cells = <2>;
333 				gpio-controller;
334 				#gpio-cells = <2>;
335 				clocks = <&clock HIX5HD2_FIXED_100M>;
336 				clock-names = "apb_pclk";
337 				interrupt-controller;
338 				#interrupt-cells = <2>;
346 				gpio-controller;
347 				#gpio-cells = <2>;
348 				clocks = <&clock HIX5HD2_FIXED_100M>;
349 				clock-names = "apb_pclk";
350 				interrupt-controller;
351 				#interrupt-cells = <2>;
359 				gpio-controller;
360 				#gpio-cells = <2>;
361 				clocks = <&clock HIX5HD2_FIXED_100M>;
362 				clock-names = "apb_pclk";
363 				interrupt-controller;
364 				#interrupt-cells = <2>;
370 				arm,primecell-periphid = <0x00141805>;
373 				clocks = <&clock HIX5HD2_WDG0_RST>,
374 					 <&clock HIX5HD2_WDG0_RST>;
375 				clock-names = "wdog_clk", "apb_pclk";
380 			compatible = "arm,cortex-a9-twd-timer";
385 		l2: cache-controller {
386 			compatible = "arm,pl310-cache";
389 			cache-unified;
390 			cache-level = <2>;
393 		sysctrl: system-controller@0 {
399 			compatible = "syscon-reboot";
407 			#address-cells = <1>;
408 			#size-cells = <1>;
412 			clock: clock@0 {  label
413 				compatible = "hisilicon,hix5hd2-clock";
415 				#clock-cells = <1>;
421 			compatible = "snps,dw-mshc";
424 			clocks = <&clock HIX5HD2_MMC_CIU_RST>,
425 				 <&clock HIX5HD2_MMC_BIU_CLK>;
426 			clock-names = "biu", "ciu";
430 			compatible = "snps,dw-mshc";
433 			clocks = <&clock HIX5HD2_SD_CIU_RST>,
434 				 <&clock HIX5HD2_SD_BIU_CLK>;
435 			clock-names = "biu", "ciu";
439 			compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1";
442 			clocks = <&clock HIX5HD2_MAC0_CLK>;
443 			clock-names = "mac_core";
448 			compatible = "hisilicon,hix5hd2-gmac", "hisilicon,hisi-gmac-v1";
451 			clocks = <&clock HIX5HD2_MAC1_CLK>;
452 			clock-names = "mac_core";
457 			compatible = "generic-ehci";
460 			clocks = <&clock HIX5HD2_USB_CLK>;
464 			compatible = "generic-ohci";
467 			clocks = <&clock HIX5HD2_USB_CLK>;
471 			compatible = "hisilicon,peri-subctrl", "syscon";
476 			compatible = "hisilicon,hix5hd2-sata-phy";
478 			#phy-cells = <0>;
479 			hisilicon,peripheral-syscon = <&peripheral_ctrl>;
480 			hisilicon,power-reg = <0x8 10>;
484 			compatible = "hisilicon,hisi-ahci";
487 			clocks = <&clock HIX5HD2_SATA_CLK>;
491 			compatible = "hisilicon,hix5hd2-ir";
494 			clocks = <&clock HIX5HD2_FIXED_24M>;
495 			hisilicon,power-syscon = <&sysctrl>;
499 			compatible = "hisilicon,hix5hd2-i2c";
502 			clocks = <&clock HIX5HD2_I2C0_RST>;
503 			#address-cells = <1>;
504 			#size-cells = <0>;
509 			compatible = "hisilicon,hix5hd2-i2c";
512 			clocks = <&clock HIX5HD2_I2C1_RST>;
513 			#address-cells = <1>;
514 			#size-cells = <0>;
519 			compatible = "hisilicon,hix5hd2-i2c";
522 			clocks = <&clock HIX5HD2_I2C2_RST>;
523 			#address-cells = <1>;
524 			#size-cells = <0>;
529 			compatible = "hisilicon,hix5hd2-i2c";
532 			clocks = <&clock HIX5HD2_I2C3_RST>;
533 			#address-cells = <1>;
534 			#size-cells = <0>;
539 			compatible = "hisilicon,hix5hd2-i2c";
542 			clocks = <&clock HIX5HD2_I2C4_RST>;
543 			#address-cells = <1>;
544 			#size-cells = <0>;
549 			compatible = "hisilicon,hix5hd2-i2c";
552 			clocks = <&clock HIX5HD2_I2C5_RST>;
553 			#address-cells = <1>;
554 			#size-cells = <0>;