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/openbmc/linux/include/linux/platform_data/
H A Dsi5351.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Si5351A/B/C programmable clock generator platform_data.
10 * enum si5351_pll_src - Si5351 pll clock source
12 * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input
13 * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only)
22 * enum si5351_multisynth_src - Si5351 multisynth clock source
24 * @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0
25 * @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO
34 * enum si5351_clkout_src - Si5351 clock output clock source
36 * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N
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/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos-clkout.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Clock driver for Exynos clock output
11 #include <linux/clk-provider.h>
53 .compatible = "samsung,exynos3250-pmu",
56 .compatible = "samsung,exynos4210-pmu",
59 .compatible = "samsung,exynos4212-pmu",
62 .compatible = "samsung,exynos4412-pmu",
65 .compatible = "samsung,exynos5250-pmu",
68 .compatible = "samsung,exynos5410-pmu",
71 .compatible = "samsung,exynos5420-pmu",
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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddm814x-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 * "2.6.11 Connected Outputs of DPLLJ". Only clkout is
10 #clock-cells = <1>;
11 compatible = "ti,dm814-adpll-s-clock";
14 clock-names = "clkinp", "clkinpulow", "clkinphif";
15 clock-output-names = "481c5040.adpll.dcoclkldo",
16 "481c5040.adpll.clkout",
22 #clock-cells = <1>;
23 compatible = "ti,dm814-adpll-lj-clock";
26 clock-names = "clkinp", "clkinpulow";
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/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-dfsdm-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
28 - st,stm32h7-dfsdm
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/openbmc/linux/drivers/clk/
H A Dclk-lmk04832.c1 // SPDX-License-Identifier: GPL-2.0
3 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
14 #include <linux/clk-provider.h>
22 /* 0x000 - 0x00d System Functions */
34 /* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
75 /* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
124 /* 0x146 - 0x14a CLKin Control */
134 /* 0x14b - 0x152 Holdover */
136 /* 0x153 - 0x15f PLL1 Configuration */
143 /* 0x160 - 0x16e PLL2 Configuration */
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H A Dclk-si5351.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-si5351.c: Skyworks / Silicon Labs Si5351A/B/C I2C Clock Generator
6 * Rabeeh Khoury <rabeeh@solid-run.com>
10 * https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
12 * https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/AN619.pdf
18 #include <linux/clk-provider.h>
31 #include "clk-si5351.h"
63 struct si5351_hw_data *clkout; member
88 ret = regmap_read(drvdata->regmap, reg, &val); in si5351_reg_read()
90 dev_err(&drvdata->client->dev, in si5351_reg_read()
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H A Dclk-rk808.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Clkout driver for Rockchip RK808
7 * Author:Chris Zhong <zyw@rock-chips.com>
10 #include <linux/clk-provider.h>
34 return regmap_update_bits(rk808_clkout->regmap, RK808_CLK32OUT_REG, in rk808_clkout2_enable()
55 int ret = regmap_read(rk808_clkout->regmap, RK808_CLK32OUT_REG, &val); in rk808_clkout2_is_prepared()
78 unsigned int idx = clkspec->args[0]; in of_clk_rk808_get()
82 return ERR_PTR(-EINVAL); in of_clk_rk808_get()
85 return idx ? &rk808_clkout->clkout2_hw : &rk808_clkout->clkout1_hw; in of_clk_rk808_get()
94 return regmap_update_bits(rk808_clkout->regmap, RK817_SYS_CFG(1), in rk817_clkout2_enable()
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H A Dclk-lochnagar.c1 // SPDX-License-Identifier: GPL-2.0
3 * Lochnagar clock control
5 * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
11 #include <linux/clk-provider.h>
22 #include <dt-bindings/clock/lochnagar.h>
49 LN_PARENT("ln-none"),
50 LN_PARENT("ln-spdif-mclk"),
51 LN_PARENT("ln-psia1-mclk"),
52 LN_PARENT("ln-psia2-mclk"),
53 LN_PARENT("ln-cdc-clkout"),
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H A Dclk-cdce706.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI CDCE706 programmable 3-PLL clock synthesizer driver
11 #include <linux/clk-provider.h>
50 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4))
85 struct cdce706_hw_data clkout[6]; member
115 int rc = regmap_read(dev_data->regmap, reg | 0x80, val); in cdce706_reg_read()
118 dev_err(&dev_data->client->dev, "error reading reg %u", reg); in cdce706_reg_read()
125 int rc = regmap_write(dev_data->regmap, reg | 0x80, val); in cdce706_reg_write()
128 dev_err(&dev_data->client->dev, "error writing reg %u", reg); in cdce706_reg_write()
135 int rc = regmap_update_bits(dev_data->regmap, reg | 0x80, mask, val); in cdce706_reg_update()
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dti,lmk04832.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/ti,lmk04832.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments LMK04832 Clock Controller
10 - Liam Beguin <liambeguin@gmail.com>
13 Devicetree binding for the LMK04832, a clock conditioner with JEDEC JESD204B
21 - ti,lmk04832
26 '#address-cells':
29 '#size-cells':
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H A Dcirrus,lochnagar.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/cirrus,lochnagar.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of various
21 This binding document describes the binding for the clock portion of the
25 [1] Clock : ../clock/clock-bindings.txt
28 [2] include/dt-bindings/clock/lochnagar.h
36 - cirrus,lochnagar1-clk
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H A Dstericsson,u8500-clks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 (U8500) clocks
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Linus Walleij <linus.walleij@linaro.org>
14 DB8500 digital baseband system-on-chip and its siblings such as
16 itself, not off-chip clocks. There are four different on-chip
17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
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H A Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Drealtek,rtl82xx.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 realtek,clkout-disable:
24 Disable CLKOUT clock, CLKOUT clock default is enabled after hardware reset.
27 realtek,aldps-enable:
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/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dcc770.txt8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
14 - interrupts : property with a value describing the interrupt source
19 - bosch,external-clock-frequency : frequency of the external oscillator
20 clock in Hz. Note that the internal clock frequency used by the
24 - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
25 If not specified or if the specified value is 0, the CLKOUT pin
28 - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
31 - bosch,disconnect-rx0-input : see data sheet.
33 - bosch,disconnect-rx1-input : see data sheet.
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H A Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
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/openbmc/linux/drivers/net/can/cc770/
H A Dcc770_platform.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * in your board-specific code:
29 * interrupt-parent = <&mpic>;
30 * bosch,external-clock-frequency = <16000000>;
53 MODULE_DESCRIPTION("Socket-CAN driver for CC770 on the platform bus");
61 return ioread8(priv->reg_base + reg); in cc770_platform_read_reg()
67 iowrite8(val, priv->reg_base + reg); in cc770_platform_write_reg()
73 struct device_node *np = pdev->dev.of_node; in cc770_get_of_node_data()
78 prop = of_get_property(np, "bosch,external-clock-frequency", in cc770_get_of_node_data()
84 priv->can.clock.freq = clkext; in cc770_get_of_node_data()
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/openbmc/linux/sound/soc/sh/rcar/
H A Dadg.c1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
6 #include <linux/clk-provider.h>
16 #define CLKOUT 0 macro
34 struct clk *clkout[CLKOUTMAX]; member
50 (i < adg->clkin_size) && \
51 ((pos) = adg->clkin[i]); \
55 (i < adg->clkout_size) && \
56 ((pos) = adg->clkout[i]); \
58 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
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/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Dadpll.txt1 Binding for Texas Instruments ADPLL clock.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1]. It assumes a
6 register-mapped ADPLL with two to three selectable input clocks
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible : shall be one of "ti,dm814-adpll-s-clock" or
13 "ti,dm814-adpll-lj-clock" depending on the type of the ADPLL
14 - #clock-cells : from common clock binding; shall be set to 1.
15 - clocks : link phandles of parent clocks clkinp and clkinpulow, note
16 that the adpll-s-clock also has an optional clkinphif
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/openbmc/linux/drivers/clk/ux500/
H A Du8500_of_clk.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Clock definitions for u8500 platform.
5 * Copyright (C) 2012 ST-Ericsson SA
11 #include <linux/clk-provider.h>
12 #include <linux/mfd/dbx500-prcmu.h>
16 #include "reset-prcc.h"
35 if (clkspec->args_count != 2) in ux500_twocell_get()
36 return ERR_PTR(-EINVAL); in ux500_twocell_get()
38 base = clkspec->args[0]; in ux500_twocell_get()
39 bit = clkspec->args[1]; in ux500_twocell_get()
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/openbmc/linux/drivers/clk/xilinx/
H A Dclk-xlnx-clock-wizard.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 - 2021 Xilinx
14 #include <linux/clk-provider.h>
56 /* Divider limits, from UG572 Table 3-4 for Ultrascale+ */
72 #define div_mask(width) ((1 << (width)) - 1)
74 /* Extract divider instance from clock hardware instance */
85 * struct clk_wzrd - Clock wizard private data structure
87 * @clk_data: Clock data
90 * @clk_in1: Handle to input clock 'clk_in1'
91 * @axi_clk: Handle to input clock 's_axi_aclk'
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/openbmc/linux/drivers/clk/renesas/
H A Dr9a06g032-clocks.c1 // SPDX-License-Identifier: GPL-2.0
3 * R9A06G032 clock driver
11 #include <linux/clk-provider.h>
24 #include <linux/soc/renesas/r9a06g032-sysctrl.h>
26 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
33 * struct regbit - describe one bit in a register
35 * expressed in units of 32-bit words (not bytes),
43 * Since registers are aligned on 32-bit boundaries, the
44 * offset will be specified in 32-bit words rather than bytes.
48 * offset from bytes to 32-bit words.
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/openbmc/linux/drivers/clk/ti/
H A Dadpll.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk-provider.h>
181 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
182 "clock-output-names", in ti_adpll_clk_get_name()
188 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
189 d->pa, postfix); in ti_adpll_clk_get_name()
197 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, in ti_adpll_setup_clock() argument
205 d->clocks[index].clk = clock; in ti_adpll_setup_clock()
206 d->clocks[index].unregister = unregister; in ti_adpll_setup_clock()
212 dev_warn(d->dev, "clock %s con_id lookup may fail\n", in ti_adpll_setup_clock()
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H A Dclk-814x.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk-provider.h>
8 #include <dt-bindings/clock/dm814.h>
10 #include "clock.h"
65 return -ENODEV; in dm814x_adpll_early_init()
70 return -ENODEV; in dm814x_adpll_early_init()
81 "pll040clkout", /* MPU 481c5040.adpll.clkout */
82 "pll290clkout", /* DDR 481c5290.adpll.clkout */
90 return -ENODEV; in dm814x_adpll_enable_init_clocks()
93 struct clk *clock; in dm814x_adpll_enable_init_clocks() local
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/openbmc/linux/Documentation/devicetree/bindings/soc/samsung/
H A Dexynos-pmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos3250-pmu
19 - samsung,exynos4210-pmu
20 - samsung,exynos4212-pmu
21 - samsung,exynos4412-pmu
22 - samsung,exynos5250-pmu
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