| /openbmc/u-boot/arch/arm/dts/ |
| H A D | ast2600-bletchley.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2600-u-boot.dtsi"
9 compatible = "facebook,bletchley-bmc", "aspeed,ast2600";
17 stdout-path = &uart5;
35 clock-frequency = <800000000>;
38 clock-frequency = <800000000>;
44 u-boot,dm-pre-reloc;
49 clock-frequency = <400000000>;
66 pinctrl-names = "default";
[all …]
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| H A D | ast2600-slt.dts | 1 /dts-v1/;
3 #include "ast2600-u-boot.dtsi"
12 stdout-path = &uart5;
30 clock-frequency = <800000000>;
33 clock-frequency = <800000000>;
39 u-boot,dm-pre-reloc;
44 clock-frequency = <400000000>;
48 u-boot,dm-pre-reloc;
53 u-boot,dm-pre-reloc;
58 u-boot,dm-pre-reloc;
[all …]
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| H A D | ast2600-pfr.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /dts-v1/;
4 #include "ast2600-u-boot.dtsi"
8 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
16 stdout-path = &uart5;
34 clock-frequency = <800000000>;
37 clock-frequency = <800000000>;
43 u-boot,dm-pre-reloc;
48 clock-frequency = <400000000>;
65 pinctrl-names = "default";
[all …]
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| H A D | ast2600-intel.dts | 1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "ast2600-u-boot.dtsi"
8 compatible = "aspeed,ast2600-intel", "aspeed,ast2600";
16 stdout-path = &uart5;
34 clock-frequency = <1200000000>;
37 clock-frequency = <1200000000>;
43 u-boot,dm-pre-reloc;
48 clock-frequency = <400000000>;
65 pinctrl-names = "default";
[all …]
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| H A D | ast2600-evb.dts | 1 /dts-v1/;
3 #include "ast2600-u-boot.dtsi"
7 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
15 stdout-path = &uart5;
33 clock-frequency = <800000000>;
36 clock-frequency = <800000000>;
42 u-boot,dm-pre-reloc;
47 clock-frequency = <400000000>;
64 pinctrl-names = "default";
65 pinctrl-0 = < &pinctrl_mdio1_default &pinctrl_mdio2_default
[all …]
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| H A D | ast2500-evb.dts | 1 /dts-v1/;
3 #include "ast2500-u-boot.dtsi"
7 compatible = "aspeed,ast2500-evb", "aspeed,ast2500";
15 stdout-path = &uart5;
27 u-boot,dm-pre-reloc;
32 clock-frequency = <400000000>;
36 u-boot,dm-pre-reloc;
41 u-boot,dm-pre-reloc;
46 u-boot,dm-pre-reloc;
52 phy-mode = "rgmii";
[all …]
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| H A D | ast2400-evb.dts | 1 /dts-v1/;
3 #include "ast2400-u-boot.dtsi"
7 compatible = "aspeed,ast2400-evb", "aspeed,ast2400";
15 stdout-path = &uart5;
27 u-boot,dm-pre-reloc;
32 clock-frequency = <200000000>;
36 u-boot,dm-pre-reloc;
41 u-boot,dm-pre-reloc;
47 phy-mode = "rgmii";
49 pinctrl-names = "default";
[all …]
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| H A D | ast2600-dcscm.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /dts-v1/;
4 #include "ast2600-evb.dts"
7 model = "AST2600 DC-SCM";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_fmcquad_default>;
15 timing-calibration-disabled;
16 num-cs = <1>;
20 spi-max-frequency = <12500000>;
21 spi-tx-bus-width = <4>;
[all …]
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| H A D | ast2600-qcom-dc-scm-v1.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 // Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
3 /dts-v1/;
5 #include "ast2600-u-boot.dtsi"
8 model = "Qualcomm DC-SCM V1 BMC";
9 compatible = "qcom,dc-scm-v1-bmc", "aspeed,ast2600";
17 stdout-path = &uart5;
28 clock-frequency = <800000000>;
31 clock-frequency = <800000000>;
37 u-boot,dm-pre-reloc;
[all …]
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| H A D | ast2600-tacoma.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2600-u-boot.dtsi"
9 compatible = "ibm,tacoma-bmc", "aspeed,ast2600";
17 stdout-path = &uart5;
29 clock-frequency = <800000000>;
32 clock-frequency = <800000000>;
38 u-boot,dm-pre-reloc;
43 clock-frequency = <400000000>;
47 u-boot,dm-pre-reloc;
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/dma/ |
| H A D | adi,axi-dmac.txt | 1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
5 - reg: Specification for the controllers memory mapped register map.
6 - interrupts: Specification for the controllers interrupt.
7 - clocks: Phandle and specifier to the controllers AXI interface clock
8 - #dma-cells: Must be 1.
10 Required sub-nodes:
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following bindings apply. They must match the
15 Required properties for adi,channels sub-node:
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/misc/ |
| H A D | ifm-csi.txt | 1 IFM camera sensor interface on mpc5200 LocalPlus bus
4 - compatible: "ifm,o2d-csi"
5 - reg: specifies sensor chip select number and associated address range
6 - interrupts: external interrupt line number and interrupt sense mode
8 - gpios: three gpio-specifiers for "capture", "reset" and "master enable"
10 - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
12 - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
13 - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
14 - ifm,csi-wait-cycles: sensor bus wait cycles
17 - ifm,csi-byte-swap: if this property is present, the byte swapping on
[all …]
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| /openbmc/u-boot/arch/mips/mach-mt7620/ |
| H A D | Kconfig | 97 prompt "DDR2 chip width"
100 bool "8bit DDR chip width"
103 Use DDR chips with 8bit width
106 bool "16bit DDR chip width"
109 Use DDR chips with 16bit width
114 prompt "DDR2 bus width"
117 bool "16bit DDR bus width"
120 Use 16bit DDR bus width
123 bool "32bit DDR bus width"
126 Use 32bit DDR bus width
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| /openbmc/u-boot/doc/device-tree-bindings/spi/ |
| H A D | spi-stm32-qspi.txt | 2 --------------------------------------------
5 - compatible : should be "st,stm32-qspi".
6 - reg : 1. Physical base address and size of SPI registers map.
8 - spi-max-frequency : Max supported spi frequency.
9 - status : enable in requried dts.
12 --------------------------
13 - spi-max-frequency : Max supported spi frequency.
14 - spi-tx-bus-width : Bus width (number of lines) for writing (1-4)
15 - spi-rx-bus-width : Bus width (number of lines) for reading (1-4)
16 - memory-map : Address and size for memory-mapping the flash
[all …]
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| H A D | spi-bus.txt | 4 and a set of child nodes for each SPI slave on the bus. For this
10 - #address-cells - number of cells required to define a chip select
11 address on the SPI bus.
12 - #size-cells - should be zero.
13 - compatible - name of SPI bus controller following generic names
15 - cs-gpios - (optional) gpios chip select.
16 No other properties are required in the SPI bus node. It is assumed
17 that a driver for an SPI bus device will understand that it is an SPI bus.
20 flexible and non-standardized, it is left out of this binding with the
26 - num-cs : total number of chipselects
[all …]
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| /openbmc/linux/include/media/ |
| H A D | v4l2-mediabus.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Media Bus API header
11 #include <linux/v4l2-mediabus.h>
17 * bus configuration parameter. One and only one bit of each group of flags
20 * reporting the media bus configuration. For example, it is invalid to set or
60 /* FIELD = 0/1 - Field1 (odd)/Field2 (even) */
62 /* FIELD = 1/0 - Field1 (odd)/Field2 (even) */
64 /* Active state of Sync-on-green (SoG) signal, 0/1 for LOW/HIGH respectively. */
71 /* Clock non-continuous mode support. */
77 * struct v4l2_mbus_config_mipi_csi2 - MIPI CSI-2 data bus configuration
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | ti,da850-vpif.txt | 2 ----------------------
12 - compatible: must be "ti,da850-vpif"
13 - reg: physical base address and length of the registers set for the device;
14 - interrupts: should contain IRQ line for the VPIF
18 VPIF has a 16-bit parallel bus input, supporting 2 8-bit channels or a
19 single 16-bit channel. It should contain one or two port child nodes
23 Documentation/devicetree/bindings/media/video-interfaces.txt.
25 Example using 2 8-bit input channels, one of which is connected to an
26 I2C-connected TVP5147 decoder:
29 compatible = "ti,da850-vpif";
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| /openbmc/linux/arch/sh/include/mach-se/mach/ |
| H A D | mrshpc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
19 * PC-Card window open in mrshpc_setup_windows()
25 /* common mode & bus width 16bit SWAP = 1*/ in mrshpc_setup_windows()
28 /* common mode & bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
34 /* attribute mode & bus width 16bit SWAP = 1*/ in mrshpc_setup_windows()
37 /* attribute mode & bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
44 __raw_writew(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/ in mrshpc_setup_windows()
46 __raw_writew(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
|
| /openbmc/linux/drivers/media/platform/xilinx/ |
| H A D | xilinx-vip.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2015 Ideas on Board
6 * Copyright (C) 2013-2015 Xilinx, Inc.
18 #include <dt-bindings/media/xilinx-vip.h>
20 #include "xilinx-vip.h"
22 /* -----------------------------------------------------------------------------
48 * xvip_get_format_by_code - Retrieve format information for a media bus code
49 * @code: the format media bus code
52 * given V4L2 media bus format @code, or ERR_PTR if no corresponding format can
62 if (format->code == code) in xvip_get_format_by_code()
[all …]
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| /openbmc/u-boot/drivers/net/phy/ |
| H A D | b53.c | 1 // SPDX-License-Identifier: GPL-2.0+
32 /* Pseudo-PHY address (non configurable) to access internal registers */
114 struct mii_dev *bus; member
118 static int b53_mdio_op(struct mii_dev *bus, u8 page, u8 reg, u16 op) in b53_mdio_op() argument
126 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, in b53_mdio_op()
133 ret = bus->write(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, in b53_mdio_op()
140 v = bus->read(bus, BRCM_PSEUDO_PHY_ADDR, MDIO_DEVAD_NONE, in b53_mdio_op()
149 return -EIO; in b53_mdio_op()
154 static int b53_mdio_read8(struct mii_dev *bus, u8 page, u8 reg, u8 *val) in b53_mdio_read8() argument
158 ret = b53_mdio_op(bus, page, reg, REG_MII_ADDR_READ); in b53_mdio_read8()
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/bus/ |
| H A D | nvidia,tegra20-gmi.txt | 1 Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
3 The Generic Memory Interface bus enables memory transfers between internal and
10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/mmc/ |
| H A D | cavium-mmc.txt | 10 - compatible : should be one of:
11 cavium,octeon-6130-mmc
12 cavium,octeon-7890-mmc
13 cavium,thunder-8190-mmc
14 cavium,thunder-8390-mmc
15 mmc-slot
16 - reg : mmc controller base registers
17 - clocks : phandle
20 - for cd, bus-width and additional generic mmc parameters
22 - cavium,cmd-clk-skew : number of coprocessor clocks before sampling command
[all …]
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| /openbmc/u-boot/doc/device-tree-bindings/exynos/ |
| H A D | dwmmc.txt | 4 . Embedded Multimedia Cards (EMMC-version 4.5)
5 . Secure Digital memory (SD mem-version 2.0)
6 . Secure Digital I/O (SDIO-version 3.0)
7 . Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1)
14 - compatible: should be
15 - samsung,exynos-dwmmc: for exynos platforms
17 - reg: physical base address of the controller and length of memory mapped
20 - interrupts: The interrupt number to the cpu.
24 - #address-cells: should be 1.
25 - #size-cells: should be 0.
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/auxdisplay/ |
| H A D | hit,hd44780.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert@linux-m68k.org>
14 LCDs that can display one or more lines of text. It exposes an M6800 bus
15 interface, which can be used in either 4-bit or 8-bit mode. By using a
24 data-gpios:
26 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
27 DB4-DB7 (4-bit mode) of the LCD Controller's bus interface.
29 - maxItems: 4
[all …]
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| /openbmc/u-boot/drivers/pcmcia/ |
| H A D | marubun_pcmcia.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Marubun MR-SHPC-01 PCMCIA controller device driver
25 /* MR-SHPC-01 register */
59 * PC-Card window open in pcmcia_on()
65 outw(0x0b00,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 1 */ in pcmcia_on()
67 outw(0x0300,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 0 */ in pcmcia_on()
72 outw(0x0a00,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 1 */ in pcmcia_on()
74 outw(0x0200,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 0 */ in pcmcia_on()
80 outw(0x0a00,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1 */ in pcmcia_on()
82 outw(0x0200,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0 */ in pcmcia_on()
|