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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap2420-n8x0-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 stdout-path = &uart3;
16 compatible = "i2c-cbus-gpio";
21 #address-cells = <1>;
22 #size-cells = <0>;
25 interrupt-parent = <&gpio4>;
34 clock-frequency = <400000>;
44 clock-frequency = <400000>;
50 /* gpio-irq for dma: 26 */
53 #address-cells = <1>;
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H A Domap3-gta04a5one.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com>
6 #include "omap3-gta04a5.dts"
13 gpmc_pins: gpmc-pins {
14 pinctrl-single,pins = <
45 pinctrl-names = "default";
46 pinctrl-0 = <&gpmc_pins>;
48 /delete-node/ nand@0,0;
52 #address-cells = <1>;
53 #size-cells = <1>;
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H A Domap3-igep.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 /dts-v1/;
19 stdout-path = &uart3;
23 compatible = "ti,omap-twl4030";
28 vdd33: regulator-vdd33 {
29 compatible = "regulator-fixed";
30 regulator-name = "vdd33";
31 regulator-always-on;
37 gpmc_pins: gpmc-pins {
38 pinctrl-single,pins = <
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H A Domap3-n950-n9.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff)
13 cpu0-supply = <&vcc>;
23 compatible = "regulator-fixed";
24 regulator-name = "VEMMC";
25 regulator-min-microvolt = <2900000>;
26 regulator-max-microvolt = <2900000>;
28 startup-delay-us = <150>;
29 enable-active-high;
33 compatible = "regulator-fixed";
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H A Domap3-n900.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2013-2014 Aaro Koskinen <aaro.koskinen@iki.fi>
7 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/media/video-interfaces.h>
15 * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
17 * blocks then kernel receive "Unhandled fault: external abort on non-linefetch"
18 * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no
34 compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
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/openbmc/linux/include/linux/platform_data/
H A Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
59 u32 access; /* Start-cycle to first data valid delay */
105 u32 t_bacc; /* burst access valid clock to output delay */
131 #define GPMC_BURST_4 4 /* 4 word burst */
132 #define GPMC_BURST_8 8 /* 8 word burst */
133 #define GPMC_BURST_16 16 /* 16 word burst */
134 #define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
135 #define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
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/openbmc/u-boot/arch/arm/dts/
H A Domap3-igep.dtsi11 /dts-v1/;
22 stdout-path = &uart3;
26 compatible = "ti,omap-twl4030";
31 vdd33: regulator-vdd33 {
32 compatible = "regulator-fixed";
33 regulator-name = "vdd33";
34 regulator-always-on;
41 pinctrl-single,pins = <
48 pinctrl-single,pins = <
55 pinctrl-single,pins = <
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/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dlpddr2.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
50 …_MDSCR_MR1_VALUE 0xC2018030 /* Configure MR1: BL 4, burst type interleaved, wrap control no wrap…
64 #define MMDC_MDRWD_VALUE 0x0F9F26D2 /* Read/write command delay - default used */
/openbmc/u-boot/board/armadeus/apf27/
H A Dapf27.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
66 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
90 #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
91 #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
103 #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
108 * 0 = Burst mode
136 #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
137 #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
149 #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
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/openbmc/linux/arch/arm/boot/dts/axis/
H A Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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/openbmc/linux/drivers/net/ethernet/amazon/ena/
H A Dena_eth_com.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
15 #define ENA_LLQ_HEADER (128UL - ENA_LLQ_ENTRY_DESC_CHUNK_SIZE)
16 #define ENA_LLQ_LARGE_HEADER (256UL - ENA_LLQ_ENTRY_DESC_CHUNK_SIZE)
21 /* For LLQ, header buffer - pushed to the device mem space */
73 writel(intr_reg->intr_control, io_cq->unmask_reg); in ena_com_unmask_intr()
80 next_to_comp = io_sq->next_to_comp; in ena_com_free_q_entries()
81 tail = io_sq->tail; in ena_com_free_q_entries()
82 cnt = tail - next_to_comp; in ena_com_free_q_entries()
84 return io_sq->q_depth - 1 - cnt; in ena_com_free_q_entries()
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H A Dena_eth_com.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
15 head_masked = io_cq->head & (io_cq->q_depth - 1); in ena_com_get_next_rx_cdesc()
16 expected_phase = io_cq->phase; in ena_com_get_next_rx_cdesc()
18 cdesc = (struct ena_eth_io_rx_cdesc_base *)(io_cq->cdesc_addr.virt_addr in ena_com_get_next_rx_cdesc()
19 + (head_masked * io_cq->cdesc_entry_size_in_bytes)); in ena_com_get_next_rx_cdesc()
21 desc_phase = (READ_ONCE(cdesc->status) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> in ena_com_get_next_rx_cdesc()
40 tail_masked = io_sq->tail & (io_sq->q_depth - 1); in get_sq_desc_regular_queue()
42 offset = tail_masked * io_sq->desc_entry_size; in get_sq_desc_regular_queue()
44 return (void *)((uintptr_t)io_sq->desc_addr.virt_addr + offset); in get_sq_desc_regular_queue()
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/openbmc/linux/drivers/usb/cdns3/
H A Dcdnsp-debug.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 return "Stopped - Length Invalid"; in cdnsp_trb_comp_code_string()
63 return "Stopped - Short Packet"; in cdnsp_trb_comp_code_string()
97 return "No-Op"; in cdnsp_trb_type_string()
119 return "No-Op Command"; in cdnsp_trb_type_string()
129 return "MFINDEX Wrap Event"; in cdnsp_trb_type_string()
182 int ep_id = TRB_TO_EP_INDEX(field3) - 1; in cdnsp_decode_trb()
382 "type '%s' -> raw %08x %08x %08x %08x", in cdnsp_decode_trb()
405 s = "full-speed"; in cdnsp_decode_slot_context()
408 s = "high-speed"; in cdnsp_decode_slot_context()
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/openbmc/linux/net/dccp/
H A Dackvec.c1 // SPDX-License-Identifier: GPL-2.0-only
22 av->av_buf_head = av->av_buf_tail = DCCPAV_MAX_ACKVEC_LEN - 1; in dccp_ackvec_alloc()
23 INIT_LIST_HEAD(&av->av_records); in dccp_ackvec_alloc()
32 list_for_each_entry_safe(cur, next, &av->av_records, avr_node) in dccp_ackvec_purge_records()
34 INIT_LIST_HEAD(&av->av_records); in dccp_ackvec_purge_records()
46 * dccp_ackvec_update_records - Record information about sent Ack Vectors
57 return -ENOBUFS; in dccp_ackvec_update_records()
59 avr->avr_ack_seqno = seqno; in dccp_ackvec_update_records()
60 avr->avr_ack_ptr = av->av_buf_head; in dccp_ackvec_update_records()
61 avr->avr_ack_ackno = av->av_buf_ackno; in dccp_ackvec_update_records()
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/openbmc/linux/block/
H A Dbfq-iosched.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 * BFQ is a proportional-share I/O scheduler, with some extra
17 * low-latency capabilities. BFQ also supports full hierarchical
20 * limitations can be found in Documentation/block/bfq-iosched.rst.
22 * BFQ is a proportional-share storage-I/O scheduling algorithm based
23 * on the slice-by-slice service scheme of CFQ. But BFQ assigns
25 * time slices. The device is not granted to the in-service process
31 * B-WF2Q+, to schedule processes according to their budgets. More
33 * process/queue is assigned a user-configurable weight, and B-WF2Q+
36 * B-WF2Q+, BFQ can afford to assign high budgets to I/O-bound
[all …]
/openbmc/linux/sound/soc/codecs/
H A Drt5677-spi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5677-spi.c -- RT5677 ALSA SoC audio codec driver
30 #include "rt5677-spi.h"
39 * DataPhase word size of 16-bit commands is 2 bytes.
40 * DataPhase word size of 32-bit commands is 4 bytes.
41 * DataPhase word size of burst commands is 8 bytes.
42 * The DSP CPU is little-endian.
54 #define RT5677_MIC_BUF_BYTES ((u32)(RT5677_BUF_BYTES_TOTAL - \
66 size_t dma_offset; /* zero-based offset into runtime->dma_area */
68 u32 mic_read_offset; /* zero-based offset into DSP's mic buffer */
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/openbmc/linux/drivers/ata/
H A Dpata_cs5530.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata-cs5530.c - CS5530 PATA for new ATA layer
28 unsigned long bmdma = (unsigned long)ap->ioaddr.bmdma_addr; in cs5530_port_base()
30 return (void __iomem *)((bmdma & ~0x0F) + 0x20 + 0x10 * ap->port_no); in cs5530_port_base()
34 * cs5530_set_piomode - PIO setup
57 if (adev->devno) in cs5530_set_piomode()
60 iowrite32(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base); in cs5530_set_piomode()
64 * cs5530_set_dmamode - DMA timing setup
82 switch(adev->dma_mode) { in cs5530_set_dmamode()
100 if (adev->devno == 0) /* Master */ in cs5530_set_dmamode()
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/openbmc/linux/drivers/hwtracing/intel_th/
H A Dmsu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Intel Corporation.
21 #include <linux/dma-mapping.h>
31 #define msc_dev(x) (&(x)->thdev->dev)
35 * READY -> INUSE -+-> LOCKED -+-> READY -> etc.
36 * \-----------/
42 * All state transitions happen automatically, except for the LOCKED->READY,
57 * struct msc_window - multiblock mode window descriptor
80 * struct msc_iter - iterator for msc buffer
106 * struct msc - MSC device representation
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/openbmc/linux/drivers/memory/
H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
32 #include <linux/omap-gpmc.h>
36 #include <linux/platform_data/mtd-nand-omap2.h>
38 #define DEVICE_NAME "omap-gpmc"
257 /* Define chip-selects as reserved by default until probe completes */
305 * gpmc_get_clk_period - get period of selected clock domain in ps
342 return (time_ns * 1000 + tick_ps - 1) / tick_ps; in gpmc_ns_to_clk_ticks()
357 return (time_ps + tick_ps - 1) / tick_ps; in gpmc_ps_to_ticks()
[all …]
/openbmc/linux/drivers/dma/
H A Dtegra20-apb-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
12 #include <linux/dma-mapping.h>
102 * If any burst is in flight and DMA paused then this is the time to complete
103 * on-flight burst and update DMA status register.
144 * sub-transfer as per requester details and hw support.
201 /* Channel-slave specific configuration */
232 writel(val, tdma->base_addr + reg); in tdma_write()
238 writel(val, tdc->chan_addr + reg); in tdc_write()
243 return readl(tdc->chan_addr + reg); in tdc_read()
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H A Dimx-sdma.c1 // SPDX-License-Identifier: GPL-2.0+
3 // drivers/dma/imx-sdma.c
11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
27 #include <linux/dma-mapping.h>
38 #include <linux/dma/imx-dma.h>
41 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
44 #include "virt-dma.h"
129 * 0-7 Lower WML Lower watermark level
140 * 13-15 --------- MUST BE 0
141 * 16-23 Higher WML HWML
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/openbmc/u-boot/drivers/net/
H A Dmvneta.c1 // SPDX-License-Identifier: GPL-2.0
5 * U-Boot version:
6 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
12 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
30 #include <asm-generic/gpio.h>
42 #define WRAP (2 + ETH_HLEN + 4 + 32) macro
44 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
112 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) argument
116 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) argument
148 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
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/openbmc/linux/drivers/net/ethernet/sun/
H A Dsungem.h1 /* SPDX-License-Identifier: GPL-2.0 */
29 #define GREG_CFG_IBURST 0x00000001 /* Infinite Burst */
33 * after infinite burst (Apple) */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
91 #define GREG_BIFDIAG_BURSTSM 0x007f0000 /* PCI Burst state machine */
130 * This 13-bit register is programmed by the driver to hold the descriptor
136 * This 13-bit register is updated by GEM to hold to descriptor entry index
171 * them later. -DaveM
220 #define RXDMA_CFG_RINGSZ_32 0x00000000 /* - 32 entries */
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/openbmc/linux/drivers/net/dsa/ocelot/
H A Dfelix_vsc9959.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright 2018-2019 NXP
15 #include <linux/pcs-lynx.h>
663 /* Layer-3 Information */
669 /* Layer-4 Information */
900 /* soft-reset the switch core */ in vsc9959_reset()
906 dev_err(ocelot->dev, "timeout: switch core reset\n"); in vsc9959_reset()
916 dev_err(ocelot->dev, "timeout: switch sram init\n"); in vsc9959_reset()
928 * Bit 7-0: Value to be multiplied with unit
958 struct pci_dev *pdev = to_pci_dev(ocelot->dev); in vsc9959_mdio_bus_alloc()
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