| /openbmc/u-boot/common/ |
| H A D | Kconfig | 1 menu "Boot timing"
4 bool "Boot timing and reporting"
6 Enable recording of boot time while booting. To use it, insert
12 add up all the accumulated time and report it.
22 bool "Boot timing and reported in SPL"
25 Enable recording of boot time in SPL. To make this visible to U-Boot
27 information when SPL finishes and load it when U-Boot proper starts
28 up.
31 bool "Boot timing and reported in TPL"
34 Enable recording of boot time in SPL. To make this visible to U-Boot
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| /openbmc/u-boot/include/ |
| H A D | spl.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
11 /* Platform-specific defines */
16 /* Value in r0 indicates we booted from U-Boot */
19 /* Boot type */
26 * u_boot_first_phase() - check if this is the first U-Boot phase
28 * U-Boot has up to three phases: TPL, SPL and U-Boot proper. Depending on the
30 * phase of U-Boot or not. If there is no SPL, then this is U-Boot proper. If
34 * @returns true if this is the first phase of U-Boot
103 * We need to know the position of U-Boot in memory so we can jump to it. We
104 * allow any U-Boot binary to be used (u-boot.bin, u-boot-nodtb.bin,
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| /openbmc/u-boot/arch/x86/ |
| H A D | Kconfig | 8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
19 For now, 32-bit mode is recommended, as 64-bit is still
23 bool "32-bit"
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
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| /openbmc/u-boot/tools/binman/ |
| H A D | README.entries | 5 be placed in an image one by one to build up a final firmware image. It is
15 ------------------------------------------------------
21 - filename: Filename of file to read into entry
22 - compress: Compression algorithm to use:
24 lz4: Use lz4 compression (via 'lz4' command-line utility)
28 example the 'u_boot' entry which provides the filename 'u-boot.bin'.
30 If compression is enabled, an extra 'uncomp-size' property is written to
31 the node (if enabled with -u) which provides the uncompressed size of the
36 Entry: blob-dtb: A blob that holds a device tree
37 ------------------------------------------------
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| H A D | state.py | 1 # SPDX-License-Identifier: GPL-2.0+
15 # Records the device-tree files known to binman, keyed by filename (e.g.
16 # 'u-boot-spl.dtb')
22 # True to use fake device-tree files for testing (see U_BOOT_DTB_DATA in
36 """Get the Fdt object for a particular device-tree filename
38 Binman keeps track of at least one device-tree file called u-boot.dtb but
39 can also have others (e.g. for SPL). This function looks up the given
43 fname: Filename to look up (e.g. 'u-boot.dtb').
56 fname: Filename to look up (e.g. 'u-boot.dtb').
64 """Looks up the FDT pathname and contents
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| /openbmc/u-boot/board/freescale/t208xqds/ |
| H A D | README | 1 The T2080QDS is a high-performance computing evaluation, development and
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
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| /openbmc/u-boot/doc/ |
| H A D | README.x86 | 1 # SPDX-License-Identifier: GPL-2.0+
6 U-Boot on x86
9 This document describes the information about U-Boot running on x86 targets,
13 ------
14 U-Boot supports running as a coreboot [1] payload on x86. So far only Link
17 most of the low-level details.
19 U-Boot is a main bootloader on Intel Edison board.
21 U-Boot also supports booting directly from x86 reset vector, without coreboot.
23 'bare metal', U-Boot acts like a BIOS replacement. The following platforms
26 - Bayley Bay CRB
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| H A D | README.u-boot_on_efi | 1 # SPDX-License-Identifier: GPL-2.0+
5 U-Boot on EFI
7 This document provides information about U-Boot running on top of EFI, either
8 as an application or just as a means of getting U-Boot onto a new platform.
22 32/64-bit
28 ----------
29 Running U-Boot on EFI is useful in several situations:
31 - You have EFI running on a board but U-Boot does not natively support it
32 fully yet. You can boot into U-Boot from EFI and use that until U-Boot is
35 - You need to use an EFI implementation (e.g. UEFI) because your vendor
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| H A D | README.chromium | 1 Running U-Boot from coreboot on Chromebooks
4 U-Boot can be used as a secondary boot loader in a few situations such as from
6 ARM platforms to start up the machine.
8 This document aims to provide a guide to booting U-Boot on a Chromebook. It
10 placing this information in the U-Boot tree should make it easier to find for
11 those who use U-Boot habitually.
13 Most of these platforms are supported by U-Boot natively, but it is risky to
17 For all of these the standard U-Boot build instructions apply. For example on
20 sudo apt install gcc-arm-linux-gnueabi
22 make O=b/nyan_big CROSS_COMPILE=arm-linux-gnueabi- nyan-big_defconfig all
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| /openbmc/u-boot/board/freescale/ls2080aqds/ |
| H A D | README | 2 --------
3 The LS2080A Development System (QDS) is a high-performance computing,
10 --------------------
11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
15 -----------------------
16 - SERDES Connections, 16 lanes supporting:
17 - PCI Express - 3.0
18 - SGMII, SGMII 2.5
19 - QSGMII
20 - SATA 3.0
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| /openbmc/u-boot/tools/binman/etype/ |
| H A D | x86_start16.py | 1 # SPDX-License-Identifier: GPL-2.0+
5 # Entry-type module for the 16-bit x86 start-up code for U-Boot
12 """x86 16-bit start-up code for U-Boot
15 - filename: Filename of u-boot-x86-16bit.bin (default
16 'u-boot-x86-16bit.bin')
18 x86 CPUs start up in 16-bit mode, even if they are 32-bit CPUs. This code
21 for changing to 32-bit mode and jumping to U-Boot's entry point, which
22 requires 32-bit mode (for 32-bit U-Boot).
24 For 64-bit U-Boot, the 'x86_start16_spl' entry type is used instead.
30 return 'u-boot-x86-16bit.bin'
|
| H A D | x86_start16_spl.py | 1 # SPDX-License-Identifier: GPL-2.0+
5 # Entry-type module for the 16-bit x86 start-up code for U-Boot SPL
12 """x86 16-bit start-up code for SPL
15 - filename: Filename of spl/u-boot-x86-16bit-spl.bin (default
16 'spl/u-boot-x86-16bit-spl.bin')
18 x86 CPUs start up in 16-bit mode, even if they are 64-bit CPUs. This code
21 for changing to 32-bit mode and starting SPL, which in turn changes to
22 64-bit mode and jumps to U-Boot (for 64-bit U-Boot).
24 For 32-bit U-Boot, the 'x86_start16' entry type is used instead.
30 return 'spl/u-boot-x86-16bit-spl.bin'
|
| H A D | u_boot_ucode.py | 1 # SPDX-License-Identifier: GPL-2.0+
5 # Entry-type module for a U-Boot binary with an embedded microcode pointer
13 """U-Boot microcode block
21 U-Boot on x86 needs a single block of microcode. This is collected from
26 the FSP sets up the SRAM / cache-as-RAM but does so in the call that
28 microcode the same way in U-Boot (even non-FSP platforms). This is that
31 platforms), or used to set up the microcode (for non-FSP platforms).
37 entry (u-boot-ucode) is empty. If there is more than one update, then
39 entry (u-boot-dtb-with-ucode) is updated to remove the microcode. This
47 Contains u-boot-nodtb.bin (i.e. U-Boot without the device tree).
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| /openbmc/u-boot/lib/efi/ |
| H A D | efi_app.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * This file implements U-Boot running as an EFI application.
27 return global_priv->sys_table; in efi_get_sys_table()
32 return global_priv->ram_base; in efi_get_ram_base()
37 struct efi_boot_services *boot = priv->boot; in setup_memory() local
44 * are very few assignments to global_data in U-Boot and this makes in setup_memory()
52 gd->malloc_base = (ulong)efi_malloc(priv, CONFIG_VAL(SYS_MALLOC_F_LEN), in setup_memory()
54 if (!gd->malloc_base) in setup_memory()
59 * Don't allocate any memory above 4GB. U-Boot is a 32-bit application in setup_memory()
63 ret = boot->allocate_pages(EFI_ALLOCATE_MAX_ADDRESS, in setup_memory()
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| /openbmc/openbmc/poky/meta/lib/oeqa/manual/ |
| H A D | bsp-hw.json | 4 "@alias": "bsps-hw.bsps-hw.boot_and_install_from_USB",
14 …sults": "User can choose install system from usb stick onto harddisk from boot menu or command lin…
17 "action": "configure device BIOS to firstly boot from USB if necessary",
18 "expected_results": "Installed system can boot up"
21 "action": "boot the device and select option \"Install\" from boot menu",
38 "@alias": "bsps-hw.bsps-hw.live_boot_from_USB",
48 …"expected_results": "User can choose boot from live image on usb stick from boot menu or command l…
51 "action": "Configure device BIOS to firstly boot from USB if necessary.",
55 "action": "Reboot the device and boot from USB stick.",
56 "expected_results": "Live image can boot up with usb stick"
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| /openbmc/u-boot/board/boundary/nitrogen6x/ |
| H A D | README.mx6qsabrelite | 1 U-Boot for the Freescale i.MX6q SabreLite board
4 This file contains information for the port of U-Boot to the Freescale
9 --------
11 To build U-Boot for the SabreLite board:
17 2. Boot from SD card
18 --------------------
20 The SabreLite boards boot from the SPI NOR flash. These boards need their SPI
21 to be reflashed with a small SD card loader to support boot from SD card. The
22 board will still boot from SPI NOR, but the loader will in turn request the
23 BootROM to load the U-Boot from SD card.
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| /openbmc/u-boot/board/freescale/t102xqds/ |
| H A D | README | 2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
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| /openbmc/linux/Documentation/power/ |
| H A D | swsusp-dmcrypt.rst | 2 How to use dm-crypt and swsusp together
10 You know how dm-crypt works. If not, visit the following web page:
11 http://www.saout.de/misc/dm-crypt/
13 You did read Documentation/admin-guide/initrd.rst and know how an initrd works.
16 Now your system is properly set up, your disk is encrypted except for
17 the swap device(s) and the boot partition which may contain a mini
26 up dm-crypt and then asks swsusp to resume from the encrypted
29 The most important thing is that you set up dm-crypt in such
33 to always set up this swap device first with dmsetup, so that
36 brw------- 1 root root 254, 0 Jul 28 13:37 /dev/mapper/swap0
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| /openbmc/u-boot/common/spl/ |
| H A D | Kconfig | 25 supports MMC, NAND and YMODEM and other methods loading of U-Boot
29 bool "Pass hand-off information from SPL to U-Boot proper"
32 It is useful to be able to pass information from SPL to U-Boot
33 proper to preserve state that is known in SPL and is needed in U-Boot.
34 Enable this to locate the handoff information in U-Boot proper, early
35 in boot. It is available in gd->handoff. The state state is set up
44 This option can minilize the SPL size to compatible with AST2600-A0
45 secure boot.
48 bool "Pass hand-off information from SPL to U-Boot proper"
53 used to pass information like the size of SDRAM from SPL to U-Boot
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| /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | mp.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2011 Freescale Semiconductor, Inc.
27 * Determine if U-Boot should keep secondary cores in reset, or let them out
48 out_be32(&pic->pir, 1 << nr); in cpu_reset()
50 (void)in_be32(&pic->pir); in cpu_reset()
51 out_be32(&pic->pir, 0x0); in cpu_reset()
73 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]); in cpu_status()
74 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]); in cpu_status()
75 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); in cpu_status()
86 setbits_be32(&gur->coredisrl, 1 << nr); in cpu_disable()
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| /openbmc/u-boot/arch/arm/lib/ |
| H A D | crt0_64.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * crt0 - C-runtime startup Code for AArch64 U-Boot
9 * Albert ARIBAUD <albert.u.boot@aribaud.net>
13 #include <asm-offsets.h>
18 * This file handles the target-independent stages of the U-Boot
19 * start-up where a C runtime environment is needed. Its entry point
24 * 1. Set up initial environment for calling board_init_f().
39 * 3. Set up intermediate environment where the stack and GD are the
41 * initialized non-const data are still not available.
43 * 4a.For U-Boot proper (not SPL), call relocate_code(). This function
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| /openbmc/u-boot/board/phytec/pcl063/ |
| H A D | README | 1 How to use U-Boot on PHYTEC phyBOARD-i.MX6UL-Segin
2 --------------------------------------------------
4 - Configure and build U-Boot for phyCORE-i.MX6UL:
10 This will generate SPL and u-boot-dtb.img images.
12 - The SPL and u-boot-dtb.img images need to be flashed into the micro SD card:
15 $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
17 - Jumper settings:
19 JP1: Open: Boot from NAND
20 Closed: Boot from SD/MMC1
22 - Connect the Serial cable to UART0 and the PC for the console.
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| /openbmc/u-boot/board/freescale/mpc8572ds/ |
| H A D | README | 2 --------
3 MPC8572DS is a high-performance computing, evaluation and development platform
6 Building U-Boot
7 -----------
12 -----------
13 MPC8572DS board has two flash banks. They are both present on boot, but their
14 locations can be swapped using the dip-switch SW9[1:2].
16 Booting is always from the boot bank at 0xec00_0000.
20 ----------
22 0xe800_0000 - 0xebff_ffff Alternate bank 64MB
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| /openbmc/u-boot/board/engicam/imx6ul/ |
| H A D | README | 1 Hsow to use U-Boot on Engicam GEAM6UL and Is.IoT MX6UL Starter Kit:
2 -------------------------------------------------------------------
6 - Configure U-Boot for Engicam GEAM6UL:
9 - Configure U-Boot for Engicam Is.IoT MX6UL:
12 - Build U-Boot
15 This will generate the SPL image called SPL and the u-boot-dtb.img.
17 - Flash the SPL image into the micro SD card:
21 - Flash the u-boot-dtb.img image into the micro SD card:
23 sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
25 - Jumper settings:
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
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