Lines Matching +full:boot +full:- +full:up
1 The T2080QDS is a high-performance computing evaluation, development and
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6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
18 - 8 Ethernet interfaces, supporting combinations of the following:
19 - Up to four 10 Gbps Ethernet MACs
20 - Up to eight 1 Gbps Ethernet MACs
21 - Up to four 2.5 Gbps Ethernet MACs
22 - High-speed peripheral interfaces
23 - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
24 - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
25 - Additional peripheral interfaces
26 - Two serial ATA (SATA 2.0) controllers
27 - Two high-speed USB 2.0 controllers with integrated PHY
28 - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
29 - Enhanced serial peripheral interface (eSPI)
30 - Four I2C controllers
31 - Four 2-pin UARTs or two 4-pin UARTs
32 - Integrated Flash Controller supporting NAND and NOR flash
33 - Three eight-channel DMA engines
34 - Support for hardware virtualization and partitioning enforcement
35 - QorIQ Platform's Trust Architecture 2.0
38 -----------------------------------
46 SoC Package: 896-pins 780-pins
50 -------------------------
52 - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
54 - Single memory controller capable of supporting DDR3 and DDR3-LV devices
55 - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
57 - Two 1Gbps RGMII on-board ports
58 - Four 10Gbps XFI on-board cages
59 - 1Gbps/2.5Gbps SGMII Riser card
60 - 10Gbps XAUI Riser card
62 - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
64 - 16 lanes up to 10.3125GHz
65 - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
67 - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
69 - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
71 - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
73 - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
75 - Two SATA 2.0 ports on-board
77 - Two Serial RapidIO 2.0 ports up to 5 GHz
79 - Supports SD/SDHC/SDXC/eMMC Card
81 - Four I2C controllers.
83 - Dual 4-pins UART serial ports
85 - QIXIS-II FPGA system controll
87 - Support Legacy, COP/JTAG, Aurora, Event and EVT
89 - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
90 a on-board SFP+ cages, which to house optical module (fiber cable) or
92 10GBASE-KR scenario.
95 introduced to indicate a XFI port will use copper cable, and U-Boot
107 1000BASE-KX(1G-KX):
108 - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
109 runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
110 in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration
111 Register 1 (PCCR1), and U-Boot fixup the dtb for kernel to do proper
113 Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC
114 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
115 MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1'
118 hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.
121 ----------------
124 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
125 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
133 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
143 -------------------------
145 0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
146 0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
152 0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
153 0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
163 ------------------------------------------
164 1. NOR boot:
165 a. build NOR boot image
168 b. program u-boot.bin image to NOR flash
169 => tftp 1000000 u-boot.bin
171 set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
174 To change boot source to vbank4:
175 by software: run command 'qixis_reset altbank' in U-Boot.
176 by DIP-switch: set SW6[1:4] = '0100'
178 To change boot source to vbank0:
179 by software: run command 'qixis_reset' in U-Boot.
180 by DIP-Switch: set SW6[1:4] = '0000'
182 2. NAND Boot:
183 a. build PBL image for NAND boot
186 b. program u-boot-with-spl-pbl.bin to NAND flash
187 => tftp 1000000 u-boot-with-spl-pbl.bin
190 set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
192 3. SPI Boot:
193 a. build PBL image for SPI boot
196 b. program u-boot-with-spl-pbl.bin to SPI flash
197 => tftp 1000000 u-boot-with-spl-pbl.bin
201 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
203 4. SD Boot:
204 a. build PBL image for SD boot
207 b. program u-boot-with-spl-pbl.bin to SD/MMC card
208 => tftp 1000000 u-boot-with-spl-pbl.bin
212 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
215 2-stage NAND/SPI/SD boot loader
216 -------------------------------
217 PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
219 and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
220 Finally SPL transers control to U-Boot for futher booting.
223 - Executes within 256K
224 - No relocation required
227 -------------------------------------------------
229 -------------------------------------------------
231 -------------------------------------------------
233 -------------------------------------------------
235 -------------------------------------------------
237 -------------------------------------------------
239 -------------------------------------------------
240 |U-Boot SPL | 0xFFFD8000 (160KB) |
241 -------------------------------------------------
244 --------------------------------------------------------------
246 0x000000 0x0FFFFF U-Boot img 1MB (2 blocks)
247 0x100000 0x17FFFF U-Boot env 512KB (1 block)
252 ----------------------------------------------------
254 0x008 2048 U-Boot img 1MB
255 0x800 0016 U-Boot env 8KB
260 ----------------------------------------------------
262 0x000000 0x0FFFFF U-Boot img 1MB
263 0x100000 0x101FFF U-Boot env 8KB
268 -----------------------------------------
277 --------------------------------------------------------------
278 Device tree support is available for t2080qds for below mentioned boot,
279 1. NOR Boot
280 2. NAND Boot
281 3. SD Boot
282 4. SPIFLASH Boot
284 To enable device tree support for other boot, below configs need to be
289 CONFIG_RESET_VECTOR_ADDRESS - 0xffc
292 1. use 'u-boot-with-dtb.bin' for NOR boot.
293 2. use 'u-boot-with-spl-pbl.bin' for other boot.