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/openbmc/bmcweb/test/redfish-core/include/utils/
H A Dip_utils_test.cpp44 uint8_t bits = 0; in TEST() local
45 EXPECT_TRUE(ipv4VerifyIpAndGetBitcount("128.0.0.0", &bits)); in TEST()
46 EXPECT_EQ(bits, 1); in TEST()
47 EXPECT_TRUE(ipv4VerifyIpAndGetBitcount("192.0.0.0", &bits)); in TEST()
48 EXPECT_EQ(bits, 2); in TEST()
49 EXPECT_TRUE(ipv4VerifyIpAndGetBitcount("224.0.0.0", &bits)); in TEST()
50 EXPECT_EQ(bits, 3); in TEST()
51 EXPECT_TRUE(ipv4VerifyIpAndGetBitcount("240.0.0.0", &bits)); in TEST()
52 EXPECT_EQ(bits, 4); in TEST()
53 EXPECT_TRUE(ipv4VerifyIpAndGetBitcount("248.0.0.0", &bits)); in TEST()
[all …]
/openbmc/u-boot/board/micronas/vct/
H A Ddcgu.c40 en1.bits.en_clkmsmc = enable; in dcgu_set_clk_switch()
43 en1.bits.en_clkssi_s = enable; in dcgu_set_clk_switch()
46 en1.bits.en_clkssi_m = enable; in dcgu_set_clk_switch()
49 en1.bits.en_clksmc = enable; in dcgu_set_clk_switch()
52 en1.bits.en_clkebi = enable; in dcgu_set_clk_switch()
55 en1.bits.en_usbpll = enable; in dcgu_set_clk_switch()
58 en1.bits.en_clkusb60 = enable; in dcgu_set_clk_switch()
61 en1.bits.en_clkusb24 = enable; in dcgu_set_clk_switch()
64 en1.bits.en_clkuart2 = enable; in dcgu_set_clk_switch()
67 en1.bits.en_clkuart1 = enable; in dcgu_set_clk_switch()
[all …]
/openbmc/qemu/target/s390x/tcg/
H A Dvec_int_helper.c100 #define DEF_VAVG(BITS) \ argument
101 void HELPER(gvec_vavg##BITS)(void *v1, const void *v2, const void *v3, \
106 for (i = 0; i < (128 / BITS); i++) { \
107 const int32_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, i); \
108 const int32_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, i); \
110 s390_vec_write_element##BITS(v1, i, (a + b + 1) >> 1); \
116 #define DEF_VAVGL(BITS) \ argument
117 void HELPER(gvec_vavgl##BITS)(void *v1, const void *v2, const void *v3, \
122 for (i = 0; i < (128 / BITS); i++) { \
123 const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
[all …]
H A Dvec_helper.c67 #define DEF_VPK_HFN(BITS, TBITS) \ argument
68 typedef uint##TBITS##_t (*vpk##BITS##_fn)(uint##BITS##_t, int *); \
69 static int vpk##BITS##_hfn(S390Vector *v1, const S390Vector *v2, \
70 const S390Vector *v3, vpk##BITS##_fn fn) \
76 uint##BITS##_t src; \
78 if (i < (128 / BITS)) { \
79 src = s390_vec_read_element##BITS(v2, i); \
81 src = s390_vec_read_element##BITS(v3, i - (128 / BITS)); \
92 #define DEF_VPK(BITS, TBITS) \ argument
93 static uint##TBITS##_t vpk##BITS##e(uint##BITS##_t src, int *saturated) \
[all …]
H A Dvec_string_helper.c47 * Returns the number of bits composing one element.
82 const int bits = get_element_bits(es); in vfae() local
95 for (i = 0; i < 64; i += bits) { in vfae()
117 e0 = (e0 >> (bits - 1)) * get_single_element_mask(es); in vfae()
118 e1 = (e1 >> (bits - 1)) * get_single_element_mask(es); in vfae()
136 #define DEF_VFAE_HELPER(BITS) \ argument
137 void HELPER(gvec_vfae##BITS)(void *v1, const void *v2, const void *v3, \
144 vfae(v1, v2, v3, in, rt, zs, MO_##BITS); \
150 #define DEF_VFAE_CC_HELPER(BITS) \ argument
151 void HELPER(gvec_vfae_cc##BITS)(void *v1, const void *v2, const void *v3, \
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/upm/upm/
H A D0001-Use-stdint-types.patch26 - u_int8_t bits = (u_int8_t)std::stoul(tok.substr(20), nullptr, 0);
27 + uint8_t bits = (uint8_t)std::stoul(tok.substr(20), nullptr, 0);
28 setInterruptEnable0(bits);
31 - u_int8_t bits = (u_int8_t)std::stoul(tok.substr(20), nullptr, 0);
32 + uint8_t bits = (uint8_t)std::stoul(tok.substr(20), nullptr, 0);
33 setInterruptEnable1(bits);
36 - u_int8_t bits = (u_int8_t)std::stoul(tok.substr(20), nullptr, 0);
37 + uint8_t bits = (uint8_t)std::stoul(tok.substr(20), nullptr, 0);
38 setInterruptEnable2(bits);
41 - u_int8_t bits = (u_int8_t)std::stoul(tok.substr(17), nullptr, 0);
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3399-op1-opp.dtsi12 opp-hz = /bits/ 64 <408000000>;
17 opp-hz = /bits/ 64 <600000000>;
21 opp-hz = /bits/ 64 <816000000>;
25 opp-hz = /bits/ 64 <1008000000>;
29 opp-hz = /bits/ 64 <1200000000>;
33 opp-hz = /bits/ 64 <1416000000>;
37 opp-hz = /bits/ 64 <1512000000>;
47 opp-hz = /bits/ 64 <408000000>;
52 opp-hz = /bits/ 64 <600000000>;
56 opp-hz = /bits/ 64 <816000000>;
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dddr.c115 int bits = 0;/* Number of address bits */ in imx_ddr_size() local
117 /* Count data bus width bits */ in imx_ddr_size()
120 bits += 2 - field_val; in imx_ddr_size()
121 /* Count rank address bits */ in imx_ddr_size()
124 bits += field_val - 1; in imx_ddr_size()
125 /* Count column address bits */ in imx_ddr_size()
126 bits += 2;/* Column address 0 and 1 are fixed mapped */ in imx_ddr_size()
130 bits++; in imx_ddr_size()
133 bits++; in imx_ddr_size()
136 bits++; in imx_ddr_size()
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D112.out6 qemu-img: TEST_DIR/t.IMGFMT: Refcount width must be a power of two and may not exceed 64 bits
8 qemu-img: TEST_DIR/t.IMGFMT: Refcount width must be a power of two and may not exceed 64 bits
10 qemu-img: TEST_DIR/t.IMGFMT: Refcount width must be a power of two and may not exceed 64 bits
12 qemu-img: TEST_DIR/t.IMGFMT: Refcount width must be a power of two and may not exceed 64 bits
14 refcount bits: 1
16 refcount bits: 64
18 refcount bits: 16
23 refcount bits: 16
25 qemu-img: TEST_DIR/t.IMGFMT: Different refcount widths than 16 bits require compatibility level 1.1…
27 qemu-img: TEST_DIR/t.IMGFMT: Different refcount widths than 16 bits require compatibility level 1.1…
[all …]
/openbmc/u-boot/drivers/video/
H A Dmvebu_lcd.c152 * Bits 31-28: Duty Cycle of Backlight. value/16=High (0x8=Mid Setting) in mvebu_lcd_register_init()
153 * Bits 25-16: Backlight divider from 32kHz Clock in mvebu_lcd_register_init()
155 * Bits 15-00: Line Length in Bytes in mvebu_lcd_register_init()
162 * Bits 31-16: Vertical start of graphical overlay on screen in mvebu_lcd_register_init()
163 * Bits 15-00: Horizontal start of graphical overlay on screen in mvebu_lcd_register_init()
169 * Bits 31-16: Vertical size of graphical overlay 320=0x140 in mvebu_lcd_register_init()
170 * Bits 15-00: Horizontal size of graphical overlay 240=0xF0 in mvebu_lcd_register_init()
177 * Bits 31-16: Vertical size of graphical overlay 320=0x140 in mvebu_lcd_register_init()
178 * Bits 15-00: Horizontal size of graphical overlay 240=0xF0 in mvebu_lcd_register_init()
185 * Bits 31-16: Vertical position of HW Cursor 320=0x140 in mvebu_lcd_register_init()
[all …]
/openbmc/u-boot/lib/zlib/
H A Dinftrees.h14 table that indexes more bits of the code. op indicates whether
17 pointer, the low four bits of op is the number of index bits of
18 that table. For a length or distance, the low four bits of op
19 is the number of extra bits to get after the code. bits is
20 the number of bits in this code or part of the code to drop off
25 unsigned char op; /* operation, extra bits, table bits */
26 unsigned char bits; /* bits in this part of the code */ member
32 0000tttt - table link, tttt != 0 is the number of table index bits
33 0001eeee - length or distance, eeee is the number of extra bits
55 unsigned FAR *bits, unsigned short FAR *work));
H A Dinffast.c48 state->bits < 8
58 - The maximum input bits used by a length/distance pair is 15 bits for the
59 length code, 5 bits for the length extra, 15 bits for the distance code,
60 and 13 bits for the distance extra. This totals 48 bits, or six bytes.
86 unsigned bits; /* local strm->bits */ in inflate_fast() local
92 unsigned op; /* code bits, operation, extra bits, or */ in inflate_fast()
121 bits = state->bits; in inflate_fast()
130 if (bits < 15) { in inflate_fast()
131 hold += (unsigned long)(PUP(in)) << bits; in inflate_fast()
132 bits += 8; in inflate_fast()
[all …]
H A Dinflate.c26 state->bits = 0; in inflateReset()
185 bits = state->bits; \
196 state->bits = bits; \
203 bits = 0; \
212 hold += (unsigned long)(*next++) << bits; \
213 bits += 8; \
216 /* Assure that there are at least n bits in the bit accumulator. If there is
220 while (bits < (unsigned)(n)) \
224 /* Return the low n bits of the bit accumulator (n < 16) */
225 #define BITS(n) \ macro
[all …]
/openbmc/qemu/docs/devel/testing/
H A Dacpi-bits.rst9 `here <https://github.com/biosbits/bits/tree/master>`__. It is a software that
13 operating system getting involved in between. Bios-bits has python integration
32 bios-bits very attractive for testing bioses. More details on the inspiration
36 For QEMU, we maintain a fork of bios bits in `gitlab`_, along with all
39 bits. The author of this document is the current maintainer of the QEMU
40 fork of bios bits repository. For more information, please see `the
41 author's FOSDEM presentation <FOSDEM_>`__ on this bios-bits based test framework.
43 .. _Plumbers: https://blog.linuxplumbersconf.org/2011/ocw/system/presentations/867/original/bits.pdf
45 .. _gitlab: https://gitlab.com/qemu-project/biosbits-bits
61 ├── acpi-bits
[all …]
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-matmap.h173 * whose bits n*4+3 .. n*4 index the list of page sizes for way n
185 #define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
186 #define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
193 #define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */
225 #define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
230 #define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
231 #define XCHAL_ITLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if…
232 #define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all…
233 #define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
246 #define XCHAL_ITLB_SET1_PAGESZ_BITS 0 /* number of bits to encode the page size */
[all …]
/openbmc/qemu/scripts/kvm/
H A Dvmxcap44 def __init__(self, name, bits, cap_msr, true_cap_msr = None): argument
46 self.bits = bits
59 for bit in sorted(self.bits.keys()):
74 print(' %-40s %s' % (self.bits[bit], s))
76 # All 64 bits in the tertiary controls MSR are allowed-1
84 def __init__(self, name, bits, msr): argument
86 self.bits = bits
97 for bits in sorted(self.bits.keys(), key = first_bit):
98 if type(bits) is tuple:
99 lo, hi = bits
[all …]
/openbmc/openbmc/poky/meta/recipes-core/glibc/glibc/
H A D0016-wordsize.h-Unify-the-header-between-arm-and-aarch64.patch14 sysdeps/aarch64/bits/wordsize.h | 11 +++++++++--
15 sysdeps/arm/bits/wordsize.h | 22 +---------------------
17 mode change 100644 => 120000 sysdeps/arm/bits/wordsize.h
19 diff --git a/sysdeps/aarch64/bits/wordsize.h b/sysdeps/aarch64/bits/wordsize.h
21 --- a/sysdeps/aarch64/bits/wordsize.h
22 +++ b/sysdeps/aarch64/bits/wordsize.h
45 diff --git a/sysdeps/arm/bits/wordsize.h b/sysdeps/arm/bits/wordsize.h
48 --- a/sysdeps/arm/bits/wordsize.h
72 diff --git a/sysdeps/arm/bits/wordsize.h b/sysdeps/arm/bits/wordsize.h
76 +++ b/sysdeps/arm/bits/wordsize.h
[all …]
/openbmc/qemu/tests/functional/
H A Dtest_acpi_bits.py29 This test uses a fork of the upstream bits and has numerous fixes
31 https://gitlab.com/qemu-project/biosbits-bits .
49 # default timeout of 120 secs is sometimes not enough for bits test.
54 A QEMU VM, with isa-debugcon enabled and bits iso passed
70 name = "qemu-bits-%d" % os.getpid()
108 # this is the latest bits release as of today.
109 BITS_TAG = "qemu-bits-10262023"
112 "biosbits-bits/-/jobs/artifacts/%s/"
113 "download?job=qemu-bits-build" % BITS_TAG),
130 """ copies the bios bits config file into bits.
[all …]
/openbmc/qemu/rust/hw/char/pl011/src/
H A Dregisters.rs12 use bits::bits;
76 /// Receive Status Register / Data Register common error bits
94 /// read for RX. It is a 12-bit register, where bits 7..0 are the
95 /// character and bits 11..8 are error bits.
114 /// status error bits that can be found in bits 11..8 of the UARTDR
116 /// status bits correspond to that character that was just read.
121 /// bits.
136 // All the bits are cleared to 0 on reset. in reset()
205 /// STP2: Two stop bits select
209 /// WLEN: Word length in bits
[all …]
/openbmc/qemu/docs/devel/
H A Dloads-stores.rst37 - ``b`` : 8 bits
38 - ``w`` : 16 bits
39 - ``24`` : 24 bits
40 - ``l`` : 32 bits
41 - ``q`` : 64 bits
113 - ``b`` : 8 bits
114 - ``w`` : 16 bits
115 - ``l`` : 32 bits
116 - ``q`` : 64 bits
147 - ``b`` : 8 bits
[all …]
/openbmc/qemu/util/
H A Dbitmap.c18 * bitmaps provide an array of bits, implemented using an
19 * array of unsigned longs. The number of valid bits in a
23 * The possible unused bits in the last, partially used word
29 * carefully filter out these unused bits from impacting their
34 * unused bits set, then they won't output any set unused bits
41 int slow_bitmap_empty(const unsigned long *bitmap, long bits) in slow_bitmap_empty() argument
43 long k, lim = bits/BITS_PER_LONG; in slow_bitmap_empty()
50 if (bits % BITS_PER_LONG) { in slow_bitmap_empty()
51 if (bitmap[k] & BITMAP_LAST_WORD_MASK(bits)) { in slow_bitmap_empty()
59 int slow_bitmap_full(const unsigned long *bitmap, long bits) in slow_bitmap_full() argument
[all …]
/openbmc/qemu/
H A Dpage-vary-common.c29 bool set_preferred_target_page_bits_common(int bits) in set_preferred_target_page_bits_common() argument
37 if (target_page.bits == 0 || target_page.bits > bits) { in set_preferred_target_page_bits_common()
41 target_page.bits = bits; in set_preferred_target_page_bits_common()
48 if (target_page.bits == 0) { in finalize_target_page_bits_common()
49 target_page.bits = min; in finalize_target_page_bits_common()
51 target_page.mask = -1ull << target_page.bits; in finalize_target_page_bits_common()
/openbmc/u-boot/arch/arm/include/asm/mach-imx/
H A Dregs-common.h20 * 2) Set bits only access. To set bits, write which bits you want to set to the
22 * 3) Clear bits only access. To clear bits, write which bits you want to clear
24 * 4) Toggle bits only access. To toggle bits, write which bits you want to
27 * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
/openbmc/openbmc/poky/meta/recipes-core/musl/musl/
H A D0001-Update-syscalls-for-r32-rv64-from-kernel-6.4-through.patch9 arch/riscv32/bits/syscall.h.in | 11 +++++++++++
10 arch/riscv64/bits/syscall.h.in | 11 +++++++++++
13 diff --git a/arch/riscv32/bits/syscall.h.in b/arch/riscv32/bits/syscall.h.in
15 --- a/arch/riscv32/bits/syscall.h.in
16 +++ b/arch/riscv32/bits/syscall.h.in
42 diff --git a/arch/riscv64/bits/syscall.h.in b/arch/riscv64/bits/syscall.h.in
44 --- a/arch/riscv64/bits/syscall.h.in
45 +++ b/arch/riscv64/bits/syscall.h.in
/openbmc/qemu/tests/functional/acpi-bits/bits-config/
H A Dbits-cfg.txt1 # BITS configuration file
2 [bits]
4 # To run BITS in batch mode, set batch to a list of one or more of the
5 # following keywords; BITS will then run all of the requested operations, then
8 # test: Run the full BITS testsuite.
16 # please take a look at boot/python/init.py in bits zip file

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