pl011/src/registers.rs

12 use bits::bits;
76 /// Receive Status Register / Data Register common error bits
94 /// read for RX. It is a 12-bit register, where bits 7..0 are the
95 /// character and bits 11..8 are error bits.
114 /// status error bits that can be found in bits 11..8 of the UARTDR
116 /// status bits correspond to that character that was just read.
121 /// bits.
136         // All the bits are cleared to 0 on reset.  in reset()
205     /// STP2: Two stop bits select
209     /// WLEN: Word length in bits
210     /// b11 = 8 bits
211     /// b10 = 7 bits
212     /// b01 = 6 bits
213     /// b00 = 5 bits.
224         // All the bits are cleared to 0 when reset.  in reset()
260 /// These bits indicate the number of data bits transmitted or received in a
263     /// b11 = 8 bits
265     /// b10 = 7 bits
267     /// b01 = 6 bits
269     /// b00 = 5 bits.
276 /// enable bits, and the bits to write to set the usual outbound RS232
277 /// modem control signals. All bits reset to 0 except TXE and RXE.
330 bits! {
331     /// Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC
346         E = bits!(Self as u32: OE | BE | PE | FE),
347         MS = bits!(Self as u32: RI | DSR | DCD | CTS),