152 	 * Bits 31-28: Duty Cycle of Backlight. value/16=High (0x8=Mid Setting)  in mvebu_lcd_register_init()
153 	 * Bits 25-16: Backlight divider from 32kHz Clock  in mvebu_lcd_register_init()
155 	 * Bits 15-00: Line Length in Bytes  in mvebu_lcd_register_init()
162 	 * Bits 31-16: Vertical start of graphical overlay on screen  in mvebu_lcd_register_init()
163 	 * Bits 15-00: Horizontal start of graphical overlay on screen  in mvebu_lcd_register_init()
169 	 * Bits 31-16: Vertical size of graphical overlay 320=0x140  in mvebu_lcd_register_init()
170 	 * Bits 15-00: Horizontal size of graphical overlay 240=0xF0  in mvebu_lcd_register_init()
177 	 * Bits 31-16: Vertical size of graphical overlay 320=0x140  in mvebu_lcd_register_init()
178 	 * Bits 15-00: Horizontal size of graphical overlay 240=0xF0  in mvebu_lcd_register_init()
185 	 * Bits 31-16: Vertical position of HW Cursor 320=0x140  in mvebu_lcd_register_init()
186 	 * Bits 15-00: Horizontal position of HW Cursor 240=0xF0  in mvebu_lcd_register_init()
192 	 * Bits 31-16: Vertical size of HW Cursor  in mvebu_lcd_register_init()
193 	 * Bits 15-00: Horizontal size of HW Cursor  in mvebu_lcd_register_init()
199 	 * Bits 31-16: Screen total vertical lines:  in mvebu_lcd_register_init()
205 	 * Bits 15-00: Screen total horizontal pixels:  in mvebu_lcd_register_init()
221 	 * Bits 31-16: Screen active vertical lines 320=0x140  in mvebu_lcd_register_init()
222 	 * Bits 15-00: Screen active horizontakl pixels 240=0x00F0  in mvebu_lcd_register_init()
228 	 * Bits 31-16: Screen horizontal backporch 44=0x2c  in mvebu_lcd_register_init()
229 	 * Bits 15-00: Screen horizontal frontporch 2=0x02  in mvebu_lcd_register_init()
238 	 * Bits 31-16: Screen vertical backporch  2=0x02  in mvebu_lcd_register_init()
239 	 * Bits 15-00: Screen vertical frontporch 2=0x02  in mvebu_lcd_register_init()
261 	 * Bits 31-12: Reservd  in mvebu_lcd_register_init()
266 	 * Bits 07-00: Empty 8B FIFO entries to trigger DMA, default=0x80  in mvebu_lcd_register_init()
280 	 * Bits 23-20: Graphics Memory Color Format: 0x1=RGB1555  in mvebu_lcd_register_init()
281 	 * Bits 19-16: Video Memory Color Format:    0x1=RGB1555  in mvebu_lcd_register_init()
304 	 * Bits 30-28: DMA Trigger Source: 0x2 VSYNC  in mvebu_lcd_register_init()
306 	 * Bits 26-24: Color Key Mode: 0=disable  in mvebu_lcd_register_init()
307 	 * Bit     23: Fill low bits: 0=fill with zeroes  in mvebu_lcd_register_init()
311 	 * Bits 19-18: Reserved  in mvebu_lcd_register_init()
312 	 * Bits 17-16: Configure Video/Graphic Path: 0x1: Graphic path alpha.  in mvebu_lcd_register_init()
313 	 * Bits 15-08: Configure Alpha: 0x00.  in mvebu_lcd_register_init()
314 	 * Bits 07-00: Reserved.  in mvebu_lcd_register_init()
321 	 * Bits 15-14: SRAM control: init=0x3, Read=0, Write=2  in mvebu_lcd_register_init()
322 	 * Bits 11-08: SRAM address ID: 0=gamma_yr, 1=gammy_ug, 2=gamma_vb,  in mvebu_lcd_register_init()
339 	 * Bits 31-16: Brightness sign ext. 8-bit value +255 to -255: default=0  in mvebu_lcd_register_init()
340 	 * Bits 15-00: Contrast sign ext. 8-bit value +255 to -255: default=0  in mvebu_lcd_register_init()
346 	 * Bits 31-16: Multiplier signed 4.12 fixed point value  in mvebu_lcd_register_init()
347 	 * Bits 15-00: Saturation signed 4.12 fixed point value  in mvebu_lcd_register_init()
353 	 * Bits 31-16: Sine signed 2.14 fixed point value  in mvebu_lcd_register_init()
354 	 * Bits 15-00: Cosine signed 2.14 fixed point value  in mvebu_lcd_register_init()
360 	 * Bits 31-28: LCD Type: 3=18 bit RGB | 6=24 bit RGB888  in mvebu_lcd_register_init()
361 	 * Bits 27-12: Reserved  in mvebu_lcd_register_init()
363 	 * Bits 10-09: Reserved  in mvebu_lcd_register_init()
380 	 * Bits 31-20: Reserved  in mvebu_lcd_register_init()
381 	 * Bits 19-18: Vertical Interpolation: 0=Disable  in mvebu_lcd_register_init()
382 	 * Bits 17-16: Reserved  in mvebu_lcd_register_init()
389 	 * Bits 09-08: YUV to RGB Color space conversion: 0 (Not used)  in mvebu_lcd_register_init()
390 	 * Bits 07-04: AXI Bus Master: 0x4: no crossing of 4k boundary,  in mvebu_lcd_register_init()
392 	 * Bits 03-00: LCD pins: ??? 0=24-bit Dump panel ??  in mvebu_lcd_register_init()
408 	 * Bits 31-29: 0x0 = Fastest Delay Line (default)  in mvebu_lcd_register_init()
414 	 * Bits 24-22: Manual calibration value.  in mvebu_lcd_register_init()
417 	 * Bits 19-16: Calibration Threshold voltage, default= 0x2  in mvebu_lcd_register_init()
419 	 * Bits 13-11: Divisor for ADDL Clock: 0x1=/2, 0x3=/8, 0x5=/16  in mvebu_lcd_register_init()
421 	 * Bits 09-08: Test point configuration: 0x2=Bias, 0x3=High-z  in mvebu_lcd_register_init()
424 	 * Bits 05-00: Delay taps, 0x3F=Half Cycle, 0x00=No delay  in mvebu_lcd_register_init()
431 	 * Bits 3 and 4 must be 1  in mvebu_lcd_register_init()
437 	 * Bits 03-00: Sets the delay for the HSYNC and VSYNC signals  in mvebu_lcd_register_init()
461 	 * Bits 31-30: SCLCK Source: 0=AXIBus, 1=AHBus, 2=PLLDivider0  in mvebu_lcd_register_init()
462 	 * Bits 15-01: Clock Divider: Bypass for LVDS=0x0001  in mvebu_lcd_register_init()
470 	 * Bits 30-29: Reserved  in mvebu_lcd_register_init()
471 	 * Bits 28-26: PLL_KDIV: This encodes K  in mvebu_lcd_register_init()
473 	 * Bits 25-17: PLL_MDIV: This is M-1:  in mvebu_lcd_register_init()
475 	 * Bits 16-13: VCO band: 0x1 for 700-920MHz  in mvebu_lcd_register_init()
476 	 * Bits 12-04: PLL_NDIV: This is N-1 and corresponds to R1_CTRL!  in mvebu_lcd_register_init()
478 	 * Bits 03-00: R1_CTRL (for N=28 => 0x4)  in mvebu_lcd_register_init()
484 	 * Bits 31-19: Reserved  in mvebu_lcd_register_init()
489 	 * Bits 14-13: Reserved  in mvebu_lcd_register_init()
490 	 * Bits 12-00: PLL Full Divider [Note: Assumed to be the Post-Divider  in mvebu_lcd_register_init()
499 	 * Bits 29-11: Reserved  in mvebu_lcd_register_init()
501 	 * Bits 07-02: Reserved  in mvebu_lcd_register_init()
504 	 * Note: Bits 0 and must be verified with the help of the  in mvebu_lcd_register_init()