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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dfsl-qdma.txt8 - compatible: Must be one of
9 "fsl,ls1021a-qdma": for LS1021A Board
10 "fsl,ls1028a-qdma": for LS1028A Board
11 "fsl,ls1043a-qdma": for ls1043A Board
12 "fsl,ls1046a-qdma": for ls1046A Board
13 - reg: Should contain the register's base address and length.
14 - interrupts: Should contain a reference to the interrupt used by this
16 - interrupt-names: Should contain interrupt names:
17 "qdma-queue0": the block0 interrupt
18 "qdma-queue1": the block1 interrupt
[all …]
/openbmc/linux/drivers/usb/host/
H A Dohci.h1 /* SPDX-License-Identifier: GPL-1.0+ */
6 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
27 /* first fields are hardware-specified */
49 struct ed *ed_prev; /* for non-interrupt EDs */
53 /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
54 * usually: OPER --> UNLINK --> (IDLE | OPER) --> ...
76 ((int) (ohci->wdh_cnt - ed->takeback_wdh_cnt) >= 0)
89 /* first fields are hardware-specified */
124 * big-endian PPC hardware that's the second entry.
132 struct td *td_hash; /* dma-->td hashtable */
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H A Dehci-ppc-of.c1 // SPDX-License-Identifier: GPL-1.0+
5 * Bus Glue for PPC On-Chip EHCI driver on the of_platform bus
10 * Based on "ehci-ppc-soc.c" by Stefan Roese <sr@denx.de>
11 * and "ohci-ppc-of.c" by Sylvain Munaut <tnt@246tNt.com>
85 return -EINVAL; in ppc44x_enable_bmt()
96 struct device_node *dn = op->dev.of_node; in ehci_hcd_ppc_of_probe()
106 return -ENODEV; in ehci_hcd_ppc_of_probe()
108 dev_dbg(&op->dev, "initializing PPC-OF USB Controller\n"); in ehci_hcd_ppc_of_probe()
114 hcd = usb_create_hcd(&ehci_ppc_of_hc_driver, &op->dev, "PPC-OF USB"); in ehci_hcd_ppc_of_probe()
116 return -ENOMEM; in ehci_hcd_ppc_of_probe()
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H A Dohci-platform.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright 2011-2012 Hauke Mehrtens <hauke@hauke-m.de>
9 * Derived from the OCHI-SSB driver
10 * Derived from the OHCI-PCI driver
12 * Copyright 2000-2002 David Brownell
18 #include <linux/dma-mapping.h>
37 #define hcd_to_ohci_priv(h) ((struct ohci_platform_priv *)hcd_to_ohci(h)->priv)
50 for (clk = 0; clk < OHCI_MAX_CLKS && priv->clks[clk]; clk++) { in ohci_platform_power_on()
51 ret = clk_prepare_enable(priv->clks[clk]); in ohci_platform_power_on()
59 while (--clk >= 0) in ohci_platform_power_on()
[all …]
H A Dehci-xilinx-of.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Based on "ehci-ppc-of.c" by Valentine Barshak <vbarshak@ru.mvista.com>
10 * and "ehci-ppc-soc.c" by Stefan Roese <sr@denx.de>
11 * and "ohci-ppc-of.c" by Sylvain Munaut <tnt@246tNt.com>
23 * ehci_xilinx_port_handed_over - hand the port out if failed to enable it
40 dev_warn(hcd->self.controller, "port %d cannot be enabled\n", portnum); in ehci_xilinx_port_handed_over()
41 if (hcd->has_tt) { in ehci_xilinx_port_handed_over()
42 dev_warn(hcd->self.controller, in ehci_xilinx_port_handed_over()
45 dev_warn(hcd->self.controller, in ehci_xilinx_port_handed_over()
48 dev_warn(hcd->self.controller, in ehci_xilinx_port_handed_over()
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H A Duhci-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */
80 /* PCI Intel-specific resume-enable register */
97 /* When no queues need Full-Speed Bandwidth Reclamation,
110 * To facilitate the strongest possible byte-order checking from "sparse"
127 * with each endpoint, and qh->element (updated by the HC) is either:
128 * - the next unprocessed TD in the endpoint's queue, or
129 * - UHCI_PTR_TERM (when there's no more traffic for this endpoint).
133 * place. Then qh->element is UHCI_PTR_TERM.
135 * In the schedule, qh->link maintains a list of QHs seen by the HC:
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H A Duhci-grlib.c1 // SPDX-License-Identifier: GPL-2.0
9 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
16 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
17 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
18 * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
34 * with bit 7 (0x80) turned on then the current little-endian in uhci_grlib_init()
36 * byte-swapped; hence the register interface and presumably in uhci_grlib_init()
37 * also the descriptors are big-endian. in uhci_grlib_init()
40 uhci->big_endian_mmio = 1; in uhci_grlib_init()
41 uhci->big_endian_desc = 1; in uhci_grlib_init()
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H A Dehci-platform.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright 2010-2012 Hauke Mehrtens <hauke@hauke-m.de>
9 * Derived from the ohci-ssb driver
12 * Derived from the EHCI-PCI driver
13 * Copyright (c) 2000-2004 by David Brownell
15 * Derived from the ohci-pci driver
17 * Copyright 2000-2002 David Brownell
23 #include <linux/dma-mapping.h>
43 #define hcd_to_ehci_priv(h) ((struct ehci_platform_priv *)hcd_to_ehci(h)->priv)
58 struct platform_device *pdev = to_platform_device(hcd->self.controller); in ehci_platform_reset()
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
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H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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H A Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dgeneric-ohci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/generic-ohci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
15 - items:
16 - enum:
17 - allwinner,sun4i-a10-ohci
18 - allwinner,sun50i-a64-ohci
19 - allwinner,sun50i-h6-ohci
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H A Dgeneric-ehci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/generic-ehci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
13 - $ref: usb-hcd.yaml
14 - if:
19 const: ibm,usb-ehci-440epx
28 - items:
29 - enum:
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/openbmc/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
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/openbmc/linux/Documentation/devicetree/bindings/mips/cavium/
H A Ductl.txt4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
24 compatible = "cavium,octeon-6335-uctl";
27 #address-cells = <2>;
28 #size-cells = <2>;
[all …]
/openbmc/linux/drivers/dma/
H A Dfsl-edma-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
10 #include <linux/dma-mapping.h>
14 #include "fsl-edma-common.h"
48 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
50 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler()
52 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
56 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler()
57 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler()
58 vchan_cookie_complete(&fsl_chan->edesc->vdesc); in fsl_edma_tx_chan_handler()
[all …]
H A Dfsl-edma-common.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
9 #include <linux/dma-direction.h>
11 #include "virt-dma.h"
230 struct edma_regs regs;
236 (sizeof(chan->tcd->__name) == sizeof(u32) ? \
237 edma_readl(chan->edm
229 struct edma_regs regs; global() member
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/openbmc/linux/drivers/phy/broadcom/
H A Dphy-brcm-usb-init.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014-2017 Broadcom
60 void __iomem *regs[BRCM_REGS_MAX]; member
84 * bus endianness (i.e., big-endian CPU + big endian bus ==> native in brcm_usb_readl()
85 * endian I/O). in brcm_usb_readl()
87 * Other architectures (e.g., ARM) either do not support big endian, or in brcm_usb_readl()
88 * else leave I/O in little endian mode. in brcm_usb_readl()
117 if (ini->ops->init_ipp) in brcm_usb_init_ipp()
118 ini->ops->init_ipp(ini); in brcm_usb_init_ipp()
123 if (ini->ops->init_common) in brcm_usb_init_common()
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/openbmc/linux/arch/mips/include/asm/sgi/
H A Dhpc3.h36 /* The set of regs for each HPC3 PBUS DMA channel. */
40 u32 _unused0[0x1000/4 - 2]; /* padding */
48 #define HPC3_PDMACTRL_SEL 0x00000002 /* little endian transfer */
54 #define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
58 u32 _unused1[0x1000/4 - 1]; /* padding */
65 u32 _unused0[0x1000/4 - 2]; /* padding */
73 #define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
89 #define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
100 #define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
105 u32 _unused1[0x1000/4 - 6]; /* padding */
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/openbmc/linux/drivers/gpio/
H A Dgpio-mpc8xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
37 void __iomem *regs; member
48 * This hardware has a big endian bit assignment such that GPIO line 0 is
54 return BIT(31 - offset); in mpc_pin2mask()
68 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); in mpc8572_gpio_get()
69 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; in mpc8572_gpio_get()
70 out_shadow = gc->bgpio_data & out_mask; in mpc8572_gpio_get()
81 return -EINVAL; in mpc5121_gpio_dir_out()
83 return mpc8xxx_gc->direction_output(gc, gpio, val); in mpc5121_gpio_dir_out()
92 return -EINVAL; in mpc5125_gpio_dir_out()
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/openbmc/linux/arch/arm64/include/asm/
H A Dsyscall.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 typedef long (*syscall_fn_t)(const struct pt_regs *regs);
21 struct pt_regs *regs) in syscall_get_nr() argument
23 return regs->syscallno; in syscall_get_nr()
27 struct pt_regs *regs) in syscall_rollback() argument
29 regs->regs[0] = regs->orig_x0; in syscall_rollback()
33 struct pt_regs *regs) in syscall_get_return_value() argument
35 unsigned long val = regs->regs[0]; in syscall_get_return_value()
44 struct pt_regs *regs) in syscall_get_error() argument
46 unsigned long error = syscall_get_return_value(task, regs); in syscall_get_error()
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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dlayerscape-pci.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 which is used to describe the PLL settings at the time of chip-reset.
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
22 "fsl,ls1043a-pcie"
23 "fsl,ls1012a-pcie"
[all …]
/openbmc/linux/include/video/
H A Dsstfb.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/drivers/video/sstfb.h -- voodoo graphics frame buffer
105 # define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */
106 # define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */
108 # define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */
109 # define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */
192 # define BLT_SCR2SCR_BITBLT 0 /* Screen-to-Screen BitBLT */
193 # define BLT_CPU2SCR_BITBLT 1 /* CPU-to-screen BitBLT */
195 # define BLT_16BPP_FMT 2 /* 16 BPP (5-6-5 RGB) */
196 #define BLTDATA 0x02fc /* BitBLT data for CPU-to-Screen BitBLTs */
[all …]
/openbmc/linux/drivers/base/regmap/
H A Dregmap-mmio.c1 // SPDX-License-Identifier: GPL-2.0
3 // Register map access API - MMIO support
18 void __iomem *regs; member
39 return -EINVAL; in regmap_mmio_regbits_check()
59 return -EINVAL; in regmap_mmio_get_min_stride()
69 writeb(val, ctx->regs + reg); in regmap_mmio_write8()
76 writeb_relaxed(val, ctx->regs + reg); in regmap_mmio_write8_relaxed()
82 iowrite8(val, ctx->regs + reg); in regmap_mmio_iowrite8()
89 writew(val, ctx->regs + reg); in regmap_mmio_write16le()
96 writew_relaxed(val, ctx->regs + reg); in regmap_mmio_write16le_relaxed()
[all …]
/openbmc/linux/arch/arm64/lib/
H A Dstrncmp.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2013-2022, Arm Limited.
6 * https://github.com/ARM-software/optimized-routines/blob/189dfefe37d54c5b/string/aarch64/strncmp.S
14 * ARMv8-a, AArch64.
48 /* Define endian dependent shift operations.
49 On big-endian early bytes are at MSB and on little-endian LSB.
70 /* NUL detection works on the principle that (X - 1) & (~X) & 0x80
71 (=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
81 eor diff, data1, data2 /* Non-zero if differences found. */
83 bics has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */
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