1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 21da177e4SLinus Torvalds /* 31da177e4SLinus Torvalds * linux/drivers/video/sstfb.h -- voodoo graphics frame buffer 41da177e4SLinus Torvalds * 51da177e4SLinus Torvalds * Copyright (c) 2000,2001 Ghozlane Toumi <gtoumi@messel.emse.fr> 61da177e4SLinus Torvalds * 71da177e4SLinus Torvalds * Created 28 Aug 2001 by Ghozlane Toumi 81da177e4SLinus Torvalds */ 91da177e4SLinus Torvalds 101da177e4SLinus Torvalds 111da177e4SLinus Torvalds #ifndef _SSTFB_H_ 121da177e4SLinus Torvalds #define _SSTFB_H_ 131da177e4SLinus Torvalds 141da177e4SLinus Torvalds /* 151da177e4SLinus Torvalds * 161da177e4SLinus Torvalds * Debug Stuff 171da177e4SLinus Torvalds * 181da177e4SLinus Torvalds */ 191da177e4SLinus Torvalds 201da177e4SLinus Torvalds #ifdef SST_DEBUG 211da177e4SLinus Torvalds # define dprintk(X...) printk("sstfb: " X) 221da177e4SLinus Torvalds # define SST_DEBUG_REG 1 231da177e4SLinus Torvalds # define SST_DEBUG_FUNC 1 241da177e4SLinus Torvalds # define SST_DEBUG_VAR 1 251da177e4SLinus Torvalds #else 26*57e4bc8aSSam Ravnborg # define dprintk(X...) no_printk(X) 271da177e4SLinus Torvalds # define SST_DEBUG_REG 0 281da177e4SLinus Torvalds # define SST_DEBUG_FUNC 0 291da177e4SLinus Torvalds # define SST_DEBUG_VAR 0 301da177e4SLinus Torvalds #endif 311da177e4SLinus Torvalds 321da177e4SLinus Torvalds #if (SST_DEBUG_REG > 0) 331da177e4SLinus Torvalds # define r_dprintk(X...) dprintk(X) 341da177e4SLinus Torvalds #else 351da177e4SLinus Torvalds # define r_dprintk(X...) 361da177e4SLinus Torvalds #endif 371da177e4SLinus Torvalds #if (SST_DEBUG_REG > 1) 381da177e4SLinus Torvalds # define r_ddprintk(X...) dprintk(" " X) 391da177e4SLinus Torvalds #else 401da177e4SLinus Torvalds # define r_ddprintk(X...) 411da177e4SLinus Torvalds #endif 421da177e4SLinus Torvalds 431da177e4SLinus Torvalds #if (SST_DEBUG_FUNC > 0) 441da177e4SLinus Torvalds # define f_dprintk(X...) dprintk(X) 451da177e4SLinus Torvalds #else 461da177e4SLinus Torvalds # define f_dprintk(X...) 471da177e4SLinus Torvalds #endif 481da177e4SLinus Torvalds #if (SST_DEBUG_FUNC > 1) 491da177e4SLinus Torvalds # define f_ddprintk(X...) dprintk(" " X) 501da177e4SLinus Torvalds #else 51*57e4bc8aSSam Ravnborg # define f_ddprintk(X...) no_printk(X) 521da177e4SLinus Torvalds #endif 531da177e4SLinus Torvalds #if (SST_DEBUG_FUNC > 2) 541da177e4SLinus Torvalds # define f_dddprintk(X...) dprintk(" " X) 551da177e4SLinus Torvalds #else 561da177e4SLinus Torvalds # define f_dddprintk(X...) 571da177e4SLinus Torvalds #endif 581da177e4SLinus Torvalds 591da177e4SLinus Torvalds #if (SST_DEBUG_VAR > 0) 601da177e4SLinus Torvalds # define v_dprintk(X...) dprintk(X) 611da177e4SLinus Torvalds # define print_var(V, X...) \ 621da177e4SLinus Torvalds { \ 631da177e4SLinus Torvalds dprintk(X); \ 641da177e4SLinus Torvalds printk(" :\n"); \ 651da177e4SLinus Torvalds sst_dbg_print_var(V); \ 661da177e4SLinus Torvalds } 671da177e4SLinus Torvalds #else 681da177e4SLinus Torvalds # define v_dprintk(X...) 691da177e4SLinus Torvalds # define print_var(X,Y...) 701da177e4SLinus Torvalds #endif 711da177e4SLinus Torvalds 721da177e4SLinus Torvalds #define POW2(x) (1ul<<(x)) 731da177e4SLinus Torvalds 741da177e4SLinus Torvalds /* 751da177e4SLinus Torvalds * 761da177e4SLinus Torvalds * Const 771da177e4SLinus Torvalds * 781da177e4SLinus Torvalds */ 791da177e4SLinus Torvalds 801da177e4SLinus Torvalds /* pci stuff */ 811da177e4SLinus Torvalds #define PCI_INIT_ENABLE 0x40 821da177e4SLinus Torvalds # define PCI_EN_INIT_WR BIT(0) 831da177e4SLinus Torvalds # define PCI_EN_FIFO_WR BIT(1) 841da177e4SLinus Torvalds # define PCI_REMAP_DAC BIT(2) 851da177e4SLinus Torvalds #define PCI_VCLK_ENABLE 0xc0 /* enable video */ 861da177e4SLinus Torvalds #define PCI_VCLK_DISABLE 0xe0 871da177e4SLinus Torvalds 881da177e4SLinus Torvalds /* register offsets from memBaseAddr */ 891da177e4SLinus Torvalds #define STATUS 0x0000 901da177e4SLinus Torvalds # define STATUS_FBI_BUSY BIT(7) 911da177e4SLinus Torvalds #define FBZMODE 0x0110 921da177e4SLinus Torvalds # define EN_CLIPPING BIT(0) /* enable clipping */ 931da177e4SLinus Torvalds # define EN_RGB_WRITE BIT(9) /* enable writes to rgb area */ 941da177e4SLinus Torvalds # define EN_ALPHA_WRITE BIT(10) 951da177e4SLinus Torvalds # define ENGINE_INVERT_Y BIT(17) /* invert Y origin (pipe) */ 961da177e4SLinus Torvalds #define LFBMODE 0x0114 971da177e4SLinus Torvalds # define LFB_565 0 /* bits 3:0 .16 bits RGB */ 981da177e4SLinus Torvalds # define LFB_888 4 /* 24 bits RGB */ 991da177e4SLinus Torvalds # define LFB_8888 5 /* 32 bits ARGB */ 1001da177e4SLinus Torvalds # define WR_BUFF_FRONT 0 /* write buf select (front) */ 1011da177e4SLinus Torvalds # define WR_BUFF_BACK (1 << 4) /* back */ 1021da177e4SLinus Torvalds # define RD_BUFF_FRONT 0 /* read buff select (front) */ 1031da177e4SLinus Torvalds # define RD_BUFF_BACK (1 << 6) /* back */ 1041da177e4SLinus Torvalds # define EN_PXL_PIPELINE BIT(8) /* pixel pipeline (clip..)*/ 1051da177e4SLinus Torvalds # define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */ 1061da177e4SLinus Torvalds # define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */ 1071da177e4SLinus Torvalds # define LFB_INVERT_Y BIT(13) /* invert Y origin (LFB) */ 1081da177e4SLinus Torvalds # define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */ 1091da177e4SLinus Torvalds # define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */ 1101da177e4SLinus Torvalds #define CLIP_LEFT_RIGHT 0x0118 1111da177e4SLinus Torvalds #define CLIP_LOWY_HIGHY 0x011c 1121da177e4SLinus Torvalds #define NOPCMD 0x0120 1131da177e4SLinus Torvalds #define FASTFILLCMD 0x0124 1141da177e4SLinus Torvalds #define SWAPBUFFCMD 0x0128 1151da177e4SLinus Torvalds #define FBIINIT4 0x0200 /* misc controls */ 1161da177e4SLinus Torvalds # define FAST_PCI_READS 0 /* 1 waitstate */ 1171da177e4SLinus Torvalds # define SLOW_PCI_READS BIT(0) /* 2 ws */ 1181da177e4SLinus Torvalds # define LFB_READ_AHEAD BIT(1) 1191da177e4SLinus Torvalds #define BACKPORCH 0x0208 1201da177e4SLinus Torvalds #define VIDEODIMENSIONS 0x020c 1211da177e4SLinus Torvalds #define FBIINIT0 0x0210 /* misc+fifo controls */ 1220743b868SHelge Deller # define DIS_VGA_PASSTHROUGH BIT(0) 1231da177e4SLinus Torvalds # define FBI_RESET BIT(1) 1241da177e4SLinus Torvalds # define FIFO_RESET BIT(2) 1251da177e4SLinus Torvalds #define FBIINIT1 0x0214 /* PCI + video controls */ 1261da177e4SLinus Torvalds # define VIDEO_MASK 0x8080010f /* masks video related bits V1+V2*/ 1271da177e4SLinus Torvalds # define FAST_PCI_WRITES 0 /* 0 ws */ 1281da177e4SLinus Torvalds # define SLOW_PCI_WRITES BIT(1) /* 1 ws */ 1291da177e4SLinus Torvalds # define EN_LFB_READ BIT(3) 1301da177e4SLinus Torvalds # define TILES_IN_X_SHIFT 4 1311da177e4SLinus Torvalds # define VIDEO_RESET BIT(8) 1321da177e4SLinus Torvalds # define EN_BLANKING BIT(12) 1331da177e4SLinus Torvalds # define EN_DATA_OE BIT(13) 1341da177e4SLinus Torvalds # define EN_BLANK_OE BIT(14) 1351da177e4SLinus Torvalds # define EN_HVSYNC_OE BIT(15) 1361da177e4SLinus Torvalds # define EN_DCLK_OE BIT(16) 1371da177e4SLinus Torvalds # define SEL_INPUT_VCLK_2X 0 /* bit 17 */ 1381da177e4SLinus Torvalds # define SEL_INPUT_VCLK_SLAVE BIT(17) 1391da177e4SLinus Torvalds # define SEL_SOURCE_VCLK_SLAVE 0 /* bits 21:20 */ 1401da177e4SLinus Torvalds # define SEL_SOURCE_VCLK_2X_DIV2 (0x01 << 20) 1411da177e4SLinus Torvalds # define SEL_SOURCE_VCLK_2X_SEL (0x02 << 20) 1421da177e4SLinus Torvalds # define EN_24BPP BIT(22) 1431da177e4SLinus Torvalds # define TILES_IN_X_MSB_SHIFT 24 /* v2 */ 1441da177e4SLinus Torvalds # define VCLK_2X_SEL_DEL_SHIFT 27 /* vclk out delay 0,4,6,8ns */ 1451da177e4SLinus Torvalds # define VCLK_DEL_SHIFT 29 /* vclk in delay */ 1461da177e4SLinus Torvalds #define FBIINIT2 0x0218 /* Dram controls */ 1471da177e4SLinus Torvalds # define EN_FAST_RAS_READ BIT(5) 1481da177e4SLinus Torvalds # define EN_DRAM_OE BIT(6) 1491da177e4SLinus Torvalds # define EN_FAST_RD_AHEAD_WR BIT(7) 1501da177e4SLinus Torvalds # define VIDEO_OFFSET_SHIFT 11 /* unit: #rows tile 64x16/2 */ 1511da177e4SLinus Torvalds # define SWAP_DACVSYNC 0 1521da177e4SLinus Torvalds # define SWAP_DACDATA0 (1 << 9) 1531da177e4SLinus Torvalds # define SWAP_FIFO_STALL (2 << 9) 1541da177e4SLinus Torvalds # define EN_RD_AHEAD_FIFO BIT(21) 1551da177e4SLinus Torvalds # define EN_DRAM_REFRESH BIT(22) 1561da177e4SLinus Torvalds # define DRAM_REFRESH_16 (0x30 << 23) /* dram 16 ms */ 1571da177e4SLinus Torvalds #define DAC_READ FBIINIT2 /* in remap mode */ 1581da177e4SLinus Torvalds #define FBIINIT3 0x021c /* fbi controls */ 1591da177e4SLinus Torvalds # define DISABLE_TEXTURE BIT(6) 16025985edcSLucas De Marchi # define Y_SWAP_ORIGIN_SHIFT 22 /* Y swap subtraction value */ 1611da177e4SLinus Torvalds #define HSYNC 0x0220 1621da177e4SLinus Torvalds #define VSYNC 0x0224 1631da177e4SLinus Torvalds #define DAC_DATA 0x022c 1641da177e4SLinus Torvalds # define DAC_READ_CMD BIT(11) /* set read dacreg mode */ 1651da177e4SLinus Torvalds #define FBIINIT5 0x0244 /* v2 specific */ 1661da177e4SLinus Torvalds # define FBIINIT5_MASK 0xfa40ffff /* mask video bits*/ 1671da177e4SLinus Torvalds # define HDOUBLESCAN BIT(20) 1681da177e4SLinus Torvalds # define VDOUBLESCAN BIT(21) 1691da177e4SLinus Torvalds # define HSYNC_HIGH BIT(23) 1701da177e4SLinus Torvalds # define VSYNC_HIGH BIT(24) 1711da177e4SLinus Torvalds # define INTERLACE BIT(26) 1721da177e4SLinus Torvalds #define FBIINIT6 0x0248 /* v2 specific */ 1731da177e4SLinus Torvalds # define TILES_IN_X_LSB_SHIFT 30 /* v2 */ 1741da177e4SLinus Torvalds #define FBIINIT7 0x024c /* v2 specific */ 1751da177e4SLinus Torvalds 1761da177e4SLinus Torvalds #define BLTSRCBASEADDR 0x02c0 /* BitBLT Source base address */ 1771da177e4SLinus Torvalds #define BLTDSTBASEADDR 0x02c4 /* BitBLT Destination base address */ 1781da177e4SLinus Torvalds #define BLTXYSTRIDES 0x02c8 /* BitBLT Source and Destination strides */ 1791da177e4SLinus Torvalds #define BLTSRCCHROMARANGE 0x02cc /* BitBLT Source Chroma key range */ 1801da177e4SLinus Torvalds #define BLTDSTCHROMARANGE 0x02d0 /* BitBLT Destination Chroma key range */ 1811da177e4SLinus Torvalds #define BLTCLIPX 0x02d4 /* BitBLT Min/Max X clip values */ 1821da177e4SLinus Torvalds #define BLTCLIPY 0x02d8 /* BitBLT Min/Max Y clip values */ 1831da177e4SLinus Torvalds #define BLTSRCXY 0x02e0 /* BitBLT Source starting XY coordinates */ 1841da177e4SLinus Torvalds #define BLTDSTXY 0x02e4 /* BitBLT Destination starting XY coordinates */ 1851da177e4SLinus Torvalds #define BLTSIZE 0x02e8 /* BitBLT width and height */ 1861da177e4SLinus Torvalds #define BLTROP 0x02ec /* BitBLT Raster operations */ 1871da177e4SLinus Torvalds # define BLTROP_COPY 0x0cccc 1881da177e4SLinus Torvalds # define BLTROP_INVERT 0x05555 1891da177e4SLinus Torvalds # define BLTROP_XOR 0x06666 1901da177e4SLinus Torvalds #define BLTCOLOR 0x02f0 /* BitBLT and foreground background colors */ 1911da177e4SLinus Torvalds #define BLTCOMMAND 0x02f8 /* BitBLT command mode (v2 specific) */ 1921da177e4SLinus Torvalds # define BLT_SCR2SCR_BITBLT 0 /* Screen-to-Screen BitBLT */ 1931da177e4SLinus Torvalds # define BLT_CPU2SCR_BITBLT 1 /* CPU-to-screen BitBLT */ 1941da177e4SLinus Torvalds # define BLT_RECFILL_BITBLT 2 /* BitBLT Rectangle Fill */ 1951da177e4SLinus Torvalds # define BLT_16BPP_FMT 2 /* 16 BPP (5-6-5 RGB) */ 1961da177e4SLinus Torvalds #define BLTDATA 0x02fc /* BitBLT data for CPU-to-Screen BitBLTs */ 1971da177e4SLinus Torvalds # define LAUNCH_BITBLT BIT(31) /* Launch BitBLT in BltCommand, bltDstXY or bltSize */ 1981da177e4SLinus Torvalds 1991da177e4SLinus Torvalds /* Dac Registers */ 2001da177e4SLinus Torvalds #define DACREG_WMA 0x0 /* pixel write mode address */ 2011da177e4SLinus Torvalds #define DACREG_LUT 0x01 /* color value */ 2021da177e4SLinus Torvalds #define DACREG_RMR 0x02 /* pixel mask */ 2031da177e4SLinus Torvalds #define DACREG_RMA 0x03 /* pixel read mode address */ 2041da177e4SLinus Torvalds /*Dac registers in indexed mode (TI, ATT dacs) */ 2051da177e4SLinus Torvalds #define DACREG_ADDR_I DACREG_WMA 2061da177e4SLinus Torvalds #define DACREG_DATA_I DACREG_RMR 2071da177e4SLinus Torvalds #define DACREG_RMR_I 0x00 2081da177e4SLinus Torvalds #define DACREG_CR0_I 0x01 2091da177e4SLinus Torvalds # define DACREG_CR0_EN_INDEXED BIT(0) /* enable indexec mode */ 2101da177e4SLinus Torvalds # define DACREG_CR0_8BIT BIT(1) /* set dac to 8 bits/read */ 2111da177e4SLinus Torvalds # define DACREG_CR0_PWDOWN BIT(3) /* powerdown dac */ 2121da177e4SLinus Torvalds # define DACREG_CR0_16BPP 0x30 /* mode 3 */ 2131da177e4SLinus Torvalds # define DACREG_CR0_24BPP 0x50 /* mode 5 */ 2141da177e4SLinus Torvalds #define DACREG_CR1_I 0x05 2151da177e4SLinus Torvalds #define DACREG_CC_I 0x06 21625985edcSLucas De Marchi # define DACREG_CC_CLKA BIT(7) /* clk A controlled by regs */ 2171da177e4SLinus Torvalds # define DACREG_CC_CLKA_C (2<<4) /* clk A uses reg C */ 21825985edcSLucas De Marchi # define DACREG_CC_CLKB BIT(3) /* clk B controlled by regs */ 2191da177e4SLinus Torvalds # define DACREG_CC_CLKB_D 3 /* clkB uses reg D */ 2201da177e4SLinus Torvalds #define DACREG_AC0_I 0x48 /* clock A reg C */ 2211da177e4SLinus Torvalds #define DACREG_AC1_I 0x49 2221da177e4SLinus Torvalds #define DACREG_BD0_I 0x6c /* clock B reg D */ 2231da177e4SLinus Torvalds #define DACREG_BD1_I 0x6d 2241da177e4SLinus Torvalds 2251da177e4SLinus Torvalds /* identification constants */ 2261da177e4SLinus Torvalds #define DACREG_MIR_TI 0x97 2271da177e4SLinus Torvalds #define DACREG_DIR_TI 0x09 2281da177e4SLinus Torvalds #define DACREG_MIR_ATT 0x84 2291da177e4SLinus Torvalds #define DACREG_DIR_ATT 0x09 2301da177e4SLinus Torvalds /* ics dac specific registers */ 2311da177e4SLinus Torvalds #define DACREG_ICS_PLLWMA 0x04 /* PLL write mode address */ 2321da177e4SLinus Torvalds #define DACREG_ICS_PLLDATA 0x05 /* PLL data /parameter */ 2331da177e4SLinus Torvalds #define DACREG_ICS_CMD 0x06 /* command */ 2341da177e4SLinus Torvalds # define DACREG_ICS_CMD_16BPP 0x50 /* ics color mode 6 (16bpp bypass)*/ 2351da177e4SLinus Torvalds # define DACREG_ICS_CMD_24BPP 0x70 /* ics color mode 7 (24bpp bypass)*/ 2361da177e4SLinus Torvalds # define DACREG_ICS_CMD_PWDOWN BIT(0) /* powerdown dac */ 2371da177e4SLinus Torvalds #define DACREG_ICS_PLLRMA 0x07 /* PLL read mode address */ 2381da177e4SLinus Torvalds /* 2391da177e4SLinus Torvalds * pll parameter register: 2401da177e4SLinus Torvalds * indexed : write addr to PLLWMA, write data in PLLDATA. 2411da177e4SLinus Torvalds * for reads use PLLRMA . 2421da177e4SLinus Torvalds * 8 freq registers (0-7) for video clock (CLK0) 2431da177e4SLinus Torvalds * 2 freq registers (a-b) for graphic clock (CLK1) 2441da177e4SLinus Torvalds */ 2451da177e4SLinus Torvalds #define DACREG_ICS_PLL_CLK0_1_INI 0x55 /* initial pll M value for freq f1 */ 2461da177e4SLinus Torvalds #define DACREG_ICS_PLL_CLK0_7_INI 0x71 /* f7 */ 2471da177e4SLinus Torvalds #define DACREG_ICS_PLL_CLK1_B_INI 0x79 /* fb */ 2481da177e4SLinus Torvalds #define DACREG_ICS_PLL_CTRL 0x0e 2491da177e4SLinus Torvalds # define DACREG_ICS_CLK0 BIT(5) 2501da177e4SLinus Torvalds # define DACREG_ICS_CLK0_0 0 2511da177e4SLinus Torvalds # define DACREG_ICS_CLK1_A 0 /* bit4 */ 2521da177e4SLinus Torvalds 2531da177e4SLinus Torvalds /* sst default init registers */ 2540743b868SHelge Deller #define FBIINIT0_DEFAULT DIS_VGA_PASSTHROUGH 2551da177e4SLinus Torvalds 2561da177e4SLinus Torvalds #define FBIINIT1_DEFAULT \ 2571da177e4SLinus Torvalds ( \ 2581da177e4SLinus Torvalds FAST_PCI_WRITES \ 2591da177e4SLinus Torvalds /* SLOW_PCI_WRITES*/ \ 2601da177e4SLinus Torvalds | VIDEO_RESET \ 2611da177e4SLinus Torvalds | 10 << TILES_IN_X_SHIFT\ 2621da177e4SLinus Torvalds | SEL_SOURCE_VCLK_2X_SEL\ 2631da177e4SLinus Torvalds | EN_LFB_READ \ 2641da177e4SLinus Torvalds ) 2651da177e4SLinus Torvalds 2661da177e4SLinus Torvalds #define FBIINIT2_DEFAULT \ 2671da177e4SLinus Torvalds ( \ 2681da177e4SLinus Torvalds SWAP_DACVSYNC \ 2691da177e4SLinus Torvalds | EN_DRAM_OE \ 2701da177e4SLinus Torvalds | DRAM_REFRESH_16 \ 2711da177e4SLinus Torvalds | EN_DRAM_REFRESH \ 2721da177e4SLinus Torvalds | EN_FAST_RAS_READ \ 2731da177e4SLinus Torvalds | EN_RD_AHEAD_FIFO \ 2741da177e4SLinus Torvalds | EN_FAST_RD_AHEAD_WR \ 2751da177e4SLinus Torvalds ) 2761da177e4SLinus Torvalds 2771da177e4SLinus Torvalds #define FBIINIT3_DEFAULT \ 2781da177e4SLinus Torvalds ( DISABLE_TEXTURE ) 2791da177e4SLinus Torvalds 2801da177e4SLinus Torvalds #define FBIINIT4_DEFAULT \ 2811da177e4SLinus Torvalds ( \ 2821da177e4SLinus Torvalds FAST_PCI_READS \ 2831da177e4SLinus Torvalds /* SLOW_PCI_READS*/ \ 2841da177e4SLinus Torvalds | LFB_READ_AHEAD \ 2851da177e4SLinus Torvalds ) 2861da177e4SLinus Torvalds /* Careful with this one : writing back the data just read will trash the DAC 2871da177e4SLinus Torvalds reading some fields give logic value on pins, but setting this field will 2881da177e4SLinus Torvalds set the source signal driving the pin. conclusion : just use the default 2891da177e4SLinus Torvalds as a base before writing back . 2901da177e4SLinus Torvalds */ 2911da177e4SLinus Torvalds #define FBIINIT6_DEFAULT (0x0) 2921da177e4SLinus Torvalds 2931da177e4SLinus Torvalds /* 2941da177e4SLinus Torvalds * 2951da177e4SLinus Torvalds * Misc Const 2961da177e4SLinus Torvalds * 2971da177e4SLinus Torvalds */ 2981da177e4SLinus Torvalds 2990743b868SHelge Deller /* ioctl to enable/disable VGA passthrough */ 3000743b868SHelge Deller #define SSTFB_SET_VGAPASS _IOW('F', 0xdd, __u32) 3010743b868SHelge Deller #define SSTFB_GET_VGAPASS _IOR('F', 0xdd, __u32) 3020743b868SHelge Deller 3030743b868SHelge Deller 3041da177e4SLinus Torvalds /* used to know witch clock to set */ 3051da177e4SLinus Torvalds enum { 3061da177e4SLinus Torvalds VID_CLOCK=0, 3071da177e4SLinus Torvalds GFX_CLOCK=1, 3081da177e4SLinus Torvalds }; 3091da177e4SLinus Torvalds 3101da177e4SLinus Torvalds /* freq max */ 3111da177e4SLinus Torvalds #define DAC_FREF 14318 /* DAC reference freq (Khz) */ 3121da177e4SLinus Torvalds #define VCO_MAX 260000 3131da177e4SLinus Torvalds 3141da177e4SLinus Torvalds /* 3151da177e4SLinus Torvalds * driver structs 3161da177e4SLinus Torvalds */ 3171da177e4SLinus Torvalds 3181da177e4SLinus Torvalds struct pll_timing { 3191da177e4SLinus Torvalds unsigned int m; 3201da177e4SLinus Torvalds unsigned int n; 3211da177e4SLinus Torvalds unsigned int p; 3221da177e4SLinus Torvalds }; 3231da177e4SLinus Torvalds 3241da177e4SLinus Torvalds struct dac_switch { 3250743b868SHelge Deller const char *name; 3261da177e4SLinus Torvalds int (*detect) (struct fb_info *info); 3271da177e4SLinus Torvalds int (*set_pll) (struct fb_info *info, const struct pll_timing *t, const int clock); 3281da177e4SLinus Torvalds void (*set_vidmod) (struct fb_info *info, const int bpp); 3291da177e4SLinus Torvalds }; 3301da177e4SLinus Torvalds 3311da177e4SLinus Torvalds struct sst_spec { 3321da177e4SLinus Torvalds char * name; 3331da177e4SLinus Torvalds int default_gfx_clock; /* 50000 for voodoo1, 75000 for voodoo2 */ 3341da177e4SLinus Torvalds int max_gfxclk; /* ! in Mhz ie 60 for voodoo 1 */ 3351da177e4SLinus Torvalds }; 3361da177e4SLinus Torvalds 3371da177e4SLinus Torvalds struct sstfb_par { 3387227576fSAntonino A. Daplas u32 palette[16]; 3391da177e4SLinus Torvalds unsigned int yDim; 3401da177e4SLinus Torvalds unsigned int hSyncOn; /* hsync_len */ 3411da177e4SLinus Torvalds unsigned int hSyncOff; /* left_margin + xres + right_margin */ 3421da177e4SLinus Torvalds unsigned int hBackPorch;/* left_margin */ 3431da177e4SLinus Torvalds unsigned int vSyncOn; 3441da177e4SLinus Torvalds unsigned int vSyncOff; 3451da177e4SLinus Torvalds unsigned int vBackPorch; 3461da177e4SLinus Torvalds struct pll_timing pll; 3471da177e4SLinus Torvalds unsigned int tiles_in_X;/* num of tiles in X res */ 3481da177e4SLinus Torvalds u8 __iomem *mmio_vbase; 3491da177e4SLinus Torvalds struct dac_switch dac_sw; /* dac specific functions */ 3501da177e4SLinus Torvalds struct pci_dev *dev; 3511da177e4SLinus Torvalds int type; 3521da177e4SLinus Torvalds u8 revision; 3530743b868SHelge Deller u8 vgapass; /* VGA pass through: 1=enabled, 0=disabled */ 3541da177e4SLinus Torvalds }; 3551da177e4SLinus Torvalds 3561da177e4SLinus Torvalds #endif /* _SSTFB_H_ */ 357