Lines Matching +full:big +full:- +full:endian +full:- +full:regs
1 // SPDX-License-Identifier: GPL-2.0-only
37 void __iomem *regs; member
48 * This hardware has a big endian bit assignment such that GPIO line 0 is
54 return BIT(31 - offset); in mpc_pin2mask()
68 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); in mpc8572_gpio_get()
69 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; in mpc8572_gpio_get()
70 out_shadow = gc->bgpio_data & out_mask; in mpc8572_gpio_get()
81 return -EINVAL; in mpc5121_gpio_dir_out()
83 return mpc8xxx_gc->direction_output(gc, gpio, val); in mpc5121_gpio_dir_out()
92 return -EINVAL; in mpc5125_gpio_dir_out()
94 return mpc8xxx_gc->direction_output(gc, gpio, val); in mpc5125_gpio_dir_out()
101 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) in mpc8xxx_gpio_to_irq()
102 return irq_create_mapping(mpc8xxx_gc->irq, offset); in mpc8xxx_gpio_to_irq()
104 return -ENXIO; in mpc8xxx_gpio_to_irq()
110 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_gpio_irq_cascade()
114 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) in mpc8xxx_gpio_irq_cascade()
115 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); in mpc8xxx_gpio_irq_cascade()
117 generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i); in mpc8xxx_gpio_irq_cascade()
125 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_unmask()
128 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_unmask()
130 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, in mpc8xxx_irq_unmask()
131 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) in mpc8xxx_irq_unmask()
134 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_unmask()
140 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_mask()
143 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_mask()
145 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, in mpc8xxx_irq_mask()
146 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) in mpc8xxx_irq_mask()
149 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_mask()
155 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_ack()
157 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, in mpc8xxx_irq_ack()
164 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_set_type()
170 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
171 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, in mpc8xxx_irq_set_type()
172 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) in mpc8xxx_irq_set_type()
174 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
178 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
179 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, in mpc8xxx_irq_set_type()
180 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) in mpc8xxx_irq_set_type()
182 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
186 return -EINVAL; in mpc8xxx_irq_set_type()
195 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc512x_irq_set_type()
202 reg = mpc8xxx_gc->regs + GPIO_ICR; in mpc512x_irq_set_type()
203 shift = (15 - gpio) * 2; in mpc512x_irq_set_type()
205 reg = mpc8xxx_gc->regs + GPIO_ICR2; in mpc512x_irq_set_type()
206 shift = (15 - (gpio % 16)) * 2; in mpc512x_irq_set_type()
212 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
213 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) in mpc512x_irq_set_type()
215 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
220 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
221 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) in mpc512x_irq_set_type()
223 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
227 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
228 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))); in mpc512x_irq_set_type()
229 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
233 return -EINVAL; in mpc512x_irq_set_type()
240 .name = "mpc8xxx-gpio",
251 irq_set_chip_data(irq, h->host_data); in mpc8xxx_gpio_irq_map()
287 { .compatible = "fsl,mpc8349-gpio", },
288 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
289 { .compatible = "fsl,mpc8610-gpio", },
290 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
291 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
292 { .compatible = "fsl,pq3-gpio", },
293 { .compatible = "fsl,ls1028a-gpio", },
294 { .compatible = "fsl,ls1088a-gpio", },
295 { .compatible = "fsl,qoriq-gpio", },
301 struct device_node *np = pdev->dev.of_node; in mpc8xxx_probe()
308 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL); in mpc8xxx_probe()
310 return -ENOMEM; in mpc8xxx_probe()
314 raw_spin_lock_init(&mpc8xxx_gc->lock); in mpc8xxx_probe()
316 mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0); in mpc8xxx_probe()
317 if (IS_ERR(mpc8xxx_gc->regs)) in mpc8xxx_probe()
318 return PTR_ERR(mpc8xxx_gc->regs); in mpc8xxx_probe()
320 gc = &mpc8xxx_gc->gc; in mpc8xxx_probe()
321 gc->parent = &pdev->dev; in mpc8xxx_probe()
323 if (device_property_read_bool(&pdev->dev, "little-endian")) { in mpc8xxx_probe()
324 ret = bgpio_init(gc, &pdev->dev, 4, in mpc8xxx_probe()
325 mpc8xxx_gc->regs + GPIO_DAT, in mpc8xxx_probe()
327 mpc8xxx_gc->regs + GPIO_DIR, NULL, in mpc8xxx_probe()
331 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n"); in mpc8xxx_probe()
333 ret = bgpio_init(gc, &pdev->dev, 4, in mpc8xxx_probe()
334 mpc8xxx_gc->regs + GPIO_DAT, in mpc8xxx_probe()
336 mpc8xxx_gc->regs + GPIO_DIR, NULL, in mpc8xxx_probe()
341 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n"); in mpc8xxx_probe()
344 mpc8xxx_gc->direction_output = gc->direction_output; in mpc8xxx_probe()
346 devtype = device_get_match_data(&pdev->dev); in mpc8xxx_probe()
354 if (devtype->irq_set_type) in mpc8xxx_probe()
355 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type; in mpc8xxx_probe()
357 if (devtype->gpio_dir_out) in mpc8xxx_probe()
358 gc->direction_output = devtype->gpio_dir_out; in mpc8xxx_probe()
359 if (devtype->gpio_get) in mpc8xxx_probe()
360 gc->get = devtype->gpio_get; in mpc8xxx_probe()
362 gc->to_irq = mpc8xxx_gpio_to_irq; in mpc8xxx_probe()
371 fwnode = dev_fwnode(&pdev->dev); in mpc8xxx_probe()
372 if (of_device_is_compatible(np, "fsl,qoriq-gpio") || in mpc8xxx_probe()
373 of_device_is_compatible(np, "fsl,ls1028a-gpio") || in mpc8xxx_probe()
374 of_device_is_compatible(np, "fsl,ls1088a-gpio") || in mpc8xxx_probe()
376 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); in mpc8xxx_probe()
378 gc->bgpio_data = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & in mpc8xxx_probe()
379 gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); in mpc8xxx_probe()
382 ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc); in mpc8xxx_probe()
384 dev_err(&pdev->dev, in mpc8xxx_probe()
389 mpc8xxx_gc->irqn = platform_get_irq(pdev, 0); in mpc8xxx_probe()
390 if (mpc8xxx_gc->irqn < 0) in mpc8xxx_probe()
391 return mpc8xxx_gc->irqn; in mpc8xxx_probe()
393 mpc8xxx_gc->irq = irq_domain_create_linear(fwnode, in mpc8xxx_probe()
398 if (!mpc8xxx_gc->irq) in mpc8xxx_probe()
402 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); in mpc8xxx_probe()
403 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0); in mpc8xxx_probe()
405 ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn, in mpc8xxx_probe()
407 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade", in mpc8xxx_probe()
410 dev_err(&pdev->dev, in mpc8xxx_probe()
412 mpc8xxx_gc->irqn, ret); in mpc8xxx_probe()
418 irq_domain_remove(mpc8xxx_gc->irq); in mpc8xxx_probe()
426 if (mpc8xxx_gc->irq) { in mpc8xxx_remove()
427 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL); in mpc8xxx_remove()
428 irq_domain_remove(mpc8xxx_gc->irq); in mpc8xxx_remove()
446 .name = "gpio-mpc8xxx",