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12

/openbmc/u-boot/drivers/rtc/
H A DKconfig11 Enable drver model for real-time-clock drivers. The RTC uclass
20 Enable drver model for real-time-clock drivers. The RTC uclass
29 Enable drver model for real-time-clock drivers. The RTC uclass
41 has a selectable I2C-bus or SPI-bus, a backup battery switch-over circuit, a
56 calendar with automatic leap year correction, 2-byte battery backed SRAM,
57 automatic power switch-over, alarm function and 15 selectable frequency
67 The MicroCrystal RV3029 is a I2C Real Time Clock (RTC) with 8-byte
68 battery-backed SRAM.
71 battery-baced SRAM section.
102 This is a widely used real-time clock chip originally by Motorola
[all …]
H A Dds3231.c1 // SPDX-License-Identifier: GPL-2.0+
49 #define RTC_STAT_BIT_BB32KHZ 0x40 /* Battery backed 32KHz Output */
84 rel = -1; in rtc_get()
87 tmp->tm_sec = bcd2bin (sec & 0x7F); in rtc_get()
88 tmp->tm_min = bcd2bin (min & 0x7F); in rtc_get()
89 tmp->tm_hour = bcd2bin (hour & 0x3F); in rtc_get()
90 tmp->tm_mday = bcd2bin (mday & 0x3F); in rtc_get()
91 tmp->tm_mon = bcd2bin (mon_cent & 0x1F); in rtc_get()
92 tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900); in rtc_get()
93 tmp->tm_wday = bcd2bin ((wday - 1) & 0x07); in rtc_get()
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H A Dds1374.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Steven Scholz, steven.scholz@imc-berlin.de
21 /*---------------------------------------------------------------------*/
30 /*---------------------------------------------------------------------*/
52 #define RTC_CTL_ADDR 0x07 /* RTC-CoNTrol-register */
53 #define RTC_SR_ADDR 0x08 /* RTC-StatusRegister */
54 #define RTC_TCS_DS_ADDR 0x09 /* RTC-TrickleChargeSelect DiodeSelect-register */
56 #define RTC_CTL_BIT_AIE (1<<0) /* Bit 0 - Alarm Interrupt enable */
57 #define RTC_CTL_BIT_RS1 (1<<1) /* Bit 1/2 - Rate Select square wave output */
58 #define RTC_CTL_BIT_RS2 (1<<2) /* Bit 2/2 - Rate Select square wave output */
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/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Dtrivial-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/rtc/trivial-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
18 - $ref: rtc.yaml#
23 # AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface
24 - abracon,abb5zes3
25 # AB-RTCMC-32.768kHz-EOZ9: Real Time Clock/Calendar Module with I2C Interface
26 - abracon,abeoz9
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/openbmc/linux/Documentation/admin-guide/
H A Drtc.rst6 something that tracks wall clock time and is battery backed so that it
8 the local time zone or daylight savings time -- unless they dual boot
9 with MS-Windows -- but will instead be set to Coordinated Universal Time
12 The newest non-PC hardware tends to just count seconds, like the time(2)
16 Linux has two largely-compatible userspace RTC API families you may
20 so it's not very portable to non-x86 systems.
35 Old PC/AT-Compatible driver: /dev/rtc
36 --------------------------------------
44 a few ways (enabling longer alarm periods, and wake-from-hibernate).
59 the type of interrupt (update-done, alarm-rang, or periodic) that was
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/openbmc/linux/drivers/mtd/devices/
H A Dms02-nv.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * DEC MS02-NV (54-20948-01) battery backed-up NVRAM module for
16 * 0x000000 - 0x3fffff SRAM
17 * 0x400000 - 0x7fffff CSR
22 * 0x000000 - 0x0003ff diagnostic area, destroyed upon a reboot
23 * 0x000400 - ENDofRAM storage area, available to operating systems
29 * containing no valid data, and disables the battery resulting in
31 * for the start address of the user-available is 0x001000 which is
36 * operating system, a magic ID to distinguish a MS02-NV board from
42 * The firmware only handles the MS02-NV board if installed in the
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "Self-contained MTD device drivers"
12 These devices come in memory configurations from 32M - 1G. If you
41 tristate "DEC MS02-NV NVRAM module support"
44 This is an MTD driver for the DEC's MS02-NV (54-20948-01) battery
45 backed-up NVRAM module. The module was originally meant as an NFS
52 The module will be called ms02-nv.
59 Sometimes DataFlash chips are packaged inside MMC-format
77 one-time-programmable (OTP) data. The first half may be written
80 unique-to-each-chip bit pattern at the factory.
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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dstericsson,ab8500.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson Analog Baseband AB8500 and AB8505
10 - Linus Walleij <linus.walleij@linaro.org>
13 the AB8500 "Analog Baseband" is the mixed-signals integrated circuit
14 handling power management (regulators), analog-to-digital conversion
15 (ADC), battery charging, fuel gauging of the battery, battery-backed
16 RTC, PWM, USB PHY and some GPIO lines in the ST-Ericsson U8500 platforms
21 USB charging handling has changed, and it has an embedded USB-to-serial
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H A Datmel-gpbr.txt3 The GPBR are a set of battery-backed registers.
6 - compatible: Should be one of the following:
7 "atmel,at91sam9260-gpbr", "syscon"
8 "microchip,sam9x60-gpbr", "syscon"
9 "microchip,sam9x7-gpbr", "microchip,sam9x60-gpbr", "syscon"
10 - reg: contains offset/length value of the GPBR memory
16 compatible = "atmel,at91sam9260-gpbr", "syscon";
H A Dnxp,bbnsm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP Battery-Backed Non-Secure Module
10 - Jacky Bai <ping.bai@nxp.com>
13 NXP BBNSM serves as non-volatile logic and storage for the system.
17 significant 32 bits of the real-time counter match the value in the
26 - enum:
27 - nxp,imx93-bbnsm
28 - const: syscon
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/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/
H A DBattery.v1_3_0.json2 "$id": "http://redfish.dmtf.org/schemas/v1/Battery.v1_3_0.json",
3 "$ref": "#/definitions/Battery",
4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
26 "#Battery.Calibrate": {
29 "#Battery.Reset": {
32 "#Battery.SelfTest": {
37 "description": "The available OEM-specific actions for this resource.",
38 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
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H A DPowerDistribution.v1_4_0.json4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2024 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
31 "description": "The available OEM-specific actions for this resource.",
32 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
40 …"longDescription": "This Redfish Specification-described type shall contain links to resources tha…
42 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
66 "$ref": "http://redfish.dmtf.org/schemas/v1/odata-v4.json#/definitions/count"
84 "$ref": "http://redfish.dmtf.org/schemas/v1/odata-v4.json#/definitions/count"
89 …operties contained in this object shall conform to the Redfish Specification-described requirement…
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/openbmc/u-boot/arch/x86/include/asm/
H A Dcmos_layout.h1 /* SPDX-License-Identifier: GPL-2.0+ */
13 * registers, A - D, that are used for configuration of the RTC. The extended
14 * bank contains a full 128 bytes of battery backed SRAM.
16 * For simplicity in U-Boot we only support CMOS in the standard bank, and
23 * U-Boot for various reasons. It is put in such a unified place in order
/openbmc/bmcweb/redfish-core/schema/dmtf/csdl/
H A DBattery_v1.xml1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!--# Redfish Schema: Battery v1.3.0 -->
5 <!--# -->
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, -->
7 <!--# available at http://www.dmtf.org/standards/redfish -->
8 <!--# Copyright 2014-2024 DMTF. -->
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright -->
10 <!--################################################################################ -->
[all …]
/openbmc/qemu/include/hw/nvram/
H A Dxlnx-bbram.h2 * QEMU model of the Xilinx BBRAM Battery Backed RAM
4 * Copyright (c) 2015-2021 Xilinx Inc.
29 #include "sysemu/block-backend.h"
30 #include "hw/qdev-core.h"
37 #define TYPE_XLNX_BBRAM "xlnx.bbram-ctrl"
/openbmc/linux/drivers/rtc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
44 This clock should be battery-backed, so that it reads the correct
45 time when the system boots from a power-off state. Otherwise, your
48 If the clock you specify here is not battery backed, it may still
92 Say yes here to add support for the non volatile (often battery
93 backed) storage present on RTCs.
141 once-per-second update interrupts, used for synchronization.
159 will be called rtc-test.
173 will be called rtc-88pm860x.
183 will be called rtc-88pm80x.
[all …]
H A Drtc-ds1307.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
23 #include <linux/hwmon-sysfs.h>
24 #include <linux/clk-provider.h>
29 * We can't determine type by probing, but if we expect pre-Linux code
31 * setting the date and time), Linux can ignore the non-clock features.
56 #define DS1307_REG_SECS 0x00 /* 00-59 */
60 #define DS1307_REG_MIN 0x01 /* 00-59 */
62 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
67 #define DS1307_REG_WDAY 0x03 /* 01-07 */
[all …]
/openbmc/linux/include/linux/rtc/
H A Dds1685.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * DS1685/DS1687-series RTC chips.
8 * include larger, battery-backed NV-SRAM, burst-mode access, and an RTC
11 * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
12 * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
15 * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
16 * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
17 * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
29 * struct ds1685_priv - DS1685 private data structure.
38 * @prepare_poweroff: pointer to platform pre-poweroff function.
[all …]
/openbmc/u-boot/board/compulab/cm_t43/
H A Dcm_t43.c1 // SPDX-License-Identifier: GPL-2.0+
37 printf("WARNING: RTC not backed by battery!\n"); in power_init_board()
45 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
120 if (phydev->drv->config) in board_phy_config()
121 return phydev->drv->config(phydev); in board_phy_config()
155 writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); in board_eth_init()
/openbmc/u-boot/doc/device-tree-bindings/
H A Dchosen.txt2 ---------------
7 stdout-path property
8 --------------------
10 with a stdout-path property under /chosen.
13 -------
16 stdout-path = "/serial@f00:115200";
20 compatible = "vendor,some-uart";
25 tick-timer property
26 -------------------
28 as the tick-timer. Earlier it was hardcoded in the timer driver now
[all …]
/openbmc/linux/drivers/input/serio/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
113 This driver provides support for the PS/2 ports on PA-RISC machines
131 of delivering interrupts on a periodic and one-shot basis.
132 The SDC may also be connected to a battery-backed real-time
133 clock, a basic audio waveform generator, and an HP-HIL Master
199 echo -n "serio_raw" > /sys/bus/serio/devices/serioX/drvctl
231 When used for the E3 mailboard, a non-standard key table
268 tristate "OLPC AP-SP input support"
272 in the OLPC XO-1.75 and XO-4 laptops.
282 Select this option to enable the Hyper-V Keyboard driver.
[all …]
/openbmc/qemu/docs/system/arm/
H A Dxlnx-versal-virt.rst1 Xilinx Versal Virt (``xlnx-versal-virt``)
4 Xilinx Versal is a family of heterogeneous multi-core SoCs
10 https://www.xilinx.com/products/silicon-devices/acap/versal.html
22 - 2 ACPUs (ARM Cortex-A72)
26 - Interrupt controller (ARM GICv3)
27 - 2 UARTs (ARM PL011)
28 - An RTC (Versal built-in)
29 - 2 GEMs (Cadence MACB Ethernet MACs)
30 - 8 ADMA (Xilinx zDMA) channels
31 - 2 SD Controllers
[all …]
/openbmc/qemu/hw/nvram/
H A Dxlnx-bbram.c2 * QEMU model of the Xilinx BBRAM Battery Backed RAM
4 * Copyright (c) 2014-2021 Xilinx Inc.
27 #include "hw/nvram/xlnx-bbram.h"
29 #include "qemu/error-report.h"
34 #include "hw/qdev-properties.h"
35 #include "hw/qdev-properties-system.h"
36 #include "hw/nvram/xlnx-efuse.h"
75 #define RAM_MAX (A_BBRAM_8 + 4 - A_BBRAM_0)
79 QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxBBRam *)0)->regs));
83 return ARRAY_FIELD_EX32(s->regs, BBRAM_MSW_LOCK, VAL) != 0; in bbram_msw_locked()
[all …]
/openbmc/linux/arch/mips/include/asm/sgi/
H A Dhpc3.h40 u32 _unused0[0x1000/4 - 2]; /* padding */
54 #define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
58 u32 _unused1[0x1000/4 - 1]; /* padding */
65 u32 _unused0[0x1000/4 - 2]; /* padding */
89 #define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
100 #define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
105 u32 _unused1[0x1000/4 - 6]; /* padding */
113 u32 _unused0[0x1000/4 - 2]; /* padding */
152 u32 _unused2[0x1000/4 - 8]; /* padding */
157 u32 _unused3[0x1000/4 - 2]; /* padding */
[all …]
/openbmc/u-boot/common/spl/
H A DKconfig25 supports MMC, NAND and YMODEM and other methods loading of U-Boot
29 bool "Pass hand-off information from SPL to U-Boot proper"
32 It is useful to be able to pass information from SPL to U-Boot
33 proper to preserve state that is known in SPL and is needed in U-Boot.
34 Enable this to locate the handoff information in U-Boot proper, early
35 in boot. It is available in gd->handoff. The state state is set up
44 This option can minilize the SPL size to compatible with AST2600-A0
48 bool "Pass hand-off information from SPL to U-Boot proper"
53 used to pass information like the size of SDRAM from SPL to U-Boot
59 default "arch/$(ARCH)/cpu/u-boot-spl.lds"
[all …]

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