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/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-mvebu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell EBU GPIO controller
10 - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 - Andrew Lunn <andrew@lunn.ch>
16 - enum:
17 - marvell,armada-8k-gpio
18 - marvell,orion-gpio
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dap80x-system-controller.txt1 Marvell Armada AP80x System Controller
4 The AP806/AP807 is one of the two core HW blocks of the Marvell Armada
5 7K/8K/931x SoCs. It contains system controllers, which provide several
6 registers giving access to numerous features: clocks, pin-muxing and
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
18 -------
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
[all …]
H A Dcp110-system-controller.txt1 Marvell Armada CP110 System Controller
4 The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
6 giving access to numerous features: clocks, pin-muxing and many other
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the CP110 system controller
18 -------
23 - a set of core clocks
24 - a set of gateable clocks
28 - The first cell must be 0 or 1. 0 for the core clocks and 1 for the
30 - The second cell identifies the particular core clock or gateable
[all …]
/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Dmarvell,mvebu-pinctrl.txt1 The pinctrl driver enables Marvell Armada 8K SoCs to configure the multi-purpose
8 - compatible: "marvell,mvebu-pinctrl",
9 "marvell,ap806-pinctrl",
10 "marvell,armada-7k-pinctrl",
11 "marvell,armada-8k-cpm-pinctrl",
12 "marvell,armada-8k-cps-pinctrl"
13 - bank-name: A string defining the pinc controller bank name
14 - reg: A pair of values defining the pin controller base address
16 - pin-count: Numeric value defining the amount of multi purpose pins
18 - max-func: Numeric value defining the maximum function value for
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-cp110-slave.dtsi4 * This file is dual-licensed: you can use it either under the terms
44 * Device Tree file for Marvell Armada CP110 Slave.
47 #include <dt-bindings/comphy/comphy_data.h>
50 cp110-slave {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
57 config-space {
58 #address-cells = <1>;
[all …]
H A Darmada-cp110-master.dtsi4 * This file is dual-licensed: you can use it either under the terms
44 * Device Tree file for Marvell Armada CP110 Master.
47 #include <dt-bindings/comphy/comphy_data.h>
50 cp110-master {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
57 config-space {
58 #address-cells = <1>;
[all …]
H A Darmada-ap806.dtsi4 * This file is dual-licensed: you can use it either under the terms
44 * Device Tree file for Marvell Armada AP806.
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 /dts-v1/;
52 model = "Marvell Armada AP806";
53 compatible = "marvell,armada-ap806";
54 #address-cells = <2>;
55 #size-cells = <2>;
63 compatible = "arm,psci-0.2";
67 reserved-memory {
[all …]
H A Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: GPL-2.0
6 #include "armada-8040.dtsi"
9 model = "ClearFog-GT-8K";
10 compatible = "solidrun,clearfog-gt-8k",
14 stdout-path = "serial0:115200n8";
28 simple-bus {
29 compatible = "simple-bus";
31 reg_usb3h0_vbus: usb3-vbus0 {
32 compatible = "regulator-fixed";
33 pinctrl-names = "default";
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device Tree file for Marvell Armada CP11x.
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
[all …]
H A Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device Tree file for Marvell Armada AP80x.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
[all …]
H A Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * Device Tree file for SolidRun's ClearFog GT 8K
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
15 model = "SolidRun ClearFog GT 8K";
16 compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
35 compatible = "pwm-fan";
[all …]
/openbmc/u-boot/doc/device-tree-bindings/pci/
H A Darmada8k-pcie.txt1 Armada-8K PCIe DT details:
4 Armada-8k uses synopsis designware PCIe controller.
7 - compatible : should be "marvell,armada8k-pcie", "snps,dw-pcie".
8 - reg: base addresses and lengths of the pcie control and global control registers.
10 points to the pcie configuration registers as mentioned in dw-pcie dt bindings in the link below.
11 - interrupt-map-mask and interrupt-map, standard PCI properties to
13 - All other definitions as per generic PCI bindings
15 "Documentation/devicetree/bindings/pci/designware-pcie.txt"
18 PHY support is still not supported for armada-8k, once it will, the following parameters can be use…
19 - phys : phandle to phy node associated with pcie controller.
[all …]
/openbmc/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-cp110.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell Armada CP110 pinctrl driver based on mvebu pinctrl core
19 #include "pinctrl-mvebu.h"
24 * - In Armada7K (single CP) almost all the MPPs are available (except the
26 * - In Armada8K (dual CP) the MPPs are split into 2 parts, MPPs 0-31 from
27 * CPS, and MPPs 32-62 from CPM, the below flags (V_ARMADA_8K_CPM,
42 MPP_FUNCTION(0, "gpio", NULL),
49 MPP_FUNCTION(8, "uart0", "rxd"),
53 MPP_FUNCTION(0, "gpio", NULL),
60 MPP_FUNCTION(8, "uart0", "txd"),
[all …]
/openbmc/linux/Documentation/arch/arm/
H A Dmarvell.rst13 ------------
16 - 88F5082
17 - 88F5181 a.k.a Orion-1
18 - 88F5181L a.k.a Orion-VoIP
19 - 88F5182 a.k.a Orion-NAS
21 …- Datasheet: https://web.archive.org/web/20210124231420/http://csclub.uwaterloo.ca/~board/ts7800/M…
22 …- Programmer's User Guide: https://web.archive.org/web/20210124231536/http://csclub.uwaterloo.ca/~…
23 …- User Manual: https://web.archive.org/web/20210124231631/http://csclub.uwaterloo.ca/~board/ts7800…
24 …- Functional Errata: https://web.archive.org/web/20210704165540/https://www.digriz.org.uk/ts78xx/8…
25 - 88F5281 a.k.a Orion-2
[all …]
/openbmc/u-boot/drivers/usb/host/
H A Dxhci-mvebu.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <asm/gpio.h>
48 ctx->hcd = (struct xhci_hccr *)plat->hcd_base; in xhci_usb_probe()
49 len = HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)); in xhci_usb_probe()
50 hcor = (struct xhci_hcor *)((uintptr_t)ctx->hcd + len); in xhci_usb_probe()
52 ret = device_get_supply_regulator(dev, "vbus-supply", &regulator); in xhci_usb_probe()
64 return xhci_register(dev, ctx->hcd, hcor); in xhci_usb_probe()
74 plat->hcd_base = devfdt_get_addr(dev); in xhci_usb_ofdata_to_platdata()
75 if (plat->hcd_base == FDT_ADDR_T_NONE) { in xhci_usb_ofdata_to_platdata()
77 return -ENXIO; in xhci_usb_ofdata_to_platdata()
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-mvebu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for Marvell SoCs
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * This driver is a fairly straightforward GPIO driver for the
13 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
16 * platforms (MV78200 from the Discovery family and the Armada
17 * XP). Therefore, this driver handles three variants of the GPIO
19 * - the basic variant, called "orion-gpio", with the simplest
20 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
[all …]
/openbmc/u-boot/
H A DMAINTAINERS8 W: Web-page with status/info
24 N: [^a-z]tegra all files whose path contains the word tegra
37 K: Keyword perl extended regex pattern to match content in a
39 K: of_get_profile
41 K: \b(printk|pr_(info|err))\b
44 One regex pattern per line. Multiple K: lines acceptable.
52 -----------------------------------
57 L: uboot-snps-arc@synopsys.com
58 T: git git://git.denx.de/u-boot-arc.git
65 L: uboot-snps-arc@synopsys.com
[all …]
/openbmc/u-boot/drivers/video/
H A DKconfig13 to display a command-line console or splash screen. Enabling this
24 This driver can be use with "simple-panel" and
26 (leds/backlight/pwm-backlight.txt)
29 bool "Generic GPIO based Backlight Driver"
32 If you have a LCD backlight adjustable by GPIO, say Y to enable
34 This driver can be used with "simple-panel" and
36 (leds/backlight/gpio-backlight.txt)
39 bool "Support 8-bit-per-pixel displays"
43 Support drawing text and bitmaps onto a 8-bit-per-pixel display.
49 bool "Support 16-bit-per-pixel displays"
[all …]
H A Dmvebu_lcd.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Video driver for Marvell Armada XP SoC
113 for (i = 0; i < dram->num_cs; i++) { in mvebu_lcd_conf_mbus_registers()
114 const struct mbus_dram_window *cs = dram->cs + i; in mvebu_lcd_conf_mbus_registers()
115 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | in mvebu_lcd_conf_mbus_registers()
116 (dram->mbus_dram_target_id << 4) | 1, in mvebu_lcd_conf_mbus_registers()
119 writel(cs->base & 0xffff0000, regs + MVEBU_LCD_WIN_BASE(i)); in mvebu_lcd_conf_mbus_registers()
128 int x = lcd_info->x_res; in mvebu_lcd_register_init()
129 int y = lcd_info->y_res; in mvebu_lcd_register_init()
144 * end (currently 1GB-64MB but also may be 2GB-64MB). in mvebu_lcd_register_init()
[all …]
/openbmc/u-boot/doc/
H A DREADME.armada-secureboot1 The trusted boot framework on Marvell Armada 38x
13 8. Bibliography
16 -------------------------------
18 The Armada's trusted boot framework enables the SoC to cryptographically verify
22 To achieve this, the Armada SoC requires a specially prepared boot image, which
25 one-time-writeable memory) need to be configured in the correct way.
30 key from it, and verify its SHA-256 hash against a SHA-256 stored in a eFuse
43 * The SHA-256 value in the eFuse field verifies the "root" public key.
47 In the special case of building a boot image containing U-Boot as the binary
52 2. Creation of a conforming boot image containing the U-Boot image as binary
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 <http://www.linux-mtd.infradead.org/doc/nand.html>.
126 include NAND flash controllers with built-in hardware ECC
161 - PXA3xx processors (NFCv1)
162 - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2)
163 - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2)
229 Controller Module with built-in hardware ECC capabilities.
240 with built-in hardware ECC capabilities.
250 processor localbus with User-Programmable Machine support.
259 The driver supports a maximum 2k page size. With 2k pages and
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
11 model = "Marvell Armada 88AP510 SoC";
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
[all …]
/openbmc/u-boot/drivers/mmc/
H A DKconfig31 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
32 and non-removable (e.g. eMMC chip) devices are supported. These
33 appear as block devices in U-Boot and can support filesystems such
42 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
43 and non-removable (e.g. eMMC chip) devices are supported. These
44 appear as block devices in U-Boot and can support filesystems such
161 you are reading this help text, you most likely have no idea :-)
213 as removeable SD and micro-SD cards.
256 This selects PCI-based MMC controllers.
285 This enables extended-drain in the MMC/SD/SDIO1I/O and
[all …]
/openbmc/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
54 K: *Content regex* (perl extended) pattern match in a patch or file.
56 K: of_get_profile
58 K: \b(printk|pr_(info|err))\b
61 One regex pattern per line. Multiple K: lines acceptable.
[all …]
/openbmc/u-boot/drivers/net/
H A Dmvpp2.c2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
8 * U-Boot version:
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
18 #include <dm/device-internal.h>
33 #include <asm-generic/gpio.h>
98 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
99 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
101 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
102 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
135 #define MVPP22_DESC_ADDR_OFFS 8
[all …]

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