| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/ |
| H A D | mmu.json | 3 "PublicDescription": "Duration of a translation table walk handled by the MMU",
6 "BriefDescription": "Duration of a translation table walk handled by the MMU"
9 …": "Duration of a Stage 1 translation table walk handled by the MMU. This event is not counted whe…
12 …": "Duration of a Stage 1 translation table walk handled by the MMU. This event is not counted whe…
15 …": "Duration of a Stage 2 translation table walk handled by the MMU. This event is not counted whe…
18 …": "Duration of a Stage 2 translation table walk handled by the MMU. This event is not counted whe…
21 "PublicDescription": "Duration of a translation table walk requested by the LSU",
24 "BriefDescription": "Duration of a translation table walk requested by the LSU"
27 … "PublicDescription": "Duration of a translation table walk requested by the instruction side",
30 "BriefDescription": "Duration of a translation table walk requested by the instruction side"
[all …]
|
| /openbmc/qemu/include/hw/arm/ |
| H A D | smmu-common.h | 4 * Copyright (C) 2015-2016 Broadcom Corporation
30 /* VMSAv8-64 Translation constants and functions */
34 #define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1)
35 #define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \
36 (VMSA_LEVELS - (lvl)))
38 VMSA_BIT_LVL(isz, strd, lvl)) - 1)
40 #define CACHED_ENTRY_TO_ADDR(ent, addr) ((ent)->entry.translated_addr + \
41 ((addr) & (ent)->entry.addr_mask))
48 SMMU_PTW_ERR_WALK_EABT, /* Translation walk external abort */
49 SMMU_PTW_ERR_TRANSLATION, /* Translation fault */
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | virtual-memory.json | 20 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
28 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
36 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
44 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
52 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
74 …e number of page walks completed due to stores whose address translations missed in all Translatio…
82 …e number of page walks completed due to stores whose address translations missed in all Translatio…
90 …e number of page walks completed due to stores whose address translations missed in all Translatio…
98 …e number of page walks completed due to stores whose address translations missed in all Translatio…
106 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| H A D | virtual-memory.json | 20 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
28 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
36 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
44 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
52 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
74 …e number of page walks completed due to stores whose address translations missed in all Translatio…
82 …e number of page walks completed due to stores whose address translations missed in all Translatio…
90 …e number of page walks completed due to stores whose address translations missed in all Translatio…
98 …e number of page walks completed due to stores whose address translations missed in all Translatio…
106 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
[all …]
|
| /openbmc/u-boot/include/dm/ |
| H A D | fdtaddr.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
18 * devfdt_get_addr() - Get the reg property of a device
27 * devfdt_get_addr_ptr() - Return pointer to the address of the reg property
37 * devfdt_remap_addr() - Return pointer to the memory-mapped I/O address
47 * devfdt_remap_addr_index() - Return indexed pointer to the memory-mapped
48 * I/O address of the reg property of a device
59 * devfdt_remap_addr_name() - Get the reg property of a device, indexed by
60 * name, as a memory-mapped I/O pointer
62 * 'reg-names' property providing named-based identification. @index
63 * indicates the value to search for in 'reg-names'.
[all …]
|
| /openbmc/qemu/docs/devel/ |
| H A D | tcg.rst | 13 QEMU's dynamic translation backend is called TCG, for "Tiny Code
14 Generator". For more information, please take a look at :ref:`tcg-ops-ref`.
20 -----------------------
24 translation phase considers that some state information of the virtual
25 CPU cannot change in it. The state is recorded in the Translation
34 ---------------------
48 callback to be re-evaluated before executing additional instructions.
63 code address is returned, otherwise the address of the JIT epilogue is
65 opcode, which branches to the returned address. In this way, we either
71 The translation code usually implements branching by performing the
[all …]
|
| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | fsl_pci.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2007,2009-2012 Freescale Semiconductor, Inc.
17 /* Freescale-specific PCI config registers */
37 * PCI Translation Registers
40 u32 potar; /* 0x00 - Address */
41 u32 potear; /* 0x04 - Address Extended */
42 u32 powbar; /* 0x08 - Window Base Address */
44 u32 powar; /* 0x10 - Window Attributes */
54 u32 pitar; /* 0x00 - Address */
56 u32 piwbar; /* 0x08 - Window Base Address */
[all …]
|
| H A D | immap_86xx.h | 19 /* Local-Access Registers and MCM Registers(0x0000-0x2000) */
21 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
23 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
25 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
27 uint bptr; /* 0x20 - Boot Page Translation Register */
29 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
31 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
33 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
35 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
37 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
[all …]
|
| /openbmc/linux/drivers/of/ |
| H A D | fdt_address.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * FDT Address translation based on u-boot fdt_support.c which in turn was
4 * based on the kernel unflattened DT address translation code.
9 * Copyright 2010-2011 Freescale Semiconductor, Inc.
20 /* Max address size we deal with */
30 while(na--) in of_dump_addr()
54 prop = fdt_getprop(blob, parentoffset, "#address-cells", NULL); in fdt_bus_default_count_cells()
62 prop = fdt_getprop(blob, parentoffset, "#size-cells", NULL); in fdt_bus_default_count_cells()
84 return da - cp; in fdt_bus_default_map()
93 addr[na - 2] = cpu_to_fdt32(a >> 32); in fdt_bus_default_translate()
[all …]
|
| /openbmc/qemu/include/exec/ |
| H A D | translator.h | 4 * Copyright (C) 2016-2017 Lluís Vilanova <vilanova@ac.upc.edu>
7 * See the COPYING file in the top-level directory.
14 * Include this header from a target-specific file, and add a
18 * member in your target-specific DisasContext.
27 * @tb: translation block
29 * @pc: guest virtual program counter address
30 * @host_pc: host physical program counter address
33 * the target-specific DisasContext, and then invoke translator_loop.
43 * @DISAS_TARGET_*: Start of target-specific conditions.
67 * @tb: Translation block for this disassembly.
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/bus/ |
| H A D | socionext,uniphier-system-bus.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
15 controller registers provide the control for the translation from the offset
16 within each bank to the CPU-viewed address. The needed setup includes the
17 base address, the size of each bank. Optionally, some timing parameters can
21 - Masahiro Yamada <yamada.masahiro@socionext.com>
[all …]
|
| /openbmc/u-boot/arch/m68k/include/asm/ |
| H A D | immap_5445x.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
89 u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
91 u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */
92 u16 cir; /* Chip Identification Register (Read-only) */
96 u16 uocsr; /* USB On-the-Go Controller Status Register */
106 u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */
121 u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */
122 u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/iommu/ |
| H A D | iommu.txt | 10 * Remap address space to allow devices to access physical memory ranges that
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
20 address regions.
22 * Provide address space isolation between multiple contexts.
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
[all …]
|
| /openbmc/qemu/docs/system/arm/ |
| H A D | emulation.rst | 3 A-profile CPU architecture support
7 Armv8 and Armv9 versions of the A-profile architecture. It also has support for
10 - FEAT_AA32BF16 (AArch32 BFloat16 instructions)
11 - FEAT_AA32EL0 (Support for AArch32 at EL0)
12 - FEAT_AA32EL1 (Support for AArch32 at EL1)
13 - FEAT_AA32EL2 (Support for AArch32 at EL2)
14 - FEAT_AA32EL3 (Support for AArch32 at EL3)
15 - FEAT_AA32HPD (AArch32 hierarchical permission disables)
16 - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
17 - FEAT_AA64EL0 (Support for AArch64 at EL0)
[all …]
|
| /openbmc/libcper/include/libcper/sections/ |
| H A D | cper-section-dmar-generic.h | 21 "DMA Address Out of Bounds", "Invalid Read/Write", \
32 "Reserved bit set to non-zero value in the domain mapping table.", \
33 "DMA request to access an address beyond the device address width.", \
36 "DMAr unit's attempt to access the address translation table resulted in an error.", \
37 "Reserved bit set to non-zero value in the address translation table.", \
59 "Untranslated Request", "Translation Request" \
69 "VT-d", "IOMMU" \
|
| /openbmc/linux/Documentation/scsi/ |
| H A D | aha152x.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 Adaptec AHA-1520/1522 SCSI driver for Linux (aha152x)
8 Copyright |copy| 1993-1999 Jürgen Fischer <fischer@norbit.de>
14 bottom-half handler complete()).
26 IOPORT base io address (0x340/0x140)
27 IRQ interrupt level (9-12; default 11)
28 SCSI_ID scsi id of controller (0-7; default 7)
33 EXT_TRANS: enable extended translation (0/1: default 0 [off])
42 - DAUTOCONF
43 use configuration the controller reports (AHA-152x only)
[all …]
|
| /openbmc/linux/arch/arm64/mm/ |
| H A D | fault.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 1995-2004 Russell King
21 #include <linux/page-flags.h>
36 #include <asm/debug-monitors.h>
115 esr_to_fault_info(esr)->name); in mem_abort_decode()
125 return __pa_symbol(mm->pgd); in mm_to_pgd_phys()
127 return (unsigned long)virt_to_phys(mm->pgd); in mm_to_pgd_phys()
141 mm = current->active_mm; in show_pte()
143 pr_alert("[%016lx] user address but active_mm is swapper\n", in show_pte()
151 pr_alert("[%016lx] address between user and kernel address ranges\n", in show_pte()
[all …]
|
| /openbmc/linux/Documentation/arch/arm64/ |
| H A D | tagged-pointers.rst | 10 addresses in the AArch64 translation system and their potential uses
13 The kernel configures the translation tables so that translations made
15 the virtual address ignored by the translation hardware. This frees up
20 --------------------------------------
23 an address tag of 0x00, unless the application enables the AArch64
24 Tagged Address ABI explicitly
25 (Documentation/arch/arm64/tagged-address-abi.rst).
29 - pointer arguments to system calls, including pointers in structures
32 - the stack pointer (sp), e.g. when interpreting it to deliver a
35 - the frame pointer (x29) and frame records, e.g. when interpreting
[all …]
|
| /openbmc/linux/Documentation/virt/kvm/x86/ |
| H A D | mmu.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 - correctness:
18 - security:
21 - performance:
23 - scaling:
25 - hardware:
27 - integration:
31 - dirty tracking:
33 and framebuffer-based displays
34 - footprint:
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | raideng.txt | 3 RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID
11 - compatible: Should contain "fsl,raideng-v1.0" as the value
15 - reg: offset and length of the register set for the device
16 - ranges: standard ranges property specifying the translation
17 between child address space and parent address space
22 compatible = "fsl,raideng-v1.0";
23 #address-cells = <1>;
24 #size-cells = <1>;
30 There must be a sub-node for each job queue present in RAID Engine
31 This node must be a sub-node of the main RAID Engine node
[all …]
|
| /openbmc/linux/drivers/acpi/acpica/ |
| H A D | rsdumpinfo.c | 1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: rsdumpinfo - Tables used to display resource descriptors.
59 "Start-Dependent-Functions", NULL},
70 "End-Dependent-Functions", NULL}
75 {ACPI_RSD_1BITFLAG, ACPI_RSD_OFFSET(io.io_decode), "Address Decoding",
77 {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(io.minimum), "Address Minimum", NULL},
78 {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(io.maximum), "Address Maximum", NULL},
80 {ACPI_RSD_UINT8, ACPI_RSD_OFFSET(io.address_length), "Address Length",
87 {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(fixed_io.address), "Address", NULL},
89 "Address Length", NULL}
[all …]
|
| /openbmc/qemu/hw/riscv/ |
| H A D | riscv-iommu.h | 2 * QEMU emulation of an RISC-V IOMMU
4 * Copyright (C) 2022-2023 Rivos Inc.
32 uint32_t bus; /* PCI bus mapping for non-root endpoints */
38 bool enable_off; /* Enable out-of-reset OFF mode (DMA disabled) */
41 bool enable_s_stage; /* Enable S/VS-Stage translation */
42 bool enable_g_stage; /* Enable G-Stage translation */
47 dma_addr_t cq_addr; /* Command queue base physical address */
48 dma_addr_t fq_addr; /* Fault/event queue base physical address */
49 dma_addr_t pq_addr; /* Page request queue base physical address */
63 /* IOMMU target address space */
[all …]
|
| /openbmc/linux/drivers/dma/fsl-dpaa2-qdma/ |
| H A D | dpaa2-qdma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 u32 rbpcmd; /* Route-by-port command */
37 #define QMAN_FD_BMT_ENABLE BIT(15) /* bypass memory translation */
38 #define QMAN_FD_BMT_DISABLE (0) /* bypass memory translation */
53 #define QMAN_FD_VA_ENABLE BIT(14) /* Address used is virtual address */
54 #define QMAN_FD_VA_DISABLE (0)/* Address used is a real address */
55 /* Flow Context: 49bit physical address */
57 #define QMAN_FD_CBMT_DISABLE (0) /* Flow Context: 64bit virtual address */
62 #define QDMA_FL_BMT_ENABLE BIT(15) /* enable bypass memory translation */
63 #define QDMA_FL_BMT_DISABLE (0x0) /* enable bypass memory translation */
[all …]
|
| /openbmc/linux/Documentation/driver-api/ |
| H A D | ntb.rst | 5 NTB (Non-Transparent Bridge) is a type of PCI-Express bridge chip that connects
6 the separate memory systems of two or more computers to the same PCI-Express
8 registers and memory translation windows, as well as non common features like
9 scratchpad and message registers. Scratchpad registers are read-and-writable
11 exchange a small amount of information at a fixed address. Message registers can
36 ----------------------------------------
42 inbound translation configured on the local ntb port and outbound translation
46 Inbound translation:
50 | dma-mapped |-ntb_mw_set_trans(addr) |
52 | (addr) |<======| MW xlat addr |<====| MW base addr |<== memory-mapped IO
[all …]
|
| /openbmc/linux/arch/arm64/kvm/ |
| H A D | stacktrace.c | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * 1) Non-protected nVHE mode - the host can directly access the
12 * 2) pKVM (protected nVHE) mode - the host cannot directly access
28 unsigned long low = (unsigned long)stacktrace_info->overflow_stack_base; in stackinfo_get_overflow()
52 unsigned long low = (unsigned long)stacktrace_info->stack_base; in stackinfo_get_hyp()
73 * kvm_nvhe_stack_kern_va - Convert KVM nVHE HYP stack addresses to a kernel VAs
76 * allow for guard pages below the stack. Consequently, the fixed offset address
77 * translation macros won't work here.
102 *addr = *addr - stack_hyp.low + stack_kern.low; in kvm_nvhe_stack_kern_va()
107 * Convert a KVN nVHE HYP frame record address to a kernel VA
[all …]
|