include/asm/immap_5445x.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
89 	u16 ccr;		/* Chip Configuration Register (256 TEPBGA, Read-only) */
91 	u16 rcon;		/* Reset Configuration (256 TEPBGA, Read-only) */
92 	u16 cir;		/* Chip Identification Register (Read-only) */
96 	u16 uocsr;		/* USB On-the-Go Controller Status Register */
106 	u8 podr_cs;		/* Flexbus Chip-Select Port Output Data Register */
121 	u8 podr_fbadmh;		/* Flexbus AD Med-High Port Output Data Register */
122 	u8 podr_fbadml;		/* Flexbus AD Med-Low Port Output Data Register */
129 	u8 pddr_cs;		/* Flexbus Chip-Select Port Data Direction Register */
144 	u8 pddr_fbadmh;		/* Flexbus AD Med-High Port Data Direction Register */
145 	u8 pddr_fbadml;		/* Flexbus AD Med-Low Port Data Direction Register */
152 	u8 ppdsdr_cs;		/* Flexbus Chip-Select Port Pin Data/Set Data Register */
167 	u8 ppdsdr_fbadmh;	/* Flexbus AD Med-High Port Pin Data/Set Data Register */
168 	u8 ppdsdr_fbadml;	/* Flexbus AD Med-Low Port Pin Data/Set Data Register */
175 	u8 pclrr_cs;		/* Flexbus Chip-Select Port Clear Output Data Register */
190 	u8 pclrr_fbadmh;	/* Flexbus AD Med-High Port Clear Output Data Register */
191 	u8 pclrr_fbadml;	/* Flexbus AD Med-Low Port Clear Output Data Register */
197 	u8 par_be;		/* Flexbus Byte-Enable Pin Assignment Register */
198 	u8 par_cs;		/* Flexbus Chip-Select Pin Assignment Register */
249 	u32 bar0;		/* 0x10 Base address register 0 Register */
250 	u32 bar1;		/* 0x14 Base address register 1 Register */
251 	u32 bar2;		/* 0x18 Base address register 2 Register */
252 	u32 bar3;		/* 0x1c Base address register 3 Register */
253 	u32 bar4;		/* 0x20 Base address register 4 Register */
254 	u32 bar5;		/* 0x24 Base address register 5 Register */
257 	u32 erbar;		/* 0x30 Expansion ROM Base Address Register */
261 	u32 rsvd2[8];		/* 0x40 - 0x5f */
265 	u32 tbatr0a;		/* 0x64 Target Base Address Translation Register  0 */
266 	u32 tbatr1a;		/* 0x68 Target Base Address Translation Register  1 */
268 	u32 iw0btar;		/* 0x70 Initiator Window 0 Base/Translation addr */
269 	u32 iw1btar;		/* 0x74 Initiator Window 1 Base/Translation addr */
270 	u32 iw2btar;		/* 0x78 Initiator Window 2 Base/Translation addr */
276 	u32 tbatr0;		/* 0x90 Target Base Address Translation Register  0 */
277 	u32 tbatr1;		/* 0x94 Target Base Address Translation Register  1 */
278 	u32 tbatr2;		/* 0x98 Target Base Address Translation Register  2 */
279 	u32 tbatr3;		/* 0x9c Target Base Address Translation Register  3 */
280 	u32 tbatr4;		/* 0xa0 Target Base Address Translation Register  4 */
281 	u32 tbatr5;		/* 0xa4 Target Base Address Translation Register  5 */
283 	u32 rsvd4[19];		/* 0xac - 0xf7 */
284 	u32 car;		/* 0xf8 Configuration Address Register */
310 	u8 rsvd1[19];		/* 0x00 - 0x12 */
312 	u16 rsvd2;		/* 0x14 - 0x15 */
314 	u8 rsvd3[3];		/* 0x18 - 0x1A */
316 	u8 rsvd4[3];		/* 0x1C - 0x1E */
318 	u32 rsvd5;		/* 0x20 - 0x23 */
320 	u8 rsvd6[74];		/* 0x25 - 0x6F */
326 	u32 rsvd8;		/* 0x78 - 0x7B */