include/asm/fsl_pci.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright 2007,2009-2012 Freescale Semiconductor, Inc.
17 /* Freescale-specific PCI config registers */
37  * PCI Translation Registers
40 	u32	potar;		/* 0x00 - Address */
41 	u32	potear;		/* 0x04 - Address Extended */
42 	u32	powbar;		/* 0x08 - Window Base Address */
44 	u32	powar;		/* 0x10 - Window Attributes */
54 	u32	pitar;		/* 0x00 - Address */
56 	u32	piwbar;		/* 0x08 - Window Base Address */
57 	u32	piwbear;	/* 0x0c - Window Base Address Extended */
58 	u32	piwar;		/* 0x10 - Window Attributes */
69 	u32	cfg_addr;	/* 0x000 - PCI Configuration Address Register */
70 	u32	cfg_data;	/* 0x004 - PCI Configuration Data Register */
71 	u32	int_ack;	/* 0x008 - PCI Interrupt Acknowledge Register */
72 	u32	out_comp_to;	/* 0x00C - PCI Outbound Completion Timeout Register */
73 	u32	out_conf_to;	/* 0x010 - PCI Configuration Timeout Register */
74 	u32	config;		/* 0x014 - PCIE CONFIG Register */
75 	u32	int_status;	/* 0x018 - PCIE interrupt status register */
77 	u32	pme_msg_det;	/* 0x020 - PCIE PME & message detect register */
78 	u32	pme_msg_dis;	/* 0x024 - PCIE PME & message disable register */
79 	u32	pme_msg_int_en;	/* 0x028 - PCIE PME & message interrupt enable register */
80 	u32	pm_command;	/* 0x02c - PCIE PM Command register */
81 	char	res3[2188];	/*     (0x8bc - 0x30 = 2188) */
82 	u32	dbi_ro_wr_en;	/* 0x8bc - DBI read only write enable reg */
83 	char	res4[824];	/*     (0xbf8 - 0x8c0 = 824) */
84 	u32	block_rev1;	/* 0xbf8 - PCIE Block Revision register 1 */
85 	u32	block_rev2;	/* 0xbfc - PCIE Block Revision register 2 */
87 	pot_t	pot[5];		/* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
89 	pit_t	pmit;		/* 0xd00 - 0xd9c Inbound ATMU's MSI */
91 	pit_t	pit[4];		/* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */
98 	u32	potar0;		/* 0xc00 - PCI Outbound Transaction Address Register 0 */
99 	u32	potear0;	/* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
101 	u32	powar0;		/* 0xc10 - PCI Outbound Window Attributes Register 0 */
103 	u32	potar1;		/* 0xc20 - PCI Outbound Transaction Address Register 1 */
104 	u32	potear1;	/* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
105 	u32	powbar1;	/* 0xc28 - PCI Outbound Window Base Address Register 1 */
107 	u32	powar1;		/* 0xc30 - PCI Outbound Window Attributes Register 1 */
109 	u32	potar2;		/* 0xc40 - PCI Outbound Transaction Address Register 2 */
110 	u32	potear2;	/* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
111 	u32	powbar2;	/* 0xc48 - PCI Outbound Window Base Address Register 2 */
113 	u32	powar2;		/* 0xc50 - PCI Outbound Window Attributes Register 2 */
115 	u32	potar3;		/* 0xc60 - PCI Outbound Transaction Address Register 3 */
116 	u32	potear3;	/* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
117 	u32	powbar3;	/* 0xc68 - PCI Outbound Window Base Address Register 3 */
119 	u32	powar3;		/* 0xc70 - PCI Outbound Window Attributes Register 3 */
121 	u32	potar4;		/* 0xc80 - PCI Outbound Transaction Address Register 4 */
122 	u32	potear4;	/* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
123 	u32	powbar4;	/* 0xc88 - PCI Outbound Window Base Address Register 4 */
125 	u32	powar4;		/* 0xc90 - PCI Outbound Window Attributes Register 4 */
127 	u32	pitar3;		/* 0xda0 - PCI Inbound Translation Address Register 3 */
129 	u32	piwbar3;	/* 0xda8 - PCI Inbound Window Base Address Register 3 */
130 	u32	piwbear3;	/* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
131 	u32	piwar3;		/* 0xdb0 - PCI Inbound Window Attributes Register 3 */
133 	u32	pitar2;		/* 0xdc0 - PCI Inbound Translation Address Register 2 */
135 	u32	piwbar2;	/* 0xdc8 - PCI Inbound Window Base Address Register 2 */
136 	u32	piwbear2;	/* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
137 	u32	piwar2;		/* 0xdd0 - PCI Inbound Window Attributes Register 2 */
139 	u32	pitar1;		/* 0xde0 - PCI Inbound Translation Address Register 1 */
141 	u32	piwbar1;	/* 0xde8 - PCI Inbound Window Base Address Register 1 */
143 	u32	piwar1;		/* 0xdf0 - PCI Inbound Window Attributes Register 1 */
146 	u32	pedr;		/* 0xe00 - PCI Error Detect Register */
147 	u32	pecdr;		/* 0xe04 - PCI Error Capture Disable Register */
148 	u32	peer;		/* 0xe08 - PCI Error Interrupt Enable Register */
149 	u32	peattrcr;	/* 0xe0c - PCI Error Attributes Capture Register */
150 	u32	peaddrcr;	/* 0xe10 - PCI Error Address Capture Register */
151 /*	u32	perr_disr	 * 0xe10 - PCIE Erorr Disable Register */
152 	u32	peextaddrcr;	/* 0xe14 - PCI	Error Extended Address Capture Register */
153 	u32	pedlcr;		/* 0xe18 - PCI Error Data Low Capture Register */
154 	u32	pedhcr;		/* 0xe1c - PCI Error Error Data High Capture Register */
155 	u32	gas_timr;	/* 0xe20 - PCI Gasket Timer Register */
156 /*	u32	perr_cap_stat;	 * 0xe20 - PCIE Error Capture Status Register */
158 	u32	perr_cap0;	/* 0xe28 - PCIE Error Capture Register 0 */
159 	u32	perr_cap1;	/* 0xe2c - PCIE Error Capture Register 1 */
160 	u32	perr_cap2;	/* 0xe30 - PCIE Error Capture Register 2 */
161 	u32	perr_cap3;	/* 0xe34 - PCIE Error Capture Register 3 */
163 	u32	pdb_stat;	/* 0xf00 - PCIE Debug Status */
165 	u32	pex_csr0;	/* 0xf14 - PEX Control/Status register 0*/
166 	u32	pex_csr1;	/* 0xf18 - PEX Control/Status register 1*/
245 #define FSL_PCI_COMPAT	"fsl,mpc8540-pci"
249 #define FSL_PCIE_COMPAT	"fsl,mpc8548-pcie"
262 #define FSL_PCI_COMPAT	"fsl,mpc8610-pci"
263 #define FSL_PCIE_COMPAT	"fsl,mpc8641-pcie"