hw/riscv/riscv-iommu.h

2  * QEMU emulation of an RISC-V IOMMU
4  * Copyright (C) 2022-2023 Rivos Inc.
32     uint32_t bus;         /* PCI bus mapping for non-root endpoints */
38     bool enable_off;      /* Enable out-of-reset OFF mode (DMA disabled) */
41     bool enable_s_stage;  /* Enable S/VS-Stage translation */
42     bool enable_g_stage;  /* Enable G-Stage translation */
47     dma_addr_t cq_addr;   /* Command queue base physical address */
48     dma_addr_t fq_addr;   /* Fault/event queue base physical address */
49     dma_addr_t pq_addr;   /* Page request queue base physical address */
63     /* IOMMU target address space */
71     GHashTable *ctx_cache;          /* Device translation Context Cache */
73     GHashTable *iot_cache;          /* IO Translated Address Cache */
74     unsigned iot_limit;             /* IO Translation Cache size limit */
79     uint8_t *regs_wc;  /* write-1-to-clear mask */
80     uint8_t *regs_ro;  /* read-only mask */
95     uint32_t val = ldl_le_p(s->regs_rw + idx);  in riscv_iommu_reg_mod32()
96     stl_le_p(s->regs_rw + idx, (val & ~clr) | set);  in riscv_iommu_reg_mod32()
103     stl_le_p(s->regs_rw + idx, set);  in riscv_iommu_reg_set32()
108     return ldl_le_p(s->regs_rw + idx);  in riscv_iommu_reg_get32()
114     uint64_t val = ldq_le_p(s->regs_rw + idx);  in riscv_iommu_reg_mod64()
115     stq_le_p(s->regs_rw + idx, (val & ~clr) | set);  in riscv_iommu_reg_mod64()
122     stq_le_p(s->regs_rw + idx, set);  in riscv_iommu_reg_set64()
128     return ldq_le_p(s->regs_rw + idx);  in riscv_iommu_reg_get64()