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/openbmc/linux/arch/arm/mach-sa1100/include/mach/
H A Dh3xxx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
39 /* machine-specific gpios */
60 …CARD_RESET (H3XXX_EGPIO_BASE + 1) /* reset the attached pcmcia/compactflash card. active high. */
61 …e H3XXX_EGPIO_OPT_RESET (H3XXX_EGPIO_BASE + 2) /* reset the attached option pack. active high. */
62 #define H3XXX_EGPIO_CODEC_NRESET (H3XXX_EGPIO_BASE + 3) /* reset the onboard UDA1341. active low. …
63 …H3XXX_EGPIO_OPT_NVRAM_ON (H3XXX_EGPIO_BASE + 4) /* apply power to optionpack nvram, active high. */
64 #define H3XXX_EGPIO_OPT_ON (H3XXX_EGPIO_BASE + 5) /* full power to option pack. active high. */
65 #define H3XXX_EGPIO_LCD_ON (H3XXX_EGPIO_BASE + 6) /* enable 3.3V to LCD. active high. */
66 #define H3XXX_EGPIO_RS232_ON (H3XXX_EGPIO_BASE + 7) /* UART3 transceiver force on. Active high. */
69 #define H3600_EGPIO_LCD_PCI (H3XXX_EGPIO_BASE + 8) /* LCD control IC enable. active high. */
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dfreeze_controller.c1 // SPDX-License-Identifier: GPL-2.0+
33 writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); in sys_mgr_frzctrl_freeze_req()
38 &freeze_controller_base->vioctrl + channel_id); in sys_mgr_frzctrl_freeze_req()
41 * Assert active low enrnsl, plniotri in sys_mgr_frzctrl_freeze_req()
52 * Assert active low bhniotri signal and de-assert in sys_mgr_frzctrl_freeze_req()
53 * active high csrdone in sys_mgr_frzctrl_freeze_req()
66 * Assert active low enrnsl, plniotri and in sys_mgr_frzctrl_freeze_req()
73 clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); in sys_mgr_frzctrl_freeze_req()
76 * assert active low bhniotri & nfrzdrv signals, in sys_mgr_frzctrl_freeze_req()
77 * de-assert active high csrdone and assert in sys_mgr_frzctrl_freeze_req()
[all …]
/openbmc/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
21 # Active Time 25.422 us 15.253 ms
28 mode "640x480-60"
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
46 # Active Time 20.317 us 12.800 ms
52 mode "640x480-75"
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
67 # Active Time 17.778 us 11.093 ms
73 mode "640x480-85"
[all …]
/openbmc/linux/Documentation/firmware-guide/acpi/
H A Dgpio-properties.rst1 .. SPDX-License-Identifier: GPL-2.0
31 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
34 Package () { "reset-gpios", Package () { ^BTH, 1, 1, 0 } },
35 Package () { "shutdown-gpios", Package () { ^BTH, 0, 0, 0 } },
55 active low or high, the "active_low" argument can be used here. Setting
56 it to 1 marks the GPIO as active low.
61 In our Bluetooth example the "reset-gpios" refers to the second GpioIo()
70 +-------------+-------------+-----------------------------------------------+
74 +-------------+-------------+-----------------------------------------------+
76 +-------------+-------------+-----------------------------------------------+
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dnvidia,tegra20-gmi.txt4 external memory. Can be used to attach various high speed devices such as
10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dtegra30-cardhu.dts1 /dts-v1/;
10 stdout-path = &uarta;
30 pcie-controller@00003000 {
34 avdd-pexb-supply = <&ldo1_reg>;
35 vdd-pexb-supply = <&ldo1_reg>;
36 avdd-pex-pll-supply = <&ldo1_reg>;
37 hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
38 vddio-pex-ctl-supply = <&sys_3v3_reg>;
39 avdd-plle-supply = <&ldo2_reg>;
42 nvidia,num-lanes = <4>;
[all …]
H A Drk3288-veyron-speedy.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron-chromebook.dtsi"
10 #include "cros-ec-sbs.dtsi"
11 #include "rk3288-veyron-speedy-u-boot.dtsi"
15 compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
16 "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
17 "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
18 "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
19 "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-cardhu-a04.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-cardhu.dtsi"
10 compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
14 power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
15 bus-width = <4>;
16 keep-power-in-suspend;
19 ddr_reg: regulator-ddr {
20 compatible = "regulator-fixed";
21 regulator-name = "ddr";
[all …]
H A Dtegra30-cardhu-a02.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-cardhu.dtsi"
10 compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
14 power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
15 bus-width = <4>;
16 keep-power-in-suspend;
19 ddr_reg: regulator-ddr {
20 compatible = "regulator-fixed";
21 regulator-name = "vdd_ddr";
[all …]
/openbmc/openbmc/meta-quanta/meta-q71l/recipes-phosphor/quanta-powerctrl/files/
H A Dinit_once.sh5 if [ $# -ne 2 ]; then
17 # FM_BMC_READY_N, GPIO Q4, active low
18 set_gpio_active_low $((GPIO_BASE + 128 + 4)) high
20 # FM_BMC_SSB_SMI_LPC_N, GPIO Q6, active low
21 set_gpio_active_low $((GPIO_BASE + 128 + 6)) high
23 # FM_BMC_SYS_THROTTLE_N, GPIO A3, active low
24 set_gpio_active_low $((GPIO_BASE + 0 + 3)) high
26 # FM_BMC_SSB_SCI_LPC_N, GPIO E4, active low
27 set_gpio_active_low $((GPIO_BASE + 32 + 4)) high
29 # FP_PWR_BTN_PASS_R_N, GPIO D3, active low
[all …]
/openbmc/linux/Documentation/driver-api/gpio/
H A Dintro.rst16 - The descriptor-based interface is the preferred way to manipulate GPIOs,
18 - The legacy integer-based interface which is considered deprecated (but still
21 The remainder of this document applies to the new descriptor-based interface.
23 integer-based interface.
29 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
37 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
38 non-dedicated pin can be configured as a GPIO; and most chips have at least
43 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
48 - Output values are writable (high=1, low=0). Some chips also have
50 value might be driven, supporting "wire-OR" and similar schemes for the
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpiolib-of.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2007-2008 MontaVista Software, Inc.
26 #include "gpiolib-of.h"
29 * This is Linux-specific flags. By default controllers' and Linux' mapping
31 * Linux-specific in their .xlate callback. Though, 1:1 mapping is recommended.
44 * of_gpio_named_count() - Count GPIOs for a device
51 * -EINVAL for an incorrectly formed gpios property, or
52 * -ENOENT for a missing gpios property
66 return of_count_phandle_with_args(np, propname, "#gpio-cells"); in of_gpio_named_count()
70 * of_gpio_spi_cs_get_count() - special GPIO counting for SPI
[all …]
/openbmc/u-boot/doc/device-tree-bindings/video/
H A Ddisplaymode.txt4 (from http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html)
7 - xres, yres: Display resolution
8 - left-margin, right-margin, hsync-len: Horizontal Display timing
10 - upper-margin, lower-margin, vsync-len: Vertical display timing
12 - clock: display clock in Hz
15 - width-mm, height-mm: Display dimensions in mm
16 - hsync-active-high (bool): Hsync pulse is active high
17 - vsync-active-high (bool): Vsync pulse is active high
18 - interlaced (bool): This is an interlaced mode
19 - doublescan (bool): This is a doublescan mode
[all …]
H A Ddisplay-timing.txt1 display-timing bindings
4 display-timings node
5 --------------------
8 - none
11 - native-mode: The native mode for the display, in case multiple modes are
15 --------------
18 - hactive, vactive: display resolution
19 - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters
21 vfront-porch, vback-porch, vsync-len: vertical display timing parameters in
23 - clock-frequency: display clock in Hz
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dtlv320adcx140.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Andrew Davis <afd@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
28 - ti,tlv320adc3140
29 - ti,tlv320adc5140
30 - ti,tlv320adc6140
[all …]
/openbmc/linux/include/media/i2c/
H A Dtvp7002.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
6 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
19 * struct tvp7002_config - Platform dependent data
21 * 0 - Data clocked out on rising edge of DATACLK signal
22 * 1 - Data clocked out on falling edge of DATACLK signal
24 * 0 - Active low HSYNC output, 1 - Active high HSYNC output
26 * 0 - Active low VSYNC output, 1 - Active high VSYNC output
27 *@fid_polarity: Active-high Field ID polarity.
28 * 0 - The field ID output is set to logic 1 for an odd field
[all …]
/openbmc/u-boot/drivers/video/
H A Dam335x-fb.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
4 * B&R Industrial Automation GmbH - http://www.br-automation.com
29 * 0 = DE is low-active
30 * 1 = DE is high-active
33 * 0 = pix-clk is high-active
34 * 1 = pic-clk is low-active
37 * 0 = HSYNC is active high
41 * 0 = VSYNC is active high
42 * 1 = VSYNC is active low
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dadi,ad7606.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
14 https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606_7606-6_7606-4.pdf
15 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7606B.pdf
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7616.pdf
21 - adi,ad7605-4
22 - adi,ad7606-8
23 - adi,ad7606-6
[all …]
/openbmc/skeleton/libopenbmc_intf/
H A Dgpio_configs.h9 * http://www.apache.org/licenses/LICENSE-2.0
26 /* Optional active high pin enabling writes to latched power_up pins. */
28 /* Active high pin that is asserted following successful host power up. */
33 /* TRUE for active high */
38 /* TRUE for active high */
42 /* TRUE for active high */
/openbmc/linux/include/dt-bindings/sound/
H A Dcs35l45.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header
12 * cirrus,asp-sdout-hiz-ctrl
14 * TX_HIZ_UNUSED: TX pin high-impedance during unused slots.
15 * TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.
21 * Optional GPIOX Sub-nodes:
22 * The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
23 * sub-nodes for configuring the GPIO pins.
25 * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
30 * - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Drs485.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 direction for the built-in half-duplex mode. The properties described
11 hereafter shall be given to a half-duplex capable UART node.
14 - Rob Herring <robh@kernel.org>
17 rs485-rts-delay:
18 description: prop-encoded-array <a b>
19 $ref: /schemas/types.yaml#/definitions/uint32-array
21 - description: Delay between rts signal and beginning of data sent in
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Dov7670.txt8 - compatible: should be "ovti,ov7670"
9 - clocks: reference to the xclk input clock.
10 - clock-names: should be "xclk".
13 - hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
14 - vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
17 - reset-gpios: reference to the GPIO connected to the resetb pin, if any.
18 Active is low.
19 - powerdown-gpios: reference to the GPIO connected to the pwdn pin, if any.
20 Active is high.
21 - ov7670,pclk-hb-disable: a boolean property to suppress pixel clock output
[all …]
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dfixed-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/fixed-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
16 expected to have the regulator-min-microvolt and regulator-max-microvolt
20 - $ref: regulator.yaml#
21 - if:
25 const: regulator-fixed-clock
[all …]
H A Dgpio-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/gpio-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
18 - $ref: regulator.yaml#
22 const: regulator-gpio
24 regulator-name: true
26 enable-gpios:
[all …]
/openbmc/linux/arch/arm/boot/dts/synaptics/
H A Dberlin2q-marvell-dmp.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
12 model = "Marvell BG2-Q DMP";
13 compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin";
22 stdout-path = "serial0:115200n8";
26 compatible = "simple-bus";
27 #address-cells = <1>;
28 #size-cells = <0>;
[all …]

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