Lines Matching +full:active +full:- +full:high
16 - The descriptor-based interface is the preferred way to manipulate GPIOs,
18 - The legacy integer-based interface which is considered deprecated (but still
21 The remainder of this document applies to the new descriptor-based interface.
23 integer-based interface.
29 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
37 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
38 non-dedicated pin can be configured as a GPIO; and most chips have at least
43 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
48 - Output values are writable (high=1, low=0). Some chips also have
50 value might be driven, supporting "wire-OR" and similar schemes for the
53 - Input values are likewise readable (1, 0). Some chips support readback
54 of pins configured as "output", which is very useful in such "wire-OR"
56 input de-glitch/debounce logic, sometimes with software controls.
58 - Inputs can often be used as IRQ signals, often edge triggered but
62 - Usually a GPIO will be configurable as either input or output, as needed
65 - Most GPIOs can be accessed while holding spinlocks, but those accessed
69 MMC/SD card insertion/removal, detecting card write-protect status, driving
70 a LED, configuring a transceiver, bit-banging a serial bus, poking a hardware
81 Active-High and Active-Low
82 --------------------------
83 It is natural to assume that a GPIO is "active" when its output signal is 1
84 ("high"), and inactive when it is 0 ("low"). However in practice the signal of a
86 to have different conventions about what "active" means. Such decisions should
88 being either active-high ("1" means "active", the default) or active-low ("0"
89 means "active") so that drivers only need to worry about the logical signal and
93 --------------------------
95 level is actually driven), or "open source" (where only the high signal level is
97 used for TTL. A pullup or pulldown resistor causes the high or low signal level.
98 This is sometimes called a "wire-AND"; or more practically, from the negative
99 logic (low=true) perspective this is a "wire-OR".
101 One common example of an open drain signal is a shared active-low IRQ line.
112 **HIGH**: ``gpiod_direction_input(gpio)`` ... this turns off the output, so
116 high signal and configuring the GPIO as input for low. This open drain/open
119 If you are "driving" the signal high but gpiod_get_value(gpio) reports a low