| /openbmc/phosphor-dbus-interfaces/yaml/com/ibm/ipzvpd/ |
| H A D | CP00.interface.yaml | 4 - name: RT
8 - name: VD
12 - name: PG
16 - name: MK
20 - name: PD_G
24 - name: PD_R
28 - name: SB
32 - name: PZ
36 - name: AW
39 AW keyword.Array Write-assist.
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| /openbmc/docs/designs/ |
| H A D | design-template.md | 1 ---
3 # Document Guidelines - _Delete this section_
7 - Not all new features need a design document. If a feature can be contributed
11 - The focus of the document is to define the problem we need to solve and
12 analyse the trade-offs of different solutions. You should concentrate on
13 interactions between components, though analysing the trade-offs often
16 - Write this document as an [argumentative essay][argumentative-essay]. Good
19 [argumentative-essay]: https://www.grammarly.com/blog/argumentative-essay/
21 - This is not intended to be extensive documentation for a new feature.
23 - You should get your design reviewed and merged before writing your code.
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| H A D | power-systems-memory-preserving-reboot.md | 15 don't have access to a non-volatile storage to store this content after a
18 explains the high-level flow of warm reboot and extraction of the resulting dump
23 - **Boot**: The process of initializing hardware components in a computer system
26 - **Hostboot**: The firmware runs on the host processors and performs all
28 [read more](https://github.com/open-power/docs/blob/master/hostboot/HostBoot_PG.md)
30 - **Self Boot Engine (SBE)**: A microcontroller built into the host processors
31 of POWER systems to assist in initializing the processor during the boot. It
35 - **Master Processor**: The processor which gets initialized first to execute
38 - **POWER Hardware Abstraction Layer (PHAL)**: A software component on the BMC
41 - **Hypervisor**: A hypervisor (or virtual machine monitor, VMM) is a computer
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| /openbmc/qemu/include/exec/ |
| H A D | memattrs.h | 10 * See the COPYING file in the top-level directory.
21 * all as non-overlapping bitfields in a single struct to avoid
33 * easier to have both fields to assist code that does not understand
47 /* Debug access that can even write to ROM. */
57 /* PCI - IOMMU operations, see PCIAddressType */
82 /* New-style MMIO accessors can indicate that the transaction failed.
84 * of some kind. The memory subsystem will bitwise-OR together results
|
| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | processor.h | 19 #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
67 #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
70 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
87 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
140 #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
147 #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
181 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
182 #define DCWR_COPY 0 /* Copy-back */
183 #define DCWR_WRITE 1 /* Write-through */
211 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
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| H A D | mmu.h | 28 unsigned long w:1; /* Write-thru cache mode */
37 #define PP_RWXX 0 /* Supervisor read/write, User none */
38 #define PP_RWRX 1 /* Supervisor read/write, User read */
39 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
47 unsigned long n:1; /* No-execute */
90 unsigned long w:1; /* Write-thru cache */
109 * Simulated two-level MMU. This structure is used by the kernel
133 pte **pmap; /* Two-level page-map structure */
170 #define BATL_PP_01 0x00000001 /* Read-only */
171 #define BATL_PP_10 0x00000002 /* Read-write */
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| /openbmc/qemu/target/hppa/ |
| H A D | int_helper.c | 21 #include "qemu/main-loop.h"
24 #include "exec/helper-proto.h"
31 if (cpu->env.cr[CR_EIRR]) { in eval_interrupt()
39 * can write to this word to raise an external interrupt on the target CPU.
48 return cpu->env.cr[CR_EIRR]; in io_eir_read()
55 CPUHPPAState *env = &cpu->env; in io_eir_write()
60 if (hppa_is_pa20(env) && env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT) { in io_eir_write()
65 env->cr[CR_EIRR] |= 1ull << le_bit; in io_eir_write()
71 .write = io_eir_write,
86 env->cr[CR_EIRR] &= ~val; in HELPER()
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| /openbmc/phosphor-power/ |
| H A D | pmbus.hpp | 139 // Bits [7:5] - 000 - Reserved
140 // Bit 4 - 1 - Unit does not power up until commanded by the CONTROL pin and
142 // Bit 3 - 0 - Unit ignores the on/off portion of the OPERATION command from
144 // Bit 2 - 1 - Unit requires the CONTROL pin to be asserted to start the unit.
145 // Bit 1 - 0 - Polarity of the CONTROL pin. Active low (Pull pin low to start
147 // Bit 0 - 1 - Turn off the output and stop transferring energy to the output as
166 * This is a base class for PMBus to assist with unit testing via mocking.
190 * @param[in] bus - I2C bus
191 * @param[in] address - I2C address (as a 2-byte string, e.g. 0069)
221 * @param[in] path - path to the sysfs directory
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| /openbmc/qemu/hw/ide/ |
| H A D | trace-events | 16 ide_cancel_dma_sync_buffered(void *fn, void *req) "invoking cb %p of buffered request %p with -ECAN…
42 sii3112_write(int size, uint64_t addr, uint64_t val) "bmdma: write (size %d) 0x%"PRIx64" : 0x%02"PR…
70 ahci_check_irq(void *s, uint32_t old, uint32_t new) "ahci(%p): check irq 0x%08x --> 0x%08x"
71 …nt32_t effective) "ahci(%p)[%d]: trigger irq +%s (0x%08x); irqstat: 0x%08x --> 0x%08x; effective: …
72 … int port, const char *reg, int offset, uint32_t val) "ahci(%p)[%d]: port write [reg:%s] @ 0x%x: 0…
73 …st char *reg, int offset, uint32_t val) "ahci(%p)[%d]: unimplemented port write [reg:%s] @ 0x%x: 0…
79 ahci_mem_write(void *s, unsigned size, uint64_t addr, uint64_t val) "ahci(%p): write%u @ 0x%"PRIx64…
80 …s, unsigned size, const char *reg, uint64_t addr) "ahci(%p) unimplemented write%u [reg:%s] @ 0x%"P…
81 …s, unsigned size, const char *reg, uint64_t addr, uint64_t val) "ahci(%p) write%u [reg:%s] @ 0x%"P…
82 ahci_mem_write_unimpl(void *s, unsigned size, uint64_t addr, uint64_t val) "ahci(%p): write%u to un…
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| /openbmc/qemu/docs/system/i386/ |
| H A D | hyperv.rst | 1 Hyper-V Enlightenments
6 -----------
11 It may, however, be hard-to-impossible to add support for these interfaces to
14 KVM on x86 implements Hyper-V Enlightenments for Windows guests. These features
15 make Windows and Hyper-V guests think they're running on top of a Hyper-V
16 compatible hypervisor and use Hyper-V specific features.
20 -----
22 No Hyper-V enlightenments are enabled by default by either KVM or QEMU. In
25 .. parsed-literal::
27 |qemu_system| --enable-kvm --cpu host,hv_relaxed,hv_vpindex,hv_time, ...
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| /openbmc/qemu/hw/misc/ |
| H A D | xlnx-versal-trng.c | 2 * Non-crypto strength model of the True Random Number Generator
5 * Copyright (c) 2017-2020 Xilinx Inc.
29 #include "hw/misc/xlnx-versal-trng.h"
33 #include "qemu/error-report.h"
34 #include "qemu/guest-random.h"
38 #include "hw/qdev-properties.h"
140 return s->hw_version < 0x0200; in trng_older_than_v2()
145 if (ARRAY_FIELD_EX32(s->regs, RESET, VAL)) { in trng_in_reset()
148 if (ARRAY_FIELD_EX32(s->regs, CTRL, PRNGSRST)) { in trng_in_reset()
157 return ARRAY_FIELD_EX32(s->regs, CTRL, TSTMODE); in trng_test_enabled()
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| /openbmc/u-boot/doc/ |
| H A D | README.x86 | 1 # SPDX-License-Identifier: GPL-2.0+
6 U-Boot on x86
9 This document describes the information about U-Boot running on x86 targets,
13 ------
14 U-Boot supports running as a coreboot [1] payload on x86. So far only Link
17 most of the low-level details.
19 U-Boot is a main bootloader on Intel Edison board.
21 U-Boot also supports booting directly from x86 reset vector, without coreboot.
23 'bare metal', U-Boot acts like a BIOS replacement. The following platforms
26 - Bayley Bay CRB
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| /openbmc/qemu/target/i386/nvmm/ |
| H A D | nvmm-all.c | 2 * Copyright (c) 2018-2019 Maxime Villard, All rights reserved.
7 * See the COPYING file in the top-level directory.
12 #include "system/address-spaces.h"
15 #include "accel/accel-ops.h"
19 #include "qemu/main-loop.h"
20 #include "qemu/error-report.h"
23 #include "accel/accel-cpu-target.h"
24 #include "host-cpu.h"
28 #include "nvmm-accel-ops.h"
37 /* Window-exiting for INTs/NMIs. */
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| /openbmc/u-boot/include/u-boot/ |
| H A D | zlib.h | 2 * This file is derived from zlib.h and zconf.h from the zlib-1.2.3
3 * distribution by Jean-loup Gailly and Mark Adler, with some additions
12 * whether an up-to-date version of this file is already installed.
15 /* zlib.h -- interface of the 'zlib' general purpose compression library
18 Copyright (C) 1995-2005 Jean-loup Gailly and Mark Adler
20 This software is provided 'as-is', without any express or implied
36 Jean-loup Gailly Mark Adler
56 /* zconf.h -- configuration of the zlib compression library
57 * Copyright (C) 1995-2005 Jean-loup Gailly.
64 * compile with -DZ_PREFIX. The "standard" zlib should be compiled without it.
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| /openbmc/qemu/target/ppc/ |
| H A D | cpu.h | 4 * Copyright (c) 2003-2007 Jocelyn Mayer
24 #include "qemu/cpu-float.h"
25 #include "exec/cpu-common.h"
26 #include "exec/cpu-defs.h"
27 #include "exec/cpu-interrupt.h"
28 #include "cpu-qom.h"
43 #define PPC_BIT_NR(bit) (63 - (bit))
45 #define PPC_BIT32_NR(bit) (31 - (bit))
48 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
49 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
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| H A D | cpu_init.c | 5 * Copyright (c) 2003-2007 Jocelyn Mayer
23 #include "disas/dis-asm.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
33 #include "qemu/qemu-print.h"
37 #include "hw/qdev-properties.h"
39 #include "mmu-book3s-v3.h"
47 #include "power8-pmu.h"
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| /openbmc/openbmc-build-scripts/scripts/ |
| H A D | build-unit-test-docker | 7 # default is openbmc/ubuntu-unit-test
9 # FORCE_DOCKER_BUILD: <optional, a non-zero value with force all Docker
35 # typing.Dict is used for type-hints.
61 def __init_subclass__(cls, **kwargs: Any) -> None:
75 # url [optional]: lambda function to create URL: (package, rev) -> url.
105 lambda pkg, rev: f"https://github.com/boostorg/{pkg}/releases/download/{pkg}-{rev}/{pkg}-{rev}-cmake.tar.gz"
111 f" -
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| /openbmc/openbmc/poky/documentation/dev-manual/ |
| H A D | new-recipe.rst | 1 .. SPDX-License-Identifier: CC-BY-SA-2.0-UK
9 how to create, write, and test a new recipe.
15 ":ref:`ref-manual/varlocality:recipes`" section of the Yocto Project
24 .. image:: figures/recipe-workflow.png
31 You can always write a recipe from scratch. However, there are three choices
34 - ``devtool add``: A command that assists in creating a recipe and an
37 - ``recipetool create``: A command provided by the Yocto Project that
40 - *Existing Recipes:* Location and modification of an existing recipe
46 ":ref:`dev-manual/new-recipe:recipe syntax`" section.
49 ----------------------------------------------
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| /openbmc/qemu/hw/s390x/ |
| H A D | s390-pci-bus.c | 10 * your option) any later version. See the COPYING file in the top-level
18 #include "hw/s390x/s390-pci-bus.h"
19 #include "hw/s390x/s390-pci-inst.h"
20 #include "hw/s390x/s390-pci-kvm.h"
21 #include "hw/s390x/s390-pci-vfio.h"
22 #include "hw/s390x/s390-virtio-ccw.h"
25 #include "hw/qdev-properties.h"
28 #include "qemu/error-report.h"
57 sei_cont = QTAILQ_FIRST(&s->pending_sei); in pci_chsc_sei_nt2_get_event()
59 QTAILQ_REMOVE(&s->pending_sei, sei_cont, link); in pci_chsc_sei_nt2_get_event()
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| /openbmc/u-boot/drivers/usb/gadget/ |
| H A D | ether.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * ether.c -- Ethernet gadget driver, with CDC and non-CDC options
5 * Copyright (C) 2003-2005,2008 David Brownell
6 * Copyright (C) 2003-2004 Robert Schwebel, Benedikt Spranger
29 #include <dm/uclass-internal.h>
30 #include <dm/device-internal.h>
41 * Ethernet gadget driver -- with CDC and non-CDC options
47 * this USB-IF standard as its open-systems interoperability solution;
51 * TLA-soup. "CDC ACM" (Abstract Control Model) is for modems, and a new
55 * implement a "minimalist" vendor-agnostic CDC core: same framing, but
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| /openbmc/qemu/linux-user/ |
| H A D | elfload.c | 1 /* This is the Linux kernel elf-loading code, ported into user space */
10 #include "user/tswap-target.h"
11 #include "user/page-protection.h"
12 #include "exec/page-protection.h"
13 #include "exec/mmap-lock.h"
14 #include "exec/translation-block.h"
16 #include "user/guest-base.h"
17 #include "user-internals.h"
18 #include "signal-common.h"
20 #include "user-mmap.h"
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| /openbmc/qemu/target/s390x/tcg/ |
| H A D | translate.c | 33 #include "s390x-internal.h"
34 #include "tcg/tcg-op.h"
35 #include "tcg/tcg-op-gvec.h"
37 #include "qemu/host-utils.h"
38 #include "exec/helper-proto.h"
39 #include "exec/helper-gen.h"
42 #include "exec/translation-block.h"
47 #include "exec/helper-info.c.inc"
146 * to be executed after base.pc_next - e.g. next sequential instruction
172 if (s->base.tb->flags & FLAG_MASK_32) { in pc_to_link_info()
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| /openbmc/qemu/disas/ |
| H A D | hppa.c | 1 /* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c.
6 University of Utah (pa-gdb-bugs@cs.utah.edu).
22 #include "disas/dis-asm.h"
24 /* HP PA-RISC SOM object file format: definitions internal to BFD.
29 University of Utah (pa-gdb-bugs@cs.utah.edu).
55 /* HP PA-RISC relocation types */
173 ((((bfd_signed_vma)(a)) << (BFD_ARCH_SIZE-22)) >> (BFD_ARCH_SIZE-22))
205 int signbit = (1 << (len - 1)); in sign_extend()
206 int mask = (signbit << 1) - 1; in sign_extend()
207 return ((x & mask) ^ signbit) - signbit; in sign_extend()
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