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/openbmc/linux/arch/powerpc/include/asm/
H A Dreg_booke.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * specification. Notice that while the IBM-40x series of CPUs
9 * Copyright 2009-2010 Freescale Semiconductor, Inc.
15 #include <asm/ppc-opcode.h>
19 #define MSR_UCLE_LG 26 /* User-mode cache lock enable */
26 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
62 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
63 #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
64 #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
65 #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
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/openbmc/linux/Documentation/virt/kvm/devices/
H A Dvm.rst1 .. SPDX-License-Identifier: GPL-2.0
9 struct kvm_device_attr as other devices, but targets VM-wide settings
21 -------------------------------------------
24 :Returns: -EBUSY if a vcpu is already defined, otherwise 0
26 Enables Collaborative Memory Management Assist (CMMA) for the virtual machine.
29 ----------------------------------------
32 :Returns: -EINVAL if CMMA was not enabled;
39 -----------------------------------------
41 :Parameters: in attr->addr the address for the new limit of guest memory
42 :Returns: -EFAULT if the given address is not accessible;
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/openbmc/phosphor-dbus-interfaces/yaml/com/ibm/ipzvpd/
H A DCP00.interface.yaml4 - name: RT
8 - name: VD
12 - name: PG
16 - name: MK
20 - name: PD_G
24 - name: PD_R
28 - name: SB
32 - name: PZ
36 - name: AW
39 AW keyword.Array Write-assist.
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/openbmc/linux/arch/x86/hyperv/
H A Dhv_init.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * X86 specific Hyper-V initialization code.
10 #define pr_fmt(fmt) "Hyper-V: " fmt
22 #include <asm/hyperv-tlfs.h>
62 return -EINVAL; in hyperv_init_ghcb()
75 return -ENOMEM; in hyperv_init_ghcb()
99 * For root partition we get the hypervisor provided VP assist in hv_cpu_init()
107 * The VP assist page is an "overlay" page (see Hyper-V TLFS's in hv_cpu_init()
109 * out to make sure we always write the EOI MSR in in hv_cpu_init()
118 * Hyper-V should never specify a VM that is a Confidential in hv_cpu_init()
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/openbmc/linux/tools/testing/selftests/kvm/include/x86_64/
H A Dhyperv.h1 /* SPDX-License-Identifier: GPL-2.0 */
245 * Issue a Hyper-V hypercall. Returns exception vector raised or 0, 'hv_status'
255 /* Note both the hypercall and the "asm safe" clobber r9-r11. */ in __hyperv_hypercall()
262 "a" (-EFAULT) in __hyperv_hypercall()
267 /* Issue a Hyper-V hypercall and assert that it succeeded. */
280 /* Write 'Fast' hypercall input 'data' to the first 'n_sse_regs' SSE regs */
296 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
308 /* Define virtual processor assist page structure. */
324 /* VP assist page */
329 /* Partition assist page */
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h19 #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
67 #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
70 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
87 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
140 #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
147 #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
181 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
182 #define DCWR_COPY 0 /* Copy-back */
183 #define DCWR_WRITE 1 /* Write-through */
211 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
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H A Dmmu.h28 unsigned long w:1; /* Write-thru cache mode */
37 #define PP_RWXX 0 /* Supervisor read/write, User none */
38 #define PP_RWRX 1 /* Supervisor read/write, User read */
39 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
47 unsigned long n:1; /* No-execute */
90 unsigned long w:1; /* Write-thru cache */
109 * Simulated two-level MMU. This structure is used by the kernel
133 pte **pmap; /* Two-level page-map structure */
170 #define BATL_PP_01 0x00000001 /* Read-only */
171 #define BATL_PP_10 0x00000002 /* Read-write */
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/openbmc/linux/Documentation/usb/
H A Draw-gadget.rst5 USB Raw Gadget is a gadget driver that gives userspace low-level control over
38 capabilities. This allows the user to write UDC-agnostic gadgets.
40 5. Raw Gadget has an ioctl-based interface instead of a filesystem-based
46 The user can interact with Raw Gadget by opening ``/dev/raw-gadget`` and
53 1. Create a Raw Gadget instance by opening ``/dev/raw-gadget``.
62 Nevertheless, Raw Gadget provides a UDC-agnostic way to write USB gadgets.
71 https://github.com/xairy/raw-gadget
76 Every Raw Gadget endpoint read/write ioctl submits a USB request and waits
77 until its completion. This is done deliberately to assist with coverage-guided
84 - Report more events (suspend, resume, etc.) through
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/openbmc/docs/designs/
H A Ddesign-template.md1 ---
3 # Document Guidelines - _Delete this section_
7 - Not all new features need a design document. If a feature can be contributed
11 - The focus of the document is to define the problem we need to solve and
12 analyse the trade-offs of different solutions. You should concentrate on
13 interactions between components, though analysing the trade-offs often
16 - Write this document as an [argumentative essay][argumentative-essay]. Good
19 [argumentative-essay]: https://www.grammarly.com/blog/argumentative-essay/
21 - This is not intended to be extensive documentation for a new feature.
23 - You should get your design reviewed and merged before writing your code.
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/openbmc/linux/arch/powerpc/include/asm/nohash/32/
H A Dpte-85xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 MMU Assist Register 3:
14 - PRESENT *must* be in the bottom two bits because swap PTEs use
19 /* Definitions for FSL Book-E Cores */
22 #define _PAGE_RW 0x00004 /* S: Write permission (SW) */
H A Dmmu-8xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * A write operation to these registers causes serialized access.
10 * During software tablewalk, the registers used perform mask/shift-add
43 * 4-15 => Not Used
81 * Also mark all subpages valid and write access.
91 #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
131 * when the MD_RPN is written. It is also provides the hardware assist
173 #define MODULES_VADDR (PAGE_OFFSET - SZ_256M)
193 /* Page size definitions, common between 32 and 64-bit
217 return -1; in shift_to_mmu_psize()
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/openbmc/qemu/target/hppa/
H A Dint_helper.c21 #include "qemu/main-loop.h"
24 #include "exec/helper-proto.h"
31 if (cpu->env.cr[CR_EIRR]) { in eval_interrupt()
39 * can write to this word to raise an external interrupt on the target CPU.
48 return cpu->env.cr[CR_EIRR]; in io_eir_read()
55 CPUHPPAState *env = &cpu->env; in io_eir_write()
60 if (hppa_is_pa20(env) && env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT) { in io_eir_write()
65 env->cr[CR_EIRR] |= 1ull << le_bit; in io_eir_write()
71 .write = io_eir_write,
86 env->cr[CR_EIRR] &= ~val; in HELPER()
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/openbmc/linux/Documentation/admin-guide/mm/
H A Didle_page_tracking.rst22 Currently, it consists of the only read-write file,
26 bitmap is represented by an array of 8-byte integers, and the page at PFN #i is
34 the page by writing to the file. A value written to the file is OR-ed with the
46 -EINVAL if you are not starting the read/write on an 8-byte boundary, or
47 if the size of the read/write is not a multiple of 8 bytes. Writing to
48 this file beyond max PFN will return -ENXIO.
66 The page-types tool in the tools/mm directory can be used to assist in this.
71 See Documentation/admin-guide/mm/pagemap.rst for more information about
86 - a userspace process reads or writes a page using a system call (e.g. read(2)
87 or write(2))
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
10 "Unit": "CPU-M-CF",
14 … Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is…
17 "Unit": "CPU-M-CF",
21 …ress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progr…
24 "Unit": "CPU-M-CF",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
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/openbmc/linux/arch/parisc/mm/
H A Dfault.c39 * parisc_acctyp(unsigned int inst) --
40 * Given a PA-RISC memory access instruction, determine if the
41 * instruction would perform a memory read or memory write
50 * VM_WRITE if write operation
81 * older PA-RISC platforms. The case where a block in parisc_acctyp()
89 * 01 Graphics flush write (IO space -> VM) in parisc_acctyp()
90 * 10 Graphics flush read (VM -> IO space) in parisc_acctyp()
91 * 11 Graphics flush read/write (VM <-> IO space) in parisc_acctyp()
100 * the above two instructions and is a write. in parisc_acctyp()
127 * not, but I want it committed to CVS so I don't lose it :-)
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/openbmc/linux/Documentation/arch/x86/
H A Dmds.rst7 --------
12 - Microarchitectural Store Buffer Data Sampling (MSBDS) (CVE-2018-12126)
13 - Microarchitectural Fill Buffer Data Sampling (MFBDS) (CVE-2018-12130)
14 - Microarchitectural Load Port Data Sampling (MLPDS) (CVE-2018-12127)
15 - Microarchitectural Data Sampling Uncacheable Memory (MDSUM) (CVE-2019-11091)
18 dependent load (store-to-load forwarding) as an optimization. The forward
21 buffers are partitioned between Hyper-Threads so cross thread forwarding is
28 operation and also write data to the cache. When the fill buffer is
32 Hyper-Threads so cross thread leakage is possible.
39 exploited eventually. Load ports are shared between Hyper-Threads so cross
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/openbmc/linux/arch/arc/include/asm/
H A Dsmp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
15 #define raw_smp_processor_id() (current_thread_info()->cpu)
39 * Takes @cpu and @hwirq to which the arch-common ISR is hooked up
44 * struct plat_smp_ops - SMP callbacks provided by platform to ARC SMP
49 * mach_desc->init_early()
79 * ARC700 doesn't support atomic Read-Modify-Write ops.
81 * The LLOCK/SCOND insns allow writing interrupt-hassle-free based atomic ops
82 * based on retry-if-irq-in-atomic (with hardware assist).
95 * asm/bitops.h -> linux/spinlock.h -> linux/preempt.h
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/openbmc/linux/drivers/s390/net/
H A Dlcs.h1 /* SPDX-License-Identifier: GPL-2.0 */
34 &((struct ccwgroup_device *)dev_get_drvdata(&cdev->dev))->dev);
112 #define LCS_FRAME_TYPE_AUTO -1
121 #define LCS_INVALID_PORT_NO -1
132 * LCS IP Assist declarations
149 LCS_BUF_STATE_READY, /* buffer is ready for read/write */
313 struct lcs_channel write; member
/openbmc/linux/include/linux/
H A Dpstore.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Persistent Storage - pstore.h
35 /* PPC64-specific partition types */
51 * struct pstore_record - details of a pstore record entry
54 * @id: per-type unique identifier for record
61 * kfree()d by the pstore core if non-NULL
89 * struct pstore_info - backend pstore driver structure
109 * @data: backend-private pointer passed back during callbacks
119 * Returns 0 on success, and non-zero on error.
128 * Returns 0 on success, and non-zero on error. (Though pstore will
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/openbmc/linux/drivers/clk/tegra/
H A Dclk-periph-gate.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
18 /* Macros to assist peripheral gate clock */
20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
22 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
24 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
27 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
29 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
31 #define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
44 if (!(gate->flags & TEGRA_PERIPH_NO_RESET)) in clk_periph_is_enabled()
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/openbmc/linux/arch/arc/kernel/
H A Dunaligned.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2012 Synopsys (www.synopsys.com)
6 * -Adapted (from .26 to .35)
7 * -original contribution by Tim.yao@amlogic.com
137 /* register write back */ in fixup_load()
138 if ((state->aa == 1) || (state->aa == 2)) { in fixup_load()
139 set_reg(state->wb_reg, state->src1 + state->src2, regs, cregs); in fixup_load()
141 if (state->aa == 2) in fixup_load()
142 state->src2 = 0; in fixup_load()
145 if (state->zz == 0) { in fixup_load()
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/openbmc/linux/Documentation/admin-guide/hw-vuln/
H A Dmds.rst1 MDS - Microarchitectural Data Sampling
9 -------------------
14 - Processors from AMD, Centaur and other non Intel vendors
16 - Older processor models, where the CPU family is < 6
18 - Some Atoms (Bonnell, Saltwell, Goldmont, GoldmontPlus)
20 - Intel processors which have the ARCH_CAP_MDS_NO bit set in the
31 ------------
36 CVE-2018-12126 MSBDS Microarchitectural Store Buffer Data Sampling
37 CVE-2018-12130 MFBDS Microarchitectural Fill Buffer Data Sampling
38 CVE-2018-12127 MLPDS Microarchitectural Load Port Data Sampling
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/openbmc/linux/arch/powerpc/kernel/
H A Dl2cr_6xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 Copyright © 1997-1998 by PowerLogix R & D, Inc.
9 - First public release, contributed by PowerLogix.
12 - Terry: Made sure code disabled interrupts before running. (Previously
14 - Terry: Updated for tentative G4 support. 4MB of memory is now flushed
16 - Terry: Updated for workaround to HID0[DPM] processor bug
20 - Terry: Added isync to correct for an errata.
23 - DanM: Finally added the 7450 patch I've had for the past
29 Please e-mail updates to this file to me, thanks!
36 #include <asm/feature-fixups.h>
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/openbmc/linux/Documentation/scsi/
H A DFlashPoint.rst1 .. SPDX-License-Identifier: GPL-2.0
17 FREMONT, CA, -- October 8, 1996 -- Mylex Corporation has expanded Linux
33 Linux is a freely-distributed implementation of UNIX for Intel x86, Sun
71 510/796-6100
78 BusLogic FlashPoint LT/BT-948 Upgrade Program
82 BusLogic FlashPoint LW/BT-958 Upgrade Program
99 customers to make sure the BT-946C/956C MultiMaster cards would still be
101 the FlashPoint would be able to upgrade to the BT-946C. While this helped
104 assist the people who initially purchased a FlashPoint for a supported
121 for third parties to write drivers for the FlashPoint. The only existing
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/openbmc/phosphor-power/
H A Dpmbus.hpp139 // Bits [7:5] - 000 - Reserved
140 // Bit 4 - 1 - Unit does not power up until commanded by the CONTROL pin and
142 // Bit 3 - 0 - Unit ignores the on/off portion of the OPERATION command from
144 // Bit 2 - 1 - Unit requires the CONTROL pin to be asserted to start the unit.
145 // Bit 1 - 0 - Polarity of the CONTROL pin. Active low (Pull pin low to start
147 // Bit 0 - 1 - Turn off the output and stop transferring energy to the output as
166 * This is a base class for PMBus to assist with unit testing via mocking.
190 * @param[in] bus - I2C bus
191 * @param[in] address - I2C address (as a 2-byte string, e.g. 0069)
221 * @param[in] path - path to the sysfs directory
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