include/asm/reg_booke.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
4  * specification.  Notice that while the IBM-40x series of CPUs
9  * Copyright 2009-2010 Freescale Semiconductor, Inc.
15 #include <asm/ppc-opcode.h>
19 #define MSR_UCLE_LG	26	/* User-mode cache lock enable */
26 #define MSR_CM_LG	31	/* Computation Mode (0=32-bit, 1=64-bit) */
62 #define SPRN_SPRG4W	0x114	/* Special Purpose Register General 4 Write */
63 #define SPRN_SPRG5W	0x115	/* Special Purpose Register General 5 Write */
64 #define SPRN_SPRG6W	0x116	/* Special Purpose Register General 6 Write */
65 #define SPRN_SPRG7W	0x117	/* Special Purpose Register General 7 Write */
75 #define SPRN_MAS8	0x155	/* MMU Assist Register 8 */
78 #define SPRN_MAS5_MAS6	0x15c	/* MMU Assist Register 5 || 6 */
79 #define SPRN_MAS8_MAS1	0x15d	/* MMU Assist Register 8 || 1 */
85 #define SPRN_MAS7_MAS3	0x174	/* MMU Assist Register 7 || 3 */
86 #define SPRN_MAS0_MAS1	0x175	/* MMU Assist Register 0 || 1 */
145 #define SPRN_MAS0	0x270	/* MMU Assist Register 0 */
146 #define SPRN_MAS1	0x271	/* MMU Assist Register 1 */
147 #define SPRN_MAS2	0x272	/* MMU Assist Register 2 */
148 #define SPRN_MAS3	0x273	/* MMU Assist Register 3 */
149 #define SPRN_MAS4	0x274	/* MMU Assist Register 4 */
150 #define SPRN_MAS5	0x153	/* MMU Assist Register 5 */
151 #define SPRN_MAS6	0x276	/* MMU Assist Register 6 */
161 #define SPRN_MAS7	0x3B0	/* MMU Assist Register 7 */
167 #define SPRN_DCWR	0x3BA	/* Data Cache Write-thru Register */
168 #define SPRN_SLER	0x3BB	/* Little-endian real mode */
223 #define	CCR1_DPC	0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
238 #define MCSR_DWB	0x10000000 /* Data Write PLB Error */
240 #define MCSR_ICP	0x04000000 /* I-Cache Parity Error */
241 #define MCSR_DCSP	0x02000000 /* D-Cache Search Parity Error */
242 #define MCSR_DCFP	0x01000000 /* D-Cache Flush Parity Error */
252 #define MCSR_ICPERR 	0x40000000UL /* I-Cache Parity Error */
255 #define MCSR_DCP_PERR 	0x20000000UL /* D-Cache Push Parity Error */
256 #define MCSR_DCPERR 	0x10000000UL /* D-Cache Parity Error */
259 #define MCSR_BUS_WAERR 	0x00000020UL /* Write Address Error */
262 #define MCSR_BUS_WBERR 	0x00000004UL /* Write Data Bus Error */
267 #define MCSR_DCPERR_MC	0x20000000UL /* D-Cache Parity Error */
269 #define MCSR_NMI	0x00100000UL /* Non-Maskable Interrupt */
293 #define HID1_MPXTT	0x00000400	/* MPX re-map transfer type */
314 #define DBSR_DAC1W	0x00040000	/* Data Addr Compare 1 Write Event */
316 #define DBSR_DAC2W	0x00010000	/* Data Addr Compare 2 Write Event */
333 #define DBSR_DAC1W	0x00800000	/* Data Address Compare 1 Write Event */
335 #define DBSR_DAC2W	0x00200000	/* Data Address Compare 2 Write Event */
339 #define ESR_MCI		0x80000000	/* Machine Check - Instruction */
340 #define ESR_IMCP	0x80000000	/* Instr. Machine Check - Protection */
341 #define ESR_IMCN	0x40000000	/* Instr. Machine Check - Non-config */
342 #define ESR_IMCB	0x20000000	/* Instr. Machine Check - Bus error */
343 #define ESR_IMCT	0x10000000	/* Instr. Machine Check - Timeout */
344 #define ESR_PIL		0x08000000	/* Program Exception - Illegal */
345 #define ESR_PPR		0x04000000	/* Program Exception - Privileged */
346 #define ESR_PTR		0x02000000	/* Program Exception - Trap */
348 #define ESR_DST		0x00800000	/* Storage Exception - Data miss */
349 #define ESR_DIZ		0x00400000	/* Storage Exception - Zone fault */
377 #define DBCR0_IA12	0x00200000	/* Instr Addr 1-2 range enable */
378 #define DBCR0_IA12X	0x00100000	/* Instr Addr 1-2 range eXclusive */
383 #define DBCR0_IA34	0x00020000	/* Instr Addr 3-4 range Enable */
384 #define DBCR0_IA34X	0x00010000	/* Instr Addr 3-4 range eXclusive */
385 #define DBCR0_IA12T	0x00008000	/* Instr Addr 1-2 range Toggle */
386 #define DBCR0_IA34T	0x00004000	/* Instr Addr 3-4 range Toggle */
389 #define dbcr_iac_range(task)	((task)->thread.debug.dbcr0)
392 #define DBCR_IAC12MODE	(DBCR0_IA12 | DBCR0_IA12X)	/* IAC 1-2 Mode Bits */
395 #define DBCR_IAC34MODE	(DBCR0_IA34 | DBCR0_IA34X)	/* IAC 3-4 Mode Bits */
400 #define DBCR1_DAC1W	0x20000000	/* DAC1 Write Debug Event */
401 #define DBCR1_DAC2W	0x10000000	/* DAC2 Write Debug Event */
403 #define dbcr_dac(task)	((task)->thread.debug.dbcr1)
441 #define DBCR0_DAC1W	0x00040000	/* DAC 1 Write enable */
443 #define DBCR0_DAC2W	0x00010000	/* DAC 2 Write enable */
449 #define dbcr_dac(task)	((task)->thread.debug.dbcr0)
466 #define DBCR1_IAC12M	0x00800000	/* Instr Addr 1-2 range enable */
467 #define DBCR1_IAC12MX	0x00C00000	/* Instr Addr 1-2 range eXclusive */
468 #define DBCR1_IAC12AT	0x00010000	/* Instr Addr 1-2 range Toggle */
479 #define DBCR1_IAC34M	0x00000080	/* Instr Addr 3-4 range enable */
480 #define DBCR1_IAC34MX	0x000000C0	/* Instr Addr 3-4 range eXclusive */
481 #define DBCR1_IAC34AT	0x00000001	/* Instr Addr 3-4 range Toggle */
483 #define dbcr_iac_range(task)	((task)->thread.debug.dbcr1)
486 #define DBCR_IAC12MODE	DBCR1_IAC12MX	/* IAC 1-2 Mode Bits */
489 #define DBCR_IAC34MODE	DBCR1_IAC34MX	/* IAC 3-4 Mode Bits */
496 #define DBCR2_DAC12M	0x00800000	/* DAC 1-2 range enable */
497 #define DBCR2_DAC12MM	0x00400000	/* DAC 1-2 Mask mode*/
498 #define DBCR2_DAC12MX	0x00C00000	/* DAC 1-2 range eXclusive */
499 #define DBCR2_DAC12MODE	0x00C00000	/* DAC 1-2 Mode Bits */
500 #define DBCR2_DAC12A	0x00200000	/* DAC 1-2 Asynchronous */
572 #define DCWR_COPY	0		/* Copy-back */
573 #define DCWR_WRITE	1		/* Write-through */
594 #define L1CSR2_DCWS	0x40000000	/* Data Cache write shadow */