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/openbmc/qemu/docs/system/arm/
H A Dxlnx-versal-virt.rst1 Xilinx Versal Virt (``xlnx-versal-virt``)
4 Xilinx Versal is a family of heterogeneous multi-core SoCs
10 https://www.xilinx.com/products/silicon-devices/acap/versal.html
12 The family of Versal SoCs share a single architecture but come in
16 The Xilinx Versal Virt board in QEMU is a model of a virtual board
17 (does not exist in reality) with a virtual Versal SoC without I/O
28 - An RTC (Versal built-in)
45 edit it to include suitable entries describing the Versal DDR memory ranges.
77 $ qemu-system-aarch64 -M xlnx-versal-virt -m 2G \
90 $ qemu-system-aarch64 -M xlnx-versal-virt -m 2G \
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/openbmc/linux/Documentation/devicetree/bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml26 - description: For implementations complying for Versal.
27 const: xlnx,versal-firmware
45 $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
57 $ref: /schemas/clock/xlnx,versal-clk.yaml#
58 description: The clock controller is a hardware block of Xilinx versal
83 versal-firmware {
84 compatible = "xlnx,versal-firmware";
88 compatible = "xlnx,versal-fpga";
97 compatible = "xlnx,versal-clk";
/openbmc/qemu/include/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.h2 * Header file for the Xilinx Versal's PMC IOU SLCR
27 * This is a model of Xilinx Versal's PMC I/O Peripheral Control and Status
28 * module documented in Versal's Technical Reference manual [1] and the Versal
33 * [1] Versal ACAP Technical Reference Manual,
34 * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
36 * [2] Versal ACAP Register Reference,
37 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PMC_IOP_SLCR-Module
60 #define TYPE_XILINX_VERSAL_PMC_IOU_SLCR "xlnx.versal-pmc-iou-slcr"
H A Dxlnx-versal-cfu.h11 * [1] Versal ACAP Technical Reference Manual,
12 * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
14 * [2] Versal ACAP Register Reference,
15 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/CFU_CSR-Module
25 #define TYPE_XLNX_VERSAL_CFU_APB "xlnx-versal-cfu-apb"
28 #define TYPE_XLNX_VERSAL_CFU_FDRO "xlnx-versal-cfu-fdro"
31 #define TYPE_XLNX_VERSAL_CFU_SFR "xlnx-versal-cfu-sfr"
/openbmc/linux/Documentation/devicetree/bindings/fpga/
H A Dxlnx,versal-fpga.yaml4 $id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
7 title: Xilinx Versal FPGA driver.
13 Device Tree Versal FPGA bindings for the Versal SoC, controlled
20 - xlnx,versal-fpga
30 compatible = "xlnx,versal-fpga";
/openbmc/qemu/include/hw/ssi/
H A Dxlnx-versal-ospi.h2 * Header file for the Xilinx Versal's OSPI controller
27 * This is a model of Xilinx Versal's Octal SPI flash memory controller
28 * documented in Versal's Technical Reference manual [1] and the Versal ACAP
33 * [1] Versal ACAP Technical Reference Manual,
34 * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
36 * [2] Versal ACAP Register Reference,
37 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/OSPI-Module
60 #define TYPE_XILINX_VERSAL_OSPI "xlnx.versal-ospi"
/openbmc/qemu/include/hw/arm/
H A Dxlnx-versal.h2 * Model of the Xilinx Versal
26 #include "hw/misc/xlnx-versal-xramc.h"
28 #include "hw/nvram/xlnx-versal-efuse.h"
29 #include "hw/ssi/xlnx-versal-ospi.h"
31 #include "hw/misc/xlnx-versal-crl.h"
32 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
33 #include "hw/misc/xlnx-versal-trng.h"
34 #include "hw/net/xlnx-versal-canfd.h"
35 #include "hw/misc/xlnx-versal-cfu.h"
36 #include "hw/misc/xlnx-versal-cframe-reg.h"
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dxlnx,versal-clk.yaml4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
7 title: Xilinx Versal clock controller
13 The clock controller is a hardware block of Xilinx versal clock tree. It
21 - xlnx,versal-clk
25 - xlnx,versal-net-clk
26 - const: xlnx,versal-clk
55 - xlnx,versal-clk
112 compatible = "xlnx,versal-clk";
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dxlnx,zynqmp-reset.yaml7 title: Zynq UltraScale+ MPSoC and Versal reset
13 The Zynq UltraScale+ MPSoC and Versal has several different resets.
27 For list of all valid reset indices for Versal
28 <dt-bindings/reset/xlnx-versal-resets.h>
34 - xlnx,versal-reset
35 - xlnx,versal-net-reset
/openbmc/qemu/hw/arm/
H A Dxlnx-versal.c2 * Xilinx Versal SoC model.
24 #include "hw/arm/xlnx-versal.h"
36 static void versal_create_apu_cpus(Versal *s) in versal_create_apu_cpus()
67 static void versal_create_apu_gic(Versal *s, qemu_irq *pic) in versal_create_apu_gic()
140 static void versal_create_rpu_cpus(Versal *s) in versal_create_rpu_cpus()
169 static void versal_create_uarts(Versal *s, qemu_irq *pic) in versal_create_uarts()
194 static void versal_create_canfds(Versal *s, qemu_irq *pic) in versal_create_canfds()
226 static void versal_create_usbs(Versal *s, qemu_irq *pic) in versal_create_usbs()
251 static void versal_create_gems(Versal *s, qemu_irq *pic) in versal_create_gems()
291 static void versal_create_admas(Versal *s, qemu_irq *pic) in versal_create_admas()
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/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dxlnx,versal-wwdt.yaml4 $id: http://devicetree.org/schemas/watchdog/xlnx,versal-wwdt.yaml#
7 title: Xilinx Versal window watchdog timer controller
13 Versal watchdog intellectual property uses window watchdog mode.
27 - xlnx,versal-wwdt
45 compatible = "xlnx,versal-wwdt";
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dxilinx-versal-cpm.yaml4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
7 title: CPM Host Controller device tree for Xilinx Versal SoCs
18 - xlnx,versal-cpm-host-1.00
19 - xlnx,versal-cpm5-host
75 versal {
79 compatible = "xlnx,versal-cpm-host-1.00";
106 compatible = "xlnx,versal-cpm5-host";
/openbmc/u-boot/arch/arm/dts/
H A Dversal-mini-emmc1.dts3 * dts file for Xilinx Versal Mini eMMC1 Configuration
14 compatible = "xlnx,versal";
17 model = "Xilinx Versal MINI eMMC1";
39 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
H A Dversal-mini-emmc0.dts3 * dts file for Xilinx Versal Mini eMMC0 Configuration
14 compatible = "xlnx,versal";
17 model = "Xilinx Versal MINI eMMC0";
39 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
H A Dversal-mini.dts3 * dts file for Xilinx Versal Mini Configuration
13 model = "Versal MINI";
14 compatible = "xlnx,versal";
/openbmc/qemu/hw/usb/
H A Dxlnx-usb-subsystem.c59 object_initialize_child(obj, "versal.dwc3", &s->dwc3, in versal_usb2_init()
61 object_initialize_child(obj, "versal.usb2-ctrl", &s->usb2Ctrl, in versal_usb2_init()
63 memory_region_init_alias(&s->dwc3_mr, obj, "versal.dwc3_alias", in versal_usb2_init()
65 memory_region_init_alias(&s->usb2Ctrl_mr, obj, "versal.usb2Ctrl_alias", in versal_usb2_init()
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml29 - xlnx,versal-8.9a
30 - xlnx,versal-net-emmc
61 - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
66 - const: xlnx,versal-net-emmc # Versal Net eMMC PHY
238 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
/openbmc/qemu/hw/misc/
H A Dmeson.build93 'xlnx-versal-crl.c',
94 'xlnx-versal-xramc.c',
95 'xlnx-versal-pmc-iou-slcr.c',
96 'xlnx-versal-cfu.c',
98 'xlnx-versal-cframe-reg.c',
101 'xlnx-versal-trng.c',
/openbmc/linux/drivers/fpga/
H A Dversal-fpga.c57 mgr = devm_fpga_mgr_register(dev, "Xilinx Versal FPGA Manager", in versal_fpga_probe()
63 { .compatible = "xlnx,versal-fpga", },
79 MODULE_DESCRIPTION("Xilinx Versal FPGA Manager");
/openbmc/u-boot/board/xilinx/versal/
H A DMAINTAINERS4 F: arch/arm/dts/versal*
5 F: board/xilinx/versal/
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dxlnx,versal-net-cdx.yaml4 $id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
39 const: xlnx,versal-net-cdx
73 compatible = "xlnx,versal-net-cdx";
/openbmc/u-boot/arch/arm/mach-versal/
H A DKconfig7 default "versal"
14 default "versal"
/openbmc/u-boot/configs/
H A Dxilinx_versal_mini_emmc0_defconfig15 CONFIG_SYS_PROMPT="Versal> "
45 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc0"
H A Dxilinx_versal_mini_emmc1_defconfig15 CONFIG_SYS_PROMPT="Versal> "
45 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-emmc1"
H A Dxilinx_versal_mini_defconfig17 CONFIG_SYS_PROMPT="Versal> "
47 CONFIG_DEFAULT_DEVICE_TREE="versal-mini"

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