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e3beca3a |
| 17-Oct-2018 |
Tom Rini <trini@konsulko.com> |
Merge tag 'signed-efi-2018.11' of git://github.com/agraf/u-boot Patch queue for efi - 2018-10-17 A few bug fixes for the 2018.11 release: - Fix block seeking on 32bit
Merge tag 'signed-efi-2018.11' of git://github.com/agraf/u-boot Patch queue for efi - 2018-10-17 A few bug fixes for the 2018.11 release: - Fix block seeking on 32bit - Fix execution with DEBUG set - Fix a few Coverity found bugs - Fix warnings Heinrich Schuchardt (13): efi_loader: fix relocation on x86_64 efi_loader: correct signature of GetPosition, SetPosition efi_loader: execute efi_save_gd() first efi_loader: efi_allocate_pool(EFI_ALLOCATE_ANY_PAGES, ...) efi_loader: error handling in read_console() efi_loader: return type efi_console_register() efi_loader: superfluous statement in is_dir() efi_loader: memory leak in efi_set_variable() efi_loader: remove lcd.h from efi_net.c arm: do not include efi_loader.h twice efi_loader: fix typo in efi_boottime.c efi_selftest: creating new handle in controller test efi_loader: efi_dp_get_next_instance() superfluous statement Tom Rini (2): efi_loader: Fix warning in efi_load_image() fs: fat: Fix warning in normalize_longname()
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d0423c44 |
| 16-Oct-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-microblaze Xilinx changes for v2018.11-rc2-v2 FPGA: - Fix SPL fpga loading from FIT ARM64: - Fix gic accesses in EL2/EL1 Xil
Merge git://git.denx.de/u-boot-microblaze Xilinx changes for v2018.11-rc2-v2 FPGA: - Fix SPL fpga loading from FIT ARM64: - Fix gic accesses in EL2/EL1 Xilinx: - Add dlc20 board support - Add Versal board support - Sync defconfigs - Enable MP via Kconfig - Add missing efuse node - Enable CDC for zcu100 cmd: - Fix kgdb Kconfig dependency
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ec48b6c9 |
| 22-Aug-2018 |
Michal Simek <michal.simek@xilinx.com> |
arm64: versal: Add support for new Xilinx Versal ACAPs Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAP
arm64: versal: Add support for new Xilinx Versal ACAPs Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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