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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,wcd9335.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9335 Codec is a standalone Hi-Fi audio codec IC with in-built
27 clock-names:
29 - const: mclk
30 - const: slimbus
35 interrupt-names:
37 - const: intr1
[all …]
H A Dqcom,wsa8840.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
18 - $ref: dai-common.yaml#
27 powerdown-gpios:
31 '#sound-dai-cells':
34 vdd-1p8-supply: true
35 vdd-io-supply: true
[all …]
H A Dcirrus,cs42l43.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
21 - $ref: dai-common.yaml#
26 - cirrus,cs42l43
31 vdd-p-supply:
35 vdd-a-supply:
39 vdd-d-supply:
43 vdd-io-supply:
[all …]
H A Dqcom,pm8916-wcd-analog-codec.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,pm8916-wcd-analog-codec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
17 const: qcom,pm8916-wcd-analog-codec
25 interrupt-names:
27 - const: cdc_spk_cnp_int
28 - const: cdc_spk_clip_int
29 - const: cdc_spk_ocp_int
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm8450-hdk.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
10 #include <dt-bindings/iio/qcom,spmi-adc7-pm8350b.h>
11 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
12 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
13 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
24 compatible = "qcom,sm8450-hdk", "qcom,sm8450";
25 chassis-type = "embedded";
[all …]
H A Dsm8250-mtp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/sound/qcom,q6afe.h>
10 #include <dt-bindings/sound/qcom,q6asm.h>
11 #include <dt-bindings/gpio/gpio.h>
20 compatible = "qcom,sm8250-mtp", "qcom,sm8250";
21 chassis-type = "handset";
27 wcd938x: audio-codec {
28 compatible = "qcom,wcd9380-codec";
[all …]
H A Dsdm845-mtp.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
17 compatible = "qcom,sdm845-mtp", "qcom,sdm845";
18 chassis-type = "handset";
25 stdout-path = "serial0:115200n8";
28 vph_pwr: vph-pwr-regulator {
29 compatible = "regulator-fixed";
30 regulator-name = "vph_pwr";
31 regulator-min-microvolt = <3700000>;
[all …]
H A Dsc8280xp-lenovo-thinkpad-x13s.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
11 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
12 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
13 #include <dt-bindings/input/gpio-keys.h>
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/leds/common.h>
16 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
[all …]
H A Dsm8550-mtp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
20 compatible = "qcom,sm8550-mtp", "qcom,sm8550";
21 chassis-type = "handset";
27 wcd938x: audio-codec {
28 compatible = "qcom,wcd9385-codec";
30 pinctrl-names = "default";
31 pinctrl-0 = <&wcd_default>;
33 qcom,micbias1-microvolt = <1800000>;
[all …]
H A Dqrb5165-rb5.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
10 #include <dt-bindings/sound/qcom,q6afe.h>
11 #include <dt-bindings/sound/qcom,q6asm.h>
19 compatible = "qcom,qrb5165-rb5", "qcom,sm8250";
20 qcom,msm-id = <455 0x20001>;
21 qcom,board-id = <11 3>;
29 stdout-path = "serial0:115200n8";
[all …]
H A Dsm8550-qrd.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
21 compatible = "qcom,sm8550-qrd", "qcom,sm8550";
22 chassis-type = "handset";
28 wcd938x: audio-codec {
29 compatible = "qcom,wcd9385-codec";
31 pinctrl-names = "default";
32 pinctrl-0 = <&wcd_default>;
[all …]
/openbmc/u-boot/drivers/power/
H A DKconfig19 ---help---
27 ---help---
36 ---help---
45 ---help---
54 ---help---
62 ---help---
69 ---help---
80 ---help---
83 generic 3.3V IO voltage for external devices like the lcd-panal and
85 save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/accel/
H A Dkionix,kx022a.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
13 KX022A is a 3-axis accelerometer supporting +/- 2G, 4G, 8G and 16G ranges,
14 output data-rates from 0.78Hz to 1600Hz and a hardware-fifo buffering.
28 interrupt-names:
31 - enum: [INT1, INT2]
32 - const: INT2
34 vdd-supply: true
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmicrel,ks8851.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
15 - micrel,ks8851 # SPI bus option
16 - micrel,ks8851-mll # Parallel bus option
24 - description: SPI or Parallel bus hardware address
25 - description: Parallel bus command mode address
27 reset-gpios:
32 vdd-supply:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dsamsung,exynos-adc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/samsung,exynos-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - samsung,exynos-adc-v1 # Exynos5250
16 - samsung,exynos-adc-v2
17 - samsung,exynos3250-adc
18 - samsung,exynos4212-adc # Exynos4212 and Exynos4412
19 - samsung,exynos7-adc
[all …]
H A Dst,stm32-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp15xx-dhcor-io1v8.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
10 vdd_io: regulator-buck-io {
11 compatible = "regulator-fixed";
12 regulator-name = "buck-io";
13 regulator-min-microvolt = <1800000>;
14 regulator-max-microvolt = <1800000>;
15 regulator-always-on;
16 regulator-boot-on;
17 vin-supply = <&vdd>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/light/
H A Dsharp,gp2ap002.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
20 - sharp,gp2ap002a00f
21 - sharp,gp2ap002s00f
30 vdd-supply:
31 description: VDD power supply a phandle to a regulator
33 vio-supply:
36 io-channels:
[all …]
H A Dcapella,cm3605.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
12 - Kevin Tsai <ktsai@capellamicro.com>
26 aset-gpios:
39 io-channels:
45 io-channel-names:
48 vdd-supply: true
50 capella,aset-resistance-ohms:
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra210-p2894.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/mfd/max77620.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
16 stdout-path = "serial0:115200n8";
26 pinctrl-names = "boot";
27 pinctrl-0 = <&state_boot>;
35 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
36 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
[all …]
H A Dtegra210-p2597.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
23 avdd-dsi-csi-supply = <&vdd_dsi_csi>;
33 avdd-io-hdmi-dp-supply = <&avdd_1v05>;
34 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
35 hdmi-supply = <&vdd_hdmi>;
37 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
38 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/nfc/
H A Dti,trf7970a.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Mark Greer <mgreer@animalcreek.com>
17 autosuspend-delay:
22 clock-frequency:
27 en2-rf-quirk:
35 irq-status-read-quirk:
43 ti,enable-gpios:
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dmotorola-cpcap-mapphone.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 interrupt-parent = <&gpio1>;
12 interrupt-controller;
13 #interrupt-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 spi-max-frequency = <9600000>;
17 spi-cs-high;
18 spi-cpol;
19 spi-cpha;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/input/
H A Dgoodix,gt7375p.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Douglas Anderson <dianders@chromium.org>
14 This touchscreen uses the i2c-hid protocol but has some non-standard
18 - $ref: /schemas/input/touchscreen/touchscreen.yaml#
23 - const: goodix,gt7375p
24 - items:
25 - const: goodix,gt7986u
26 - const: goodix,gt7375p
[all …]
/openbmc/linux/drivers/gpu/drm/bridge/
H A Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/media-bus-format.h>
35 /* DSI D-PHY Layer Registers */
51 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
72 #define CLS_PRE 0x0180 /* Digital Counter inside of PHY IO */
73 #define D0S_PRE 0x0184 /* Digital Counter inside of PHY IO */
74 #define D1S_PRE 0x0188 /* Digital Counter inside of PHY IO */
75 #define D2S_PRE 0x018C /* Digital Counter inside of PHY IO */
76 #define D3S_PRE 0x0190 /* Digital Counter inside of PHY IO */
77 #define CLS_PREP 0x01A0 /* Digital Counter inside of PHY IO */
[all …]

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