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/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dxilinx-xadc.txt4 as the UltraScale/UltraScale+ System Monitor.
14 The Xilinx System Monitor is an ADC that is found in the UltraScale and
15 UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
29 UltraScale and UltraScale+ System Monitor.
/openbmc/linux/arch/microblaze/kernel/cpu/
H A Dcpuinfo.c79 {"UltraScale Virtex", 0x13},
80 {"UltraScale Kintex", 0x14},
81 {"UltraScale+ Zynq", 0x15},
82 {"UltraScale+ Virtex", 0x16},
83 {"UltraScale+ Kintex", 0x17},
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dxlnx,zynqmp-reset.yaml7 title: Zynq UltraScale+ MPSoC and Versal reset
13 The Zynq UltraScale+ MPSoC and Versal has several different resets.
24 For list of all valid reset indices for Zynq UltraScale+ MPSoC
/openbmc/linux/drivers/clk/zynqmp/
H A DKconfig4 bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers"
8 Support for the Zynqmp Ultrascale clock controller.
H A DMakefile2 # Zynq Ultrascale+ MPSoC clock specific Makefile
H A Dclk-gate-zynqmp.c3 * Zynq UltraScale+ MPSoC clock controller
H A Dclk-mux-zynqmp.c3 * Zynq UltraScale+ MPSoC mux
H A Dclkc.c3 * Zynq UltraScale+ MPSoC clock controller
675 pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n", in zynqmp_register_clocks()
/openbmc/linux/Documentation/devicetree/bindings/fpga/
H A Dxlnx,zynqmp-pcap-fpga.yaml7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
13 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
/openbmc/linux/Documentation/devicetree/bindings/display/xlnx/
H A Dxlnx,zynqmp-dpsub.yaml10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
40 Please refer to "Zynq UltraScale+ Device Technical Reference Manual"
41 (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
/openbmc/linux/drivers/iio/adc/
H A Dxilinx-xadc.h74 XADC_TYPE_US, /* UltraScale and UltraScale+ */
H A DKconfig1424 UltraScale/UltraScale+ System Management Wizard.
1431 UltraScale and UltraScale+ FPGAs.
1441 Say yes here to have support for the Xilinx AMS for Ultrascale/Ultrascale+
1445 The driver supports Voltage and Temperature monitoring on Xilinx Ultrascale
H A Dxilinx-xadc-core.c101 /* UltraScale */
587 * Values below are for UltraScale+ (SYSMONE4) using internal reference.
588 * See https://docs.xilinx.com/v/u/en-US/ug580-ultrascale-sysmon
777 * UltraScale, but as per reality setting the power-down bit for the in xadc_power_adc_b()
803 /* UltraScale has only one ADC and supports only continuous mode */ in xadc_get_seq_mode()
1134 /* UltraScale */
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-zynqmp-qspi.yaml7 title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun50i_h6.h52 * Rockchip RK3328 SoC, NXP i.MX7 SoCs and Xilinx Zynq UltraScale+ SoCs.
63 * - Zynq UltraScale+ MPSoC Register Reference (UG1087)
132 * The following register information is based on Zynq UltraScale+
/openbmc/linux/Documentation/misc-devices/
H A Dxilinx_sdfec.rst10 This driver supports SD-FEC Integrated Block for Zynq |Ultrascale+ (TM)| RFSoCs.
12 .. |Ultrascale+ (TM)| unicode:: Ultrascale+ U+2122
/openbmc/u-boot/drivers/fpga/
H A DKconfig57 on Xilinx Zynq UltraScale+ (ZynqMP) device.
/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Dxlnx,zynqmp-rtc.yaml7 title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
/openbmc/linux/Documentation/devicetree/bindings/nvmem/
H A Dxlnx,zynqmp-nvmem.txt2 = Zynq UltraScale+ MPSoC nvmem firmware driver binding =
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dcdns,uart.yaml19 - description: UART controller for Zynq Ultrascale+ MPSoC
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-driver-zynqmp-fpga9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
/openbmc/linux/Documentation/devicetree/bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dxilinx.yaml13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Dxlnx,zynqmp-ipi-mailbox.yaml11 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI

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