| /openbmc/linux/drivers/input/touchscreen/ |
| H A D | imx6ul_tsc.c | 57 /* TSC registers */
68 /* TSC configuration registers field define */
100 * TSC module need ADC to get the measure value. So
101 * before config TSC, we should initialize ADC module.
103 static int imx6ul_adc_init(struct imx6ul_tsc *tsc) in imx6ul_adc_init() argument
111 reinit_completion(&tsc->completion); in imx6ul_adc_init()
113 adc_cfg = readl(tsc->adc_regs + REG_ADC_CFG); in imx6ul_adc_init()
118 if (tsc->average_enable) { in imx6ul_adc_init()
120 adc_cfg |= (tsc->average_select) << ADC_AVGS_SHIFT; in imx6ul_adc_init()
123 writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG); in imx6ul_adc_init()
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| H A D | tps6507x-ts.c | 50 static int tps6507x_read_u8(struct tps6507x_ts *tsc, u8 reg, u8 *data) in tps6507x_read_u8() argument
52 return tsc->mfd->read_dev(tsc->mfd, reg, 1, data); in tps6507x_read_u8()
55 static int tps6507x_write_u8(struct tps6507x_ts *tsc, u8 reg, u8 data) in tps6507x_write_u8() argument
57 return tsc->mfd->write_dev(tsc->mfd, reg, 1, &data); in tps6507x_write_u8()
60 static s32 tps6507x_adc_conversion(struct tps6507x_ts *tsc, in tps6507x_adc_conversion() argument
69 ret = tps6507x_write_u8(tsc, TPS6507X_REG_TSCMODE, tsc_mode); in tps6507x_adc_conversion()
71 dev_err(tsc->dev, "TSC mode read failed\n"); in tps6507x_adc_conversion()
77 ret = tps6507x_write_u8(tsc, TPS6507X_REG_ADCONFIG, in tps6507x_adc_conversion()
80 dev_err(tsc->dev, "ADC config write failed\n"); in tps6507x_adc_conversion()
85 ret = tps6507x_read_u8(tsc, TPS6507X_REG_ADCONFIG, in tps6507x_adc_conversion()
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| H A D | lpc32xx_ts.c | 71 static void lpc32xx_fifo_clear(struct lpc32xx_tsc *tsc) in lpc32xx_fifo_clear() argument
73 while (!(tsc_readl(tsc, LPC32XX_TSC_STAT) & in lpc32xx_fifo_clear()
75 tsc_readl(tsc, LPC32XX_TSC_FIFO); in lpc32xx_fifo_clear()
82 struct lpc32xx_tsc *tsc = dev_id; in lpc32xx_ts_interrupt() local
83 struct input_dev *input = tsc->dev; in lpc32xx_ts_interrupt()
85 tmp = tsc_readl(tsc, LPC32XX_TSC_STAT); in lpc32xx_ts_interrupt()
89 lpc32xx_fifo_clear(tsc); in lpc32xx_ts_interrupt()
100 !(tsc_readl(tsc, LPC32XX_TSC_STAT) & in lpc32xx_ts_interrupt()
102 tmp = tsc_readl(tsc, LPC32XX_TSC_FIFO); in lpc32xx_ts_interrupt()
126 static void lpc32xx_stop_tsc(struct lpc32xx_tsc *tsc) in lpc32xx_stop_tsc() argument
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| H A D | tsc2007_iio.c | 42 struct tsc2007 *tsc = iio->ts; in tsc2007_read_raw() local
52 mutex_lock(&tsc->mlock); in tsc2007_read_raw()
56 *val = tsc2007_xfer(tsc, READ_X); in tsc2007_read_raw()
59 *val = tsc2007_xfer(tsc, READ_Y); in tsc2007_read_raw()
62 *val = tsc2007_xfer(tsc, READ_Z1); in tsc2007_read_raw()
65 *val = tsc2007_xfer(tsc, READ_Z2); in tsc2007_read_raw()
68 *val = tsc2007_xfer(tsc, (ADC_ON_12BIT | TSC2007_MEASURE_AUX)); in tsc2007_read_raw()
73 tc.x = tsc2007_xfer(tsc, READ_X); in tsc2007_read_raw()
74 tc.z1 = tsc2007_xfer(tsc, READ_Z1); in tsc2007_read_raw()
75 tc.z2 = tsc2007_xfer(tsc, READ_Z2); in tsc2007_read_raw()
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| H A D | cy8ctmg110_ts.c | 61 static int cy8ctmg110_write_regs(struct cy8ctmg110 *tsc, unsigned char reg, in cy8ctmg110_write_regs() argument
64 struct i2c_client *client = tsc->client; in cy8ctmg110_write_regs()
82 static int cy8ctmg110_read_regs(struct cy8ctmg110 *tsc, in cy8ctmg110_read_regs() argument
85 struct i2c_client *client = tsc->client; in cy8ctmg110_read_regs()
110 static int cy8ctmg110_touch_pos(struct cy8ctmg110 *tsc) in cy8ctmg110_touch_pos() argument
112 struct input_dev *input = tsc->input; in cy8ctmg110_touch_pos()
118 if (cy8ctmg110_read_regs(tsc, reg_p, 9, CY8CTMG110_TOUCH_X1) != 0) in cy8ctmg110_touch_pos()
156 struct cy8ctmg110 *tsc = dev_id; in cy8ctmg110_irq_thread() local
158 cy8ctmg110_touch_pos(tsc); in cy8ctmg110_irq_thread()
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| /openbmc/linux/drivers/thermal/ |
| H A D | rcar_gen3_thermal.c | 99 static inline u32 rcar_gen3_thermal_read(struct rcar_gen3_thermal_tsc *tsc, in rcar_gen3_thermal_read() argument
102 return ioread32(tsc->base + reg); in rcar_gen3_thermal_read()
105 static inline void rcar_gen3_thermal_write(struct rcar_gen3_thermal_tsc *tsc, in rcar_gen3_thermal_write() argument
108 iowrite32(data, tsc->base + reg); in rcar_gen3_thermal_write()
140 struct rcar_gen3_thermal_tsc *tsc, in rcar_gen3_thermal_calc_coefs() argument
149 tsc->tj_t = (FIXPT_INT((priv->ptat[1] - priv->ptat[2]) * (ths_tj_1 - TJ_3)) in rcar_gen3_thermal_calc_coefs()
152 tsc->coef.a1 = FIXPT_DIV(FIXPT_INT(tsc->thcode[1] - tsc->thcode[2]), in rcar_gen3_thermal_calc_coefs()
153 tsc->tj_t - FIXPT_INT(TJ_3)); in rcar_gen3_thermal_calc_coefs()
154 tsc->coef.b1 = FIXPT_INT(tsc->thcode[2]) - tsc->coef.a1 * TJ_3; in rcar_gen3_thermal_calc_coefs()
156 tsc->coef.a2 = FIXPT_DIV(FIXPT_INT(tsc->thcode[1] - tsc->thcode[0]), in rcar_gen3_thermal_calc_coefs()
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| /openbmc/linux/arch/x86/kernel/ |
| H A D | tsc_sync.c | 3 * check TSC synchronization.
7 * We check whether all boot CPUs have their TSC's synchronized,
8 * print a warning if not and turn off the TSC clock-source.
24 #include <asm/tsc.h>
37 * TSC's on different sockets may be reset asynchronously.
38 * This may cause the TSC ADJUST value on socket 0 to be NOT 0.
47 pr_info("tsc: Marking TSC async resets true due to %s\n", reason); in mark_tsc_async_resets()
58 /* Skip unnecessary error messages if TSC already unstable */ in tsc_verify_tsc_adjust()
76 pr_warn(FW_BUG "TSC ADJUST differs: CPU%u %lld --> %lld. Restoring\n", in tsc_verify_tsc_adjust()
134 * the TSC is in sync with the already running cpus. in tsc_sanitize_first_cpu()
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| H A D | tsc.c | 33 unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
42 * TSC can be unstable due to cpufreq or due to unsynced TSCs
241 * Fall back to jiffies if there's no TSC available: in native_sched_clock()
242 * ( But note that we still use it if the TSC is marked in native_sched_clock()
254 * Generate a sched_clock if you already have a TSC value.
256 u64 native_sched_clock_from_tsc(u64 tsc) in native_sched_clock_from_tsc() argument
258 return cycles_2_ns(tsc); in native_sched_clock_from_tsc()
302 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
329 pr_alert("%s: Overriding earlier tsc=watchdog with tsc=nowatchdog\n", in tsc_setup()
337 pr_alert("%s: tsc=watchdog overridden by earlier tsc=nowatchdog\n", in tsc_setup()
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| /openbmc/linux/tools/perf/arch/x86/util/ |
| H A D | tsc.c | 8 #include "../../../util/tsc.h"
21 * Derive the TSC frequency in Hz from the /proc/cpuinfo, for example:
36 pr_err("Failed to read /proc/cpuinfo for TSC frequency"); in cpuinfo_tsc_freq()
51 pr_err("Failed to find TSC frequency in /proc/cpuinfo"); in cpuinfo_tsc_freq()
62 static double tsc; in arch_get_tsc_freq() local
66 return tsc; in arch_get_tsc_freq()
78 tsc = cpuinfo_tsc_freq(); in arch_get_tsc_freq()
79 return tsc; in arch_get_tsc_freq()
83 /* TSC frequency is not enumerated */ in arch_get_tsc_freq()
85 tsc = cpuinfo_tsc_freq(); in arch_get_tsc_freq()
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| /openbmc/linux/Documentation/virt/kvm/x86/ |
| H A D | timekeeping.rst | 14 3) TSC Hardware
37 First we discuss the basic hardware devices available. TSC and the related
324 3. TSC Hardware
327 The TSC or time stamp counter is relatively simple in theory; it counts
332 The TSC is represented internally as a 64-bit MSR which can be read with the
334 limitations made it possible to write the TSC, but generally on old hardware it
339 write the TSC MSR is not an architectural guarantee.
341 The TSC is accessible from CPL-0 and conditionally, for CPL > 0 software by
342 means of the CR4.TSD bit, which when enabled, disables CPL > 0 TSC access.
345 atomically not just the TSC, but an indicator which corresponds to the
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| /openbmc/linux/drivers/thermal/tegra/ |
| H A D | tegra30-tsensor.c | 163 const struct tegra_tsensor_channel *tsc = thermal_zone_device_priv(tz); in tegra_tsensor_get_temp() local
164 const struct tegra_tsensor *ts = tsc->ts; in tegra_tsensor_get_temp()
172 err = readl_relaxed_poll_timeout(tsc->regs + TSENSOR_SENSOR0_STATUS0, val, in tegra_tsensor_get_temp()
177 dev_err_once(ts->dev, "ch%u: counter invalid\n", tsc->id); in tegra_tsensor_get_temp()
181 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_TS_STATUS1); in tegra_tsensor_get_temp()
190 dev_err_once(ts->dev, "ch%u: counter overflow\n", tsc->id); in tegra_tsensor_get_temp()
221 const struct tegra_tsensor_channel *tsc = thermal_zone_device_priv(tz); in tegra_tsensor_set_trips() local
222 const struct tegra_tsensor *ts = tsc->ts; in tegra_tsensor_set_trips()
232 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1); in tegra_tsensor_set_trips()
237 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1); in tegra_tsensor_set_trips()
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| /openbmc/u-boot/drivers/timer/ |
| H A D | tsc_timer.c | 5 * TSC calibration codes are adapted from Linux kernel
6 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
33 * Determine TSC frequency via CPUID, else return 0.
138 * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
143 * TSC, so we have no other choice than to trust it.
145 * Returns the TSC frequency in MHz or 0 if HW does not provide it.
182 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */ in cpu_mhz_from_msr()
184 debug("TSC runs at %lu MHz\n", res); in cpu_mhz_from_msr()
205 * see the same MSB (and overhead like doing a single TSC
221 * use the TSC value at the transitions to calculate a pretty
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| /openbmc/linux/Documentation/virt/hyperv/ |
| H A D | clocks.rst | 26 also provides access to the virtualized TSC via the RDTSC and
27 related instructions. These TSC instructions do not trap to
29 Hyper-V performs TSC calibration, and provides the TSC frequency
31 in Linux reads this MSR to get the frequency, so it skips TSC
42 value, the guest reads the TSC and then applies the scale and offset
45 to a host with a different TSC frequency, Hyper-V adjusts the
50 support for TSC frequency scaling to enable live migration of VMs
51 across Hyper-V hosts where the TSC frequency may be different.
53 available, it prefers to use Linux's standard TSC-based clocksource.
62 space code performs the same algorithm of reading the TSC and
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| /openbmc/linux/tools/testing/selftests/kvm/x86_64/ |
| H A D | vmx_nested_tsc_scaling_test.c | 7 * This test case verifies that nested TSC scaling behaves as expected when
32 * This function checks whether the "actual" TSC frequency of a guest matches
33 * its expected frequency. In order to account for delays in taking the TSC
46 "TSC freq is expected to be between %"PRIu64" and %"PRIu64 in compare_tsc_freq()
50 "TSC freq is expected to be between %"PRIu64" and %"PRIu64 in compare_tsc_freq()
60 * Reading the TSC twice with about a second's difference should give in check_tsc_freq()
61 * us an approximation of the TSC frequency from the guest's in check_tsc_freq()
96 /* enable TSC offsetting and TSC scaling for L2 */ in l1_guest_code()
130 !strncmp(buf, "tsc", sizeof(buf)); in system_has_stable_tsc()
169 printf("real TSC frequency is around: %"PRIu64"\n", l0_tsc_freq); in main()
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| H A D | hyperv_clock.c | 88 /* Compare TSC page clocksource with HV_X64_MSR_TIME_REF_COUNT */ in check_tsc_msr_tsc_page()
114 /* Set up TSC page is disabled state, check that it's clean */ in guest_main()
122 /* Set up TSC page is enabled state */ in guest_main()
133 /* Call KVM_SET_CLOCK from userspace, check that TSC page was updated */ in guest_main()
136 /* Sanity check TSC page timestamp, it should be close to 0 */ in guest_main()
144 * Enable Re-enlightenment and check that TSC page stays constant across in guest_main()
160 * Disable re-enlightenment and TSC page, check that KVM doesn't update in guest_main()
182 TEST_ASSERT(tsc_freq > 0, "TSC frequency must be nonzero"); in host_check_tsc_msr_rdtsc()
202 "Elapsed time does not match (MSR=%ld, TSC=%ld)", in host_check_tsc_msr_rdtsc()
221 "TSC page has to be page aligned\n"); in main()
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| H A D | vmx_preemption_timer_test.c | 140 * tsc deadlines so that host can verify they are as expected in l1_guest_code()
211 pr_info("Stage %d: L1 PT expiry TSC (%lu) , L1 TSC deadline (%lu)\n", in main()
214 pr_info("Stage %d: L2 PT expiry TSC (%lu) , L2 TSC deadline (%lu)\n", in main()
218 "Stage %d: L1 PT expiry TSC (%lu) < L1 TSC deadline (%lu)", in main()
222 "Stage %d: L2 PT expiry TSC (%lu) > L2 TSC deadline (%lu)", in main()
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| /openbmc/linux/tools/perf/tests/ |
| H A D | perf-time-to-tsc.c | 20 #include "tsc.h"
26 * Except x86_64/i386 and Arm64, other archs don't support TSC in perf. Just
61 * test__perf_time_to_tsc - test converting perf time to TSC.
64 * to and from TSC is consistent with the order of events. If the test passes
65 * %0 is returned, otherwise %-1 is returned. If TSC conversion is not
184 pr_debug("1st event perf time %"PRIu64" tsc %"PRIu64"\n", in test__perf_time_to_tsc()
186 pr_debug("rdtsc time %"PRIu64" tsc %"PRIu64"\n", in test__perf_time_to_tsc()
188 pr_debug("2nd event perf time %"PRIu64" tsc %"PRIu64"\n", in test__perf_time_to_tsc()
209 TEST_CASE_REASON("TSC support", tsc_is_supported,
211 TEST_CASE_REASON("Perf time to TSC", perf_time_to_tsc,
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| /openbmc/linux/tools/power/cpupower/utils/idle_monitor/ |
| H A D | mperf_monitor.c | 67 * 1) calculated after measurements if we know TSC ticks at mperf/P0 frequency
83 static int mperf_get_tsc(unsigned long long *tsc) in mperf_get_tsc() argument
87 ret = read_msr(base_cpu, MSR_TSC, tsc); in mperf_get_tsc()
89 dprint("Reading TSC MSR failed, returning %llu\n", *tsc); in mperf_get_tsc()
174 dprint("%s: TSC Ref - mperf_diff: %llu, tsc_diff: %llu\n", in mperf_get_count_percent()
208 /* Calculate max_freq from TSC count */ in mperf_get_count_freq()
217 (max_freq_mode == MAX_FREQ_TSC_REF) ? "TSC calculated" : "sysfs read"); in mperf_get_count_freq()
256 * we use TSC counter if it reliably ticks at P0/mperf frequency.
260 * on older Intel HW without invariant TSC feature.
261 * Or on AMD machines where TSC does not tick at P0 (do not exist yet, but
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| H A D | nhm_idle.c | 27 enum intel_nhm_id { C3 = 0, C6, PC3, PC6, TSC = 0xFFFF }; enumerator
89 case TSC: in nhm_get_count()
131 nhm_get_count(TSC, &tsc_at_measure_start, base_cpu); in nhm_start()
139 nhm_get_count(TSC, &dbg, base_cpu); in nhm_start()
140 dprint("TSC diff: %llu\n", dbg - tsc_at_measure_start); in nhm_start()
150 nhm_get_count(TSC, &tsc_at_measure_end, base_cpu); in nhm_stop()
158 nhm_get_count(TSC, &dbg, base_cpu); in nhm_stop()
159 dprint("TSC diff: %llu\n", dbg - tsc_at_measure_end); in nhm_stop()
212 .overflow_s = 922000000 /* 922337203 seconds TSC overflow
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| /openbmc/linux/Documentation/devicetree/bindings/input/touchscreen/ |
| H A D | lpc32xx-tsc.txt | 1 * NXP LPC32xx SoC Touchscreen Controller (TSC)
4 - compatible: must be "nxp,lpc3220-tsc"
7 - interrupts: The TSC/ADC interrupt
11 tsc@40048000 {
12 compatible = "nxp,lpc3220-tsc";
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| H A D | imx6ul_tsc.txt | 4 - compatible: must be "fsl,imx6ul-tsc".
8 - clock-names; must be "tsc" and "adc".
24 tsc: tsc@2040000 {
25 compatible = "fsl,imx6ul-tsc";
31 clock-names = "tsc", "adc";
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| /openbmc/linux/drivers/clocksource/ |
| H A D | hyperv_timer.c | 386 * the other that uses the TSC reference page feature as defined in the
388 * Hyper-V and 32-bit x86. The TSC reference page version is preferred.
417 * subsection Refererence Counter, guarantees that the TSC and MSR in read_hv_clock_tsc()
419 * to the MSR in case the TSC page indicates unavailability. in read_hv_clock_tsc()
442 /* Disable the TSC page */ in suspend_hv_clock_tsc()
453 /* Re-enable the TSC page */ in resume_hv_clock_tsc()
463 * used to calculate time for hv tsc page based sched_clock, to account for
537 * If Hyper-V offers TSC_INVARIANT, then the virtualized TSC correctly in hv_init_tsc_clocksource()
540 * Hyper-V Reference TSC rating, causing the generic TSC to be used. in hv_init_tsc_clocksource()
542 * TSC will be preferred over the virtualized ARM64 arch counter. in hv_init_tsc_clocksource()
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| /openbmc/linux/drivers/cpufreq/ |
| H A D | amd-pstate-trace.h | 33 u64 tsc,
45 tsc,
58 __field(unsigned long long, tsc)
71 __entry->tsc = tsc;
77 …TP_printk("amd_min_perf=%lu amd_des_perf=%lu amd_max_perf=%lu freq=%llu mperf=%llu aperf=%llu tsc=…
84 (unsigned long long)__entry->tsc,
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| /openbmc/qemu/include/hw/xen/interface/arch-x86/ |
| H A D | cpuid.h | 61 * Sub-leaf 0: EAX: bit 0: emulated tsc
62 * bit 1: host tsc is known to be reliable
66 * ECX: guest tsc frequency in kHz
67 * EDX: guest tsc incarnation (migration count)
68 * Sub-leaf 1: EAX: tsc offset low part
69 * EBX: tsc offset high part
70 * ECX: multiplicator for tsc->ns conversion
71 * EDX: shift amount for tsc->ns conversion
72 * Sub-leaf 2: EAX: host tsc frequency in kHz
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| /openbmc/linux/arch/x86/include/asm/xen/ |
| H A D | cpuid.h | 78 * Sub-leaf 0: EAX: bit 0: emulated tsc
79 * bit 1: host tsc is known to be reliable
83 * ECX: guest tsc frequency in kHz
84 * EDX: guest tsc incarnation (migration count)
85 * Sub-leaf 1: EAX: tsc offset low part
86 * EBX: tsc offset high part
87 * ECX: multiplicator for tsc->ns conversion
88 * EDX: shift amount for tsc->ns conversion
89 * Sub-leaf 2: EAX: host tsc frequency in kHz
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