5  * TSC calibration codes are adapted from Linux kernel
6  * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
33  * Determine TSC frequency via CPUID, else return 0.
138  * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
143  * TSC, so we have no other choice than to trust it.
145  * Returns the TSC frequency in MHz or 0 if HW does not provide it.
182 	/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */  in cpu_mhz_from_msr()
184 	debug("TSC runs at %lu MHz\n", res);  in cpu_mhz_from_msr()
205  *    see the same MSB (and overhead like doing a single TSC
221  * use the TSC value at the transitions to calculate a pretty
222  * good value for the TSC frequencty.
235 	u64 tsc = 0, prev_tsc = 0;  in pit_expect_msb()  local
240 		prev_tsc = tsc;  in pit_expect_msb()
241 		tsc = rdtsc();  in pit_expect_msb()
244 	*tscp = tsc;  in pit_expect_msb()
248 	 * will be based on the error terms on the TSC values.  in pit_expect_msb()
265 	u64 tsc, delta;  in quick_pit_calibrate()  local
294 	if (pit_expect_msb(0xff, &tsc, &d1)) {  in quick_pit_calibrate()
302 			delta -= tsc;  in quick_pit_calibrate()
308 			 * all TSC reads were stable wrt the PIT.  in quick_pit_calibrate()
318 	debug("Fast TSC calibration failed\n");  in quick_pit_calibrate()
328 	 * any odd delays anywhere, and the TSC reads are  in quick_pit_calibrate()
337 	debug("Fast TSC calibration using PIT\n");  in quick_pit_calibrate()
341 /* Get the speed of the TSC timer in MHz */
442 			panic("TSC frequency is ZERO");  in tsc_timer_probe()
453 	 * When TSC timer is used as the early timer, be warned that the timer  in timer_early_get_rate()
472 	{ .compatible = "x86,tsc-timer", },