| /openbmc/u-boot/drivers/usb/host/ |
| H A D | Kconfig | 12 ---help---
21 Say Y or if your system has a Dual Role SuperSpeed
22 USB controller based on the DesignWare USB3 IP Core.
26 depends on DM_USB
30 USB controller based on the DesignWare USB3 IP Core.
35 depends on ARCH_MVEBU
38 Choose this option to add support for USB 3.0 driver on mvebu
43 bool "Support for PCI-based xHCI USB controller"
44 depends on DM_USB
47 Enables support for the PCI-based xHCI controller.
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| /openbmc/qemu/docs/system/arm/ |
| H A D | sx1.rst | 1 Siemens SX1 (``sx1``, ``sx1-v1``)
7 - Texas Instruments OMAP310 System-on-chip (ARM925T core)
9 - ROM and RAM memories (ROM firmware image can be loaded with
10 -pflash) V1 1 Flash of 16MB and 1 Flash of 8MB V2 1 Flash of 32MB
12 - On-chip LCD controller
14 - On-chip Real Time Clock
16 - Secure Digital card connected to OMAP MMC/SD host
18 - Three on-chip UARTs
|
| H A D | stm32.rst | 1 STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olimex-stm32-h405``, ``stm32vl…
4 The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
7 .. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
9 The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
10 based on this chip :
12 - ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcontroller
14 The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
15 based on this chip :
17 - ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller
19 The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L4
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| H A D | nrf.rst | 4 The `Nordic nRF`_ chips are a family of ARM-based System-on-Chip that
5 are designed to be used for low-power and short-range wireless solutions.
11 The following machines are based on this chip :
13 - ``microbit`` BBC micro:bit board with nRF51822 SoC
19 -----------------
21 * ARM Cortex-M0 (ARMv6-M)
31 ---------------
34 * Real-Time Clock (RTC) controller
42 ------------
44 The Micro:bit machine can be started using the ``-device`` option to load a
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| H A D | nuvoton.rst | 1 Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj`…
4 The `Nuvoton iBMC`_ chips are a family of Arm-based SoCs that are
7 NPCM8XX series. NPCM7XX series feature one or two Arm Cortex-A9 CPU cores,
8 while NPCM8XX feature 4 Arm Cortex-A35 CPU cores. Both series contain a
12 .. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
14 The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise
15 segment. The following machines are based on this chip :
17 - ``npcm750-evb`` Nuvoton NPCM750 Evaluation board
19 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
20 Hyperscale applications. The following machines are based on this chip :
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| H A D | xlnx-versal-virt.rst | 1 Xilinx Versal Virt (``xlnx-versal-virt``)
4 Xilinx Versal is a family of heterogeneous multi-core SoCs
5 (System on Chip) that combine traditional hardened CPUs and I/O
6 peripherals in a Processing System (PS) with runtime programmable
10 https://www.xilinx.com/products/silicon-devices/acap/versal.html
22 - 2 ACPUs (ARM Cortex-A72)
26 - Interrupt controller (ARM GICv3)
27 - 2 UARTs (ARM PL011)
28 - An RTC (Versal built-in)
29 - 2 GEMs (Cadence MACB Ethernet MACs)
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| /openbmc/qemu/docs/system/ |
| H A D | target-m68k.rst | 1 .. _ColdFire-System-emulator:
3 ColdFire System emulator
4 ------------------------
6 Use the executable ``qemu-system-m68k`` to simulate a ColdFire machine.
11 - MCF5208 ColdFire V2 Microprocessor (ISA A+ with EMAC).
13 - Three Two on-chip UARTs.
15 - Fast Ethernet Controller (FEC)
19 - MCF5206 ColdFire V2 Microprocessor.
21 - Two on-chip UARTs.
|
| H A D | target-rx.rst | 1 .. _RX-System-emulator:
3 RX System emulator
4 --------------------
6 Use the executable ``qemu-system-rx`` to simulate RX target (GDB simulator).
9 - R5F562N8 MCU
11 - On-chip memory (ROM 512KB, RAM 96KB)
12 - Interrupt Control Unit (ICUa)
13 - 8Bit Timer x 1CH (TMR0,1)
14 - Compare Match Timer x 2CH (CMT0,1)
15 - Serial Communication Interface x 1CH (SCI0)
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| /openbmc/openpower-hw-diags/util/ |
| H A D | pdbg.hpp | 14 class Chip;
23 /** Chip target types. */
46 /** @return The target associated with the given chip. */
47 pdbg_target* getTrgt(const libhei::Chip& i_chip);
55 /** @return A string representing the given chip's devtree path. */
56 const char* getPath(const libhei::Chip& i_chip);
61 /** @return The absolute position of the given chip. */
62 uint32_t getChipPos(const libhei::Chip& i_chip);
64 /** @return The unit position of a target within a chip. */
70 /** @return The target type of the given chip. */
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| /openbmc/docs/designs/ |
| H A D | power-systems-memory-preserving-reboot.md | 1 # Memory preserving reboot and System Dump extraction flow on POWER Systems
9 On POWER based servers, a hypervisor firmware manages and allocates resources to
10 the logical partitions running on the server. If this hypervisor encounters an
14 required for debugging the fault. Some hypervisors on the POWER based systems
15 don't have access to a non-volatile storage to store this content after a
16 failure. A warm reboot with preserving the main memory is needed on the POWER
18 explains the high-level flow of warm reboot and extraction of the resulting dump
23 - **Boot**: The process of initializing hardware components in a computer system
24 and loading the operating system.
26 - **Hostboot**: The firmware runs on the host processors and performs all
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| /openbmc/u-boot/doc/device-tree-bindings/spi/ |
| H A D | spi-bus.txt | 4 and a set of child nodes for each SPI slave on the bus. For this
5 discussion, it is assumed that the system's SPI controller is in
10 - #address-cells - number of cells required to define a chip select
11 address on the SPI bus.
12 - #size-cells - should be zero.
13 - compatible - name of SPI bus controller following generic names
15 - cs-gpios - (optional) gpios chip select.
19 assigning chip select numbers. Since SPI chip select configuration is
20 flexible and non-standardized, it is left out of this binding with the
22 chip selects. Individual drivers can define additional properties to
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| /openbmc/phosphor-mrw-tools/docs/ |
| H A D | mrw-xml-requirements.md | 3 This document describes the data requirements that OpenBMC has on the machine
5 [Serverwiz2](https://www.github.com/open-power/serverwiz). The requirements in
11 ## System Inventory
13 The system inventory can be generated from the MRW XML. The inventory typically
14 contains all FRUs (field replaceable units), along with a few non-FRU entities,
15 like the BMC chip and processor cores.
19 - Set the `FRU_NAME` attribute of that target.
28 modeled in the MRW XML. For a system built with parts that already have existing
31 determined, depending on the part.
33 The following sections list the system dependent information that the device
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| /openbmc/phosphor-mrw-tools/ |
| H A D | Inventory.pm | 14 #Chips that are modeled as modules (card-chip together)
18 #for a system. The hash elements are:
49 for my $target (sort keys %{$targetObj->getAllTargets()}) {
53 if (!$targetObj->isBadAttribute($target, "TYPE")) {
54 $type = $targetObj->getAttribute($target, "TYPE");
57 if (!$targetObj->isBadAttribute($target, "RU_TYPE")) {
58 $ruType = $targetObj->getAttribute($target, "RU_TYPE");
73 #is a card-chip instance that plugs into a connector on the
74 #backplane/processor card. Since we already include the chip target
78 #For example, we'll already have .../module-0/proc-0 so we don't
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| H A D | Util.pm | 10 #Returns the BMC target for a system.
16 for my $target (keys %{$targetObj->getAllTargets()}) {
17 if ($targetObj->getType($target) eq "BMC") {
26 #Returns an array of child units based on their Target Type.
29 # param[in] $chip = The chip target to find the units on
32 my ($targetObj, $unitTargetType, $chip) = @_;
35 my @children = $targetObj->getAllTargetChildren($chip);
38 if ($targetObj->getTargetType($child) eq $unitTargetType) {
46 #Returns size of child units based on their Type.
49 # param[in] $chip = The chip target to find the units on
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| /openbmc/witherspoon-pfault-analysis/org/open_power/Witherspoon/ |
| H A D | Fault.errors.yaml | 1 - name: PowerSupplyInputFault
6 - name: PowerSupplyShouldBeOn
7 description: The power supply indicated that it is not on when it should be.
9 - name: PowerSupplyOutputOvercurrent
12 - name: PowerSupplyOutputOvervoltage
15 - name: PowerSupplyFanFault
18 - name: PowerSupplyTemperatureFault
21 - name: Shutdown
24 - name: PowerOnFailure
25 description: System power failed to turn on
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| /openbmc/u-boot/arch/x86/ |
| H A D | Kconfig | 2 depends on X86
8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
19 For now, 32-bit mode is recommended, as 64-bit is still
23 bool "32-bit"
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| /openbmc/u-boot/drivers/mtd/spi/ |
| H A D | Kconfig | 5 depends on DM && DM_SPI
11 supported by U-Boot. The uclass interface is defined in
20 depends on SANDBOX && DM_SPI_FLASH
26 stored in a file on the host filesystem.
30 depends on SPI
41 depends on SPI_FLASH || DM_SPI_FLASH
46 flash is present on the system.
49 int "SPI Flash default Chip-select"
50 depends on SPI_FLASH || DM_SPI_FLASH
53 The default chip select may be provided by the platform
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| /openbmc/u-boot/board/freescale/ls1021aiot/ |
| H A D | README | 2 --------
3 The LS1021A-IOT is a Freescale reference board that hosts
7 -------------------------
8 - DDR Controller
9 - Supports 1GB un-buffered DDR3L SDRAM discrete
10 devices(32-bit bus) with 4 bit ECC
11 - DDR power supplies 1.35V to all devices with
13 - Soldered DDR chip
14 - Supprot one fixed speed
15 - Ethernet
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| /openbmc/qemu/hw/ppc/ |
| H A D | pnv.c | 4 * Copyright (c) 2016-2024, IBM Corporation.
6 * SPDX-License-Identifier: GPL-2.0-or-later
28 #include "system/qtest.h"
29 #include "system/system.h"
30 #include "system/numa.h"
31 #include "system/reset.h"
32 #include "system/runstate.h"
33 #include "system/cpus.h"
34 #include "system/device_tree.h"
35 #include "system/hw_accel.h"
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| /openbmc/u-boot/drivers/misc/ |
| H A D | Kconfig | 9 depends on DM
18 depends on ARCH_ASPEED
24 depends on ARCH_ASPEED
30 depends on ARCH_ASPEED
32 Support the FSI master present in the ASPEED system on chips.
36 depends on MISC
39 details on the "Embedded Peripherals IP User Guide" of Altera.
43 depends on MISC
46 CryptoAuthentication module found for example on the Turris Omnia
50 bool "Rockchip e-fuse support"
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| /openbmc/docs/architecture/code-update/ |
| H A D | emmc-storage-design.md | 7 Created: 2019-06-20
18 based on AST2400 and AST2500, but there is no design for managed NAND.
22 - Security: Ability to enforce read-only, verification of official/signed images
25 - Updatable: Ensure that the filesystem design allows for an effective and
28 - Simplicity: Make the system easy to understand, so that it is easy to develop,
31 - Code reuse: Try to use something that already exists instead of re-inventing
36 - The eMMC image layout and characteristics are specified in a meta layer. This
41 - Code update: Support two versions on flash. This allows a known good image to
44 - GPT partitioning for the eMMC User Data Area: This is chosen over dynamic
48 - Initramfs: An initramfs is needed to run sgdisk on first boot to move the
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| /openbmc/qemu/docs/specs/ |
| H A D | fsi.rst | 8 FSI is a point-to-point two wire interface which is capable of supporting
22 "engines" that drive accesses on buses internal and external to the POWER
23 chip. Examples include the SBEFIFO and I2C masters. The engines hang off of
33 driving CFAM engine accesses into the POWER chip. At the hardware level
34 FSI is a bit-based protocol supporting synchronous and DMA-driven accesses
37 4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER
40 MMIO-mapping of the CFAM address straight onto a sub-region of the OPB
43 5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the
58 As for FSI, its symbols and wire-protocol are not modelled at all. This is not
60 space onto the OPB address space - the models follow this directly and map the
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| /openbmc/u-boot/board/freescale/t4rdb/ |
| H A D | cpld.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
7 * This file provides support for the ngPIXIS, a board-specific FPGA used on
12 * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
15 u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */
16 u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */
17 u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */
18 u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */
19 u8 hw_ver; /* 0x04 - PCBA Version Register */
20 u8 software_on; /* 0x05 - Override Physical Switch Enable Register */
21 u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */
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| /openbmc/openpower-proc-control/procedures/phal/ |
| H A D | thread_stopall.cpp | 15 #include <phosphor-logging/log.hpp>
26 * @brief Stop instruction executions on all functional threads in the
28 * This procedure is used to stop all threads in the system in
30 * chip-op with ignore hardware error mode. Since this function
31 * is used in power-off/error path, ignore the internal error now.
35 // CMD details based on SBE spec, used for logging purpose in threadStopAll()
82 "threadStopAll failed({}) on proc({})", in threadStopAll()
93 // SRC6 : [0:15] chip position in threadStopAll()
106 // SBE is not ready to accept chip-ops, in threadStopAll()
109 std::format("threadStopAll: Skipping ({}) on proc({})", in threadStopAll()
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| /openbmc/u-boot/drivers/reset/ |
| H A D | Kconfig | 5 depends on DM && OF_CONTROL
9 reset controller hardware module within the chip. In U-Boot, reset
17 depends on DM_MAILBOX && SANDBOX
25 depends on ARCH_STI
27 Support for reset controllers on STMicroelectronics STiH407 family SoCs.
28 Say Y if you want to control reset signals provided by system config
33 depends on STM32 || ARCH_STM32MP
35 Support for reset controllers on STMicroelectronics STM32 family SoCs.
39 bool "Enable Tegra CAR-based reset driver"
40 depends on TEGRA_CAR
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