| /openbmc/linux/Documentation/devicetree/bindings/power/supply/ |
| H A D | dlg,da9150-fuel-gauge.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/supply/dlg,da9150-fuel-gauge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Dialog Semiconductor DA9150 Fuel-Gauge Power Supply
10 - Sebastian Reichel <sre@kernel.org>
13 - $ref: power-supply.yaml#
17 const: dlg,da9150-fuel-gauge
19 dlg,update-interval:
21 description: Interval time (milliseconds) between battery level checks.
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| H A D | maxim,max17040.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
13 - $ref: power-supply.yaml#
18 - maxim,max17040
19 - maxim,max17041
20 - maxim,max17043
21 - maxim,max17044
22 - maxim,max17048
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| /openbmc/linux/drivers/power/supply/ |
| H A D | da9150-fg.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DA9150 Fuel-Gauge Driver
22 #include <linux/devm-helpers.h>
84 int soc; member
99 da9150_read_qif(fg->da9150, read_addr, size, buf); in da9150_fg_read_attr()
121 da9150_write_qif(fg->da9150, write_addr, size, buf); in da9150_fg_write_attr()
130 mutex_lock(&fg->io_lock); in da9150_fg_read_sync_start()
150 dev_err(fg->dev, "Failed to perform QIF read sync!\n"); in da9150_fg_read_sync_start()
159 mutex_unlock(&fg->io_lock); in da9150_fg_read_sync_end()
181 mutex_lock(&fg->io_lock); in da9150_fg_write_attr_sync()
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| H A D | max17040_battery.c | 1 // SPDX-License-Identifier: GPL-2.0
4 // fuel-gauge systems for lithium-ion (Li+) batteries
147 int soc; member
158 return regmap_write(chip->regmap, MAX17040_CMD, chip->data.reset_val); in max17040_reset()
161 static int max17040_set_low_soc_alert(struct max17040_chip *chip, u32 level) in max17040_set_low_soc_alert() argument
163 level = 32 - level * (chip->quirk_double_soc ? 2 : 1); in max17040_set_low_soc_alert()
164 return regmap_update_bits(chip->regmap, MAX17040_CONFIG, in max17040_set_low_soc_alert()
165 MAX17040_ATHD_MASK, level); in max17040_set_low_soc_alert()
170 return regmap_update_bits(chip->regmap, MAX17040_CONFIG, in max17040_set_soc_alert()
176 u16 mask = chip->data.rcomp_bytes == 2 ? in max17040_set_rcomp()
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| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | cm_common.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 * cm_ll_data: function pointers to SoC-specific implementations of
41 * cm_split_idlest_reg - split CM_IDLEST reg addr into its components
48 * via the @prcm_inst and @idlest_reg_id. Returns -EINVAL upon error,
56 if (!cm_ll_data->split_idlest_reg) { in cm_split_idlest_reg()
57 WARN_ONCE(1, "cm: %s: no low-level function defined\n", in cm_split_idlest_reg()
59 return -EINVAL; in cm_split_idlest_reg()
62 ret = cm_ll_data->split_idlest_reg(idlest_reg, prcm_inst, in cm_split_idlest_reg()
64 *prcm_inst -= cm_base.offset; in cm_split_idlest_reg()
69 * omap_cm_wait_module_ready - wait for a module to leave idle or standby
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| H A D | prm_common.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Tero Kristo <t-kristo@ti.com>
24 #include <linux/clk-provider.h>
27 #include "soc.h"
45 * actual amount of memory needed for the SoC
70 * prm_ll_data: function pointers to SoC-specific implementations of
86 for (i = 0; i < prcm_irq_setup->nr_regs; i++) { in omap_prcm_events_filter_priority()
88 events[i] & prcm_irq_setup->priority_mask[i]; in omap_prcm_events_filter_priority()
99 * done by the SoC specific individual handlers.
107 int nr_irq = prcm_irq_setup->nr_regs * 32; in omap_prcm_irq_handler()
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| /openbmc/linux/Documentation/process/ |
| H A D | maintainer-soc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 SoC Subsystem
8 --------
10 The SoC subsystem is a place of aggregation for SoC-specific code.
13 * devicetrees for 32- & 64-bit ARM and RISC-V
14 * 32-bit ARM board files (arch/arm/mach*)
15 * 32- & 64-bit ARM defconfigs
16 * SoC-specific drivers across architectures, in particular for 32- & 64-bit
17 ARM, RISC-V and Loongarch
19 These "SoC-specific drivers" do not include clock, GPIO etc drivers that have
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| /openbmc/linux/Documentation/devicetree/bindings/soc/qcom/ |
| H A D | qcom,rpmh-rsc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
21 active/wake resource requests. Multiple such DRVs can exist in a SoC and can
27 ACTIVE - Triggered by Linux
28 SLEEP - Triggered by F/W
29 WAKE - Triggered by F/W
30 CONTROL - Triggered by F/W
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | sprd,pinctrl.txt | 8 pad driving level, system control select and so on ("domain pad
9 driving level": One pin can output 3.0v or 1.8v, depending on the
13 have several systems (AP/CP/CM4) on one SoC.).
16 of them, so we can not make every Spreadtrum-special configuration
32 Now we have 4 systems for sleep mode on SC9860 SoC: AP system,
35 - input-enable
36 - input-disable
37 - output-high
38 - output-low
39 - bias-pull-up
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| /openbmc/linux/drivers/thermal/tegra/ |
| H A D | soctherm.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved.
34 #include <dt-bindings/thermal/tegra124-soctherm.h>
197 #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
200 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
203 #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
205 /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h
206 * level vector
212 #define THROT_LEVEL_TO_DEPTH(level) ((0x1 << (level)) - 1) argument
229 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
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| /openbmc/qemu/hw/dma/ |
| H A D | soc_dma.c | 2 * On-chip DMA controller framework.
21 #include "qemu/error-report.h"
27 memcpy(ch->paddr[0], ch->paddr[1], ch->bytes); in transfer_mem2mem()
28 ch->paddr[0] += ch->bytes; in transfer_mem2mem()
29 ch->paddr[1] += ch->bytes; in transfer_mem2mem()
34 ch->io_fn[1](ch->io_opaque[1], ch->paddr[0], ch->bytes); in transfer_mem2fifo()
35 ch->paddr[0] += ch->bytes; in transfer_mem2fifo()
40 ch->io_fn[0](ch->io_opaque[0], ch->paddr[1], ch->bytes); in transfer_fifo2mem()
41 ch->paddr[1] += ch->bytes; in transfer_fifo2mem()
51 if (ch->bytes > fifo_size) in transfer_fifo2fifo()
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| /openbmc/linux/arch/arm/mach-at91/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
14 bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
18 Select this if you are using an SoC from Microchip's SAME7, SAMS7 or SAMV7
34 Select this if ou are using one of Microchip's SAMA5D2 family SoC.
45 Select this if you are using one of Microchip's SAMA5D3 family SoC.
59 Select this if you are using one of Microchip's SAMA5D4 family SoC.
70 Select this if you are using one of Microchip's SAMA7G5 family SoC.
73 bool "ARMv7 based Microchip LAN966 SoC family"
79 This enables support for ARMv7 based Microchip LAN966 SoC family.
93 Select this if you are using Microchip's AT91RM9200 SoC.
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 2 * Copyright 2019-2021 Advanced Micro Devices, Inc.
121 /*TODO: correct dispclk/dppclk voltage level determination*/
365 /*TODO: correct dispclk/dppclk voltage level determination*/
458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
459 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
460 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
461 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
469 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn315_update_soc_for_wm_a()
471 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn315_update_soc_for_wm_a()
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| /openbmc/linux/Documentation/driver-api/firmware/ |
| H A D | other_interfaces.rst | 5 --------------
7 .. kernel-doc:: drivers/firmware/dmi_scan.c
11 --------------
13 .. kernel-doc:: drivers/firmware/edd.c
17 -------------------------------------
19 .. kernel-doc:: drivers/firmware/sysfb.c
22 Intel Stratix10 SoC Service Layer
23 ---------------------------------
24 Some features of the Intel Stratix10 SoC require a level of privilege
27 at Exception Level 1 (EL1), access to the features requires
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| /openbmc/u-boot/drivers/pinctrl/uniphier/ |
| H A D | pinctrl-uniphier.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015-2016 Socionext Inc.
19 - 1)
26 - 1)
30 UNIPHIER_PIN_DRV_1BIT, /* 2 level control: 4/8 mA */
31 UNIPHIER_PIN_DRV_2BIT, /* 4 level control: 8/12/16/20 mA */
32 UNIPHIER_PIN_DRV_3BIT, /* 8 level control: 4/5/7/9/11/12/14/16 mA */
56 * struct uniphier_pinctrl_pin - pin data for UniPhier SoC
59 * @data: additional per-pin data
68 * struct uniphier_pinctrl_group - pin group data for UniPhier SoC
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| /openbmc/linux/sound/soc/sof/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
21 For backwards-compatibility with previous configurations the selection will
22 be used as default for platform-specific drivers.
32 For backwards-compatibility with previous configurations the selection will
33 be used as default for platform-specific drivers.
62 This option is not user-selectable but automagically handled by
63 'select' statements at a higher level.
69 This option is not user-selectable but automagically handled by
70 'select' statements at a higher level.
121 during topology creation or run-time usage if new functionality
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| /openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | mpc5121-psc.txt | 4 ----------------
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
12 --------------------------
15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
16 Supported <soc>s: mpc5121, mpc5125
17 - reg : Offset and length of the register set for the PSC device
18 - interrupts : <a b> where a is the interrupt number of the
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| H A D | mpc5200.txt | 2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
18 chip? For the MPC5200; the answer is easy. Most of the SoC devices
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
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| /openbmc/qemu/docs/system/riscv/ |
| H A D | shakti-c.rst | 5 for the Shakti SoC.
7 Shakti SoC is a SoC based on the Shakti C-class processor core. Shakti C
10 For more details on Shakti SoC, please see:
11 https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/fpga/boards/artya7-100t/c-class/REA…
13 For more info on the Shakti C-class core, please see:
14 https://c-class.readthedocs.io/en/latest/
17 -----------------
21 * 1 C-class core
22 * Core Level Interruptor (CLINT)
23 * Platform-Level Interrupt Controller (PLIC)
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| /openbmc/linux/drivers/gpu/drm/nouveau/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
29 Choose this option for open-source NVIDIA support.
32 bool "Nouveau (NVIDIA) SoC GPUs"
36 Support for Nouveau platform driver, used for SoC GPUs as found
40 int "Maximum debug level"
45 Selects the maximum debug level to compile support for.
47 0 - fatal
48 1 - error
49 2 - warning
50 3 - info
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| /openbmc/linux/Documentation/devicetree/bindings/arm/msm/ |
| H A D | qcom,idle-state.txt | 3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
6 The idle states supported by the QCOM SoC are defined as -
41 back into Elevation Level (EL) which trampolines the control back to the
44 code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
48 itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
49 modes. In a hierarchical power domain SoC, this means L2 and other caches can
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
53 of this low power mode would be considered high even though at a cpu level,
55 with the Resource power manager (RPM) processor in the SoC to indicate a
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | imx6q.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
24 operating-points = <
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
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| /openbmc/linux/drivers/pinctrl/intel/ |
| H A D | Kconfig.tng | 1 # SPDX-License-Identifier: GPL-2.0-only
15 If built as a module its name will be pinctrl-tangier.
21 Intel Merrifield Family-Level Interface Shim (FLIS) driver provides
22 an interface that allows configuring of SoC pins and using them as
29 Intel Moorefield Family-Level Interface Shim (FLIS) driver provides
30 an interface that allows configuring of SoC pins and using them as
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| /openbmc/linux/arch/powerpc/boot/dts/fsl/ |
| H A D | t104xsi-pre.dtsi | 2 * T1040/T1042 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2013-2014 Freescale Semiconductor Inc.
35 /dts-v1/;
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
45 ccsr = &soc;
71 #address-cells = <1>;
72 #size-cells = <0>;
78 next-level-cache = <&L2_1>;
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| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | qcom,qusb2-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Wesley Cheng <quic_wcheng@quicinc.com>
19 - items:
20 - enum:
21 - qcom,ipq6018-qusb2-phy
22 - qcom,ipq8074-qusb2-phy
23 - qcom,ipq9574-qusb2-phy
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