16ca29b7eSWei Ni // SPDX-License-Identifier: GPL-2.0
265b6d57cSWei Ni /*
36ca29b7eSWei Ni * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved.
465b6d57cSWei Ni *
565b6d57cSWei Ni * Author:
665b6d57cSWei Ni * Mikko Perttunen <mperttunen@nvidia.com>
765b6d57cSWei Ni *
865b6d57cSWei Ni * This software is licensed under the terms of the GNU General Public
965b6d57cSWei Ni * License version 2, as published by the Free Software Foundation, and
1065b6d57cSWei Ni * may be copied, distributed, and modified under those terms.
1165b6d57cSWei Ni *
1265b6d57cSWei Ni * This program is distributed in the hope that it will be useful,
1365b6d57cSWei Ni * but WITHOUT ANY WARRANTY; without even the implied warranty of
1465b6d57cSWei Ni * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1565b6d57cSWei Ni * GNU General Public License for more details.
1665b6d57cSWei Ni *
1765b6d57cSWei Ni */
1865b6d57cSWei Ni
19d753b22dSWei Ni #include <linux/debugfs.h>
2065b6d57cSWei Ni #include <linux/bitops.h>
2165b6d57cSWei Ni #include <linux/clk.h>
2265b6d57cSWei Ni #include <linux/delay.h>
2365b6d57cSWei Ni #include <linux/err.h>
2465b6d57cSWei Ni #include <linux/interrupt.h>
2565b6d57cSWei Ni #include <linux/io.h>
264a04beb1SWei Ni #include <linux/irq.h>
274a04beb1SWei Ni #include <linux/irqdomain.h>
2865b6d57cSWei Ni #include <linux/module.h>
2965b6d57cSWei Ni #include <linux/of.h>
3065b6d57cSWei Ni #include <linux/platform_device.h>
3165b6d57cSWei Ni #include <linux/reset.h>
3265b6d57cSWei Ni #include <linux/thermal.h>
3365b6d57cSWei Ni
3465b6d57cSWei Ni #include <dt-bindings/thermal/tegra124-soctherm.h>
3565b6d57cSWei Ni
36ce0dbf04SWei Ni #include "../thermal_core.h"
3765b6d57cSWei Ni #include "soctherm.h"
3865b6d57cSWei Ni
3965b6d57cSWei Ni #define SENSOR_CONFIG0 0
4065b6d57cSWei Ni #define SENSOR_CONFIG0_STOP BIT(0)
4165b6d57cSWei Ni #define SENSOR_CONFIG0_CPTR_OVER BIT(2)
42d753b22dSWei Ni #define SENSOR_CONFIG0_OVER BIT(3)
43d753b22dSWei Ni #define SENSOR_CONFIG0_TCALC_OVER BIT(4)
44d753b22dSWei Ni #define SENSOR_CONFIG0_TALL_MASK (0xfffff << 8)
45d753b22dSWei Ni #define SENSOR_CONFIG0_TALL_SHIFT 8
4665b6d57cSWei Ni
4765b6d57cSWei Ni #define SENSOR_CONFIG1 4
48d753b22dSWei Ni #define SENSOR_CONFIG1_TSAMPLE_MASK 0x3ff
4965b6d57cSWei Ni #define SENSOR_CONFIG1_TSAMPLE_SHIFT 0
50d753b22dSWei Ni #define SENSOR_CONFIG1_TIDDQ_EN_MASK (0x3f << 15)
5165b6d57cSWei Ni #define SENSOR_CONFIG1_TIDDQ_EN_SHIFT 15
52d753b22dSWei Ni #define SENSOR_CONFIG1_TEN_COUNT_MASK (0x3f << 24)
5365b6d57cSWei Ni #define SENSOR_CONFIG1_TEN_COUNT_SHIFT 24
5465b6d57cSWei Ni #define SENSOR_CONFIG1_TEMP_ENABLE BIT(31)
5565b6d57cSWei Ni
5665b6d57cSWei Ni /*
5765b6d57cSWei Ni * SENSOR_CONFIG2 is defined in soctherm.h
5865b6d57cSWei Ni * because, it will be used by tegra_soctherm_fuse.c
5965b6d57cSWei Ni */
6065b6d57cSWei Ni
61d753b22dSWei Ni #define SENSOR_STATUS0 0xc
62d753b22dSWei Ni #define SENSOR_STATUS0_VALID_MASK BIT(31)
63d753b22dSWei Ni #define SENSOR_STATUS0_CAPTURE_MASK 0xffff
64d753b22dSWei Ni
65d753b22dSWei Ni #define SENSOR_STATUS1 0x10
66d753b22dSWei Ni #define SENSOR_STATUS1_TEMP_VALID_MASK BIT(31)
67d753b22dSWei Ni #define SENSOR_STATUS1_TEMP_MASK 0xffff
68d753b22dSWei Ni
6965b6d57cSWei Ni #define READBACK_VALUE_MASK 0xff00
7065b6d57cSWei Ni #define READBACK_VALUE_SHIFT 8
7165b6d57cSWei Ni #define READBACK_ADD_HALF BIT(7)
7265b6d57cSWei Ni #define READBACK_NEGATE BIT(0)
7365b6d57cSWei Ni
74ce0dbf04SWei Ni /*
75ce0dbf04SWei Ni * THERMCTL_LEVEL0_GROUP_CPU is defined in soctherm.h
76ce0dbf04SWei Ni * because it will be used by tegraxxx_soctherm.c
77ce0dbf04SWei Ni */
78ce0dbf04SWei Ni #define THERMCTL_LVL0_CPU0_EN_MASK BIT(8)
79ce0dbf04SWei Ni #define THERMCTL_LVL0_CPU0_CPU_THROT_MASK (0x3 << 5)
80ce0dbf04SWei Ni #define THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT 0x1
81ce0dbf04SWei Ni #define THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY 0x2
82ce0dbf04SWei Ni #define THERMCTL_LVL0_CPU0_GPU_THROT_MASK (0x3 << 3)
83ce0dbf04SWei Ni #define THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT 0x1
84ce0dbf04SWei Ni #define THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY 0x2
85ce0dbf04SWei Ni #define THERMCTL_LVL0_CPU0_MEM_THROT_MASK BIT(2)
86ce0dbf04SWei Ni #define THERMCTL_LVL0_CPU0_STATUS_MASK 0x3
87ce0dbf04SWei Ni
88ce0dbf04SWei Ni #define THERMCTL_LVL0_UP_STATS 0x10
89ce0dbf04SWei Ni #define THERMCTL_LVL0_DN_STATS 0x14
90ce0dbf04SWei Ni
91d7180be0SWei Ni #define THERMCTL_INTR_STATUS 0x84
92d7180be0SWei Ni
93d7180be0SWei Ni #define TH_INTR_MD0_MASK BIT(25)
94d7180be0SWei Ni #define TH_INTR_MU0_MASK BIT(24)
95d7180be0SWei Ni #define TH_INTR_GD0_MASK BIT(17)
96d7180be0SWei Ni #define TH_INTR_GU0_MASK BIT(16)
97d7180be0SWei Ni #define TH_INTR_CD0_MASK BIT(9)
98d7180be0SWei Ni #define TH_INTR_CU0_MASK BIT(8)
99d7180be0SWei Ni #define TH_INTR_PD0_MASK BIT(1)
100d7180be0SWei Ni #define TH_INTR_PU0_MASK BIT(0)
101d7180be0SWei Ni #define TH_INTR_IGNORE_MASK 0xFCFCFCFC
102d7180be0SWei Ni
103ce0dbf04SWei Ni #define THERMCTL_STATS_CTL 0x94
104ce0dbf04SWei Ni #define STATS_CTL_CLR_DN 0x8
105ce0dbf04SWei Ni #define STATS_CTL_EN_DN 0x4
106ce0dbf04SWei Ni #define STATS_CTL_CLR_UP 0x2
107ce0dbf04SWei Ni #define STATS_CTL_EN_UP 0x1
108ce0dbf04SWei Ni
1091dcc242cSWei Ni #define OC1_CFG 0x310
1101dcc242cSWei Ni #define OC1_CFG_LONG_LATENCY_MASK BIT(6)
1111dcc242cSWei Ni #define OC1_CFG_HW_RESTORE_MASK BIT(5)
1121dcc242cSWei Ni #define OC1_CFG_PWR_GOOD_MASK_MASK BIT(4)
1131dcc242cSWei Ni #define OC1_CFG_THROTTLE_MODE_MASK (0x3 << 2)
1141dcc242cSWei Ni #define OC1_CFG_ALARM_POLARITY_MASK BIT(1)
1151dcc242cSWei Ni #define OC1_CFG_EN_THROTTLE_MASK BIT(0)
1161dcc242cSWei Ni
1171dcc242cSWei Ni #define OC1_CNT_THRESHOLD 0x314
1181dcc242cSWei Ni #define OC1_THROTTLE_PERIOD 0x318
1191dcc242cSWei Ni #define OC1_ALARM_COUNT 0x31c
1201dcc242cSWei Ni #define OC1_FILTER 0x320
1211dcc242cSWei Ni #define OC1_STATS 0x3a8
1221dcc242cSWei Ni
1234a04beb1SWei Ni #define OC_INTR_STATUS 0x39c
1244a04beb1SWei Ni #define OC_INTR_ENABLE 0x3a0
1254a04beb1SWei Ni #define OC_INTR_DISABLE 0x3a4
1261dcc242cSWei Ni #define OC_STATS_CTL 0x3c4
1271dcc242cSWei Ni #define OC_STATS_CTL_CLR_ALL 0x2
1281dcc242cSWei Ni #define OC_STATS_CTL_EN_ALL 0x1
1294a04beb1SWei Ni
1304a04beb1SWei Ni #define OC_INTR_OC1_MASK BIT(0)
1314a04beb1SWei Ni #define OC_INTR_OC2_MASK BIT(1)
1324a04beb1SWei Ni #define OC_INTR_OC3_MASK BIT(2)
1334a04beb1SWei Ni #define OC_INTR_OC4_MASK BIT(3)
1344a04beb1SWei Ni #define OC_INTR_OC5_MASK BIT(4)
1354a04beb1SWei Ni
136ce0dbf04SWei Ni #define THROT_GLOBAL_CFG 0x400
137ce0dbf04SWei Ni #define THROT_GLOBAL_ENB_MASK BIT(0)
138ce0dbf04SWei Ni
139ce0dbf04SWei Ni #define CPU_PSKIP_STATUS 0x418
140ce0dbf04SWei Ni #define XPU_PSKIP_STATUS_M_MASK (0xff << 12)
141ce0dbf04SWei Ni #define XPU_PSKIP_STATUS_N_MASK (0xff << 4)
142ce0dbf04SWei Ni #define XPU_PSKIP_STATUS_SW_OVERRIDE_MASK BIT(1)
143ce0dbf04SWei Ni #define XPU_PSKIP_STATUS_ENABLED_MASK BIT(0)
144ce0dbf04SWei Ni
145ce0dbf04SWei Ni #define THROT_PRIORITY_LOCK 0x424
146ce0dbf04SWei Ni #define THROT_PRIORITY_LOCK_PRIORITY_MASK 0xff
147ce0dbf04SWei Ni
148ce0dbf04SWei Ni #define THROT_STATUS 0x428
149ce0dbf04SWei Ni #define THROT_STATUS_BREACH_MASK BIT(12)
150ce0dbf04SWei Ni #define THROT_STATUS_STATE_MASK (0xff << 4)
151ce0dbf04SWei Ni #define THROT_STATUS_ENABLED_MASK BIT(0)
152ce0dbf04SWei Ni
153ce0dbf04SWei Ni #define THROT_PSKIP_CTRL_LITE_CPU 0x430
154ce0dbf04SWei Ni #define THROT_PSKIP_CTRL_ENABLE_MASK BIT(31)
155ce0dbf04SWei Ni #define THROT_PSKIP_CTRL_DIVIDEND_MASK (0xff << 8)
156ce0dbf04SWei Ni #define THROT_PSKIP_CTRL_DIVISOR_MASK 0xff
157ce0dbf04SWei Ni #define THROT_PSKIP_CTRL_VECT_GPU_MASK (0x7 << 16)
158ce0dbf04SWei Ni #define THROT_PSKIP_CTRL_VECT_CPU_MASK (0x7 << 8)
159ce0dbf04SWei Ni #define THROT_PSKIP_CTRL_VECT2_CPU_MASK 0x7
160ce0dbf04SWei Ni
161ce0dbf04SWei Ni #define THROT_VECT_NONE 0x0 /* 3'b000 */
162ce0dbf04SWei Ni #define THROT_VECT_LOW 0x1 /* 3'b001 */
163ce0dbf04SWei Ni #define THROT_VECT_MED 0x3 /* 3'b011 */
164ce0dbf04SWei Ni #define THROT_VECT_HIGH 0x7 /* 3'b111 */
165ce0dbf04SWei Ni
166ce0dbf04SWei Ni #define THROT_PSKIP_RAMP_LITE_CPU 0x434
167ce0dbf04SWei Ni #define THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK BIT(31)
168ce0dbf04SWei Ni #define THROT_PSKIP_RAMP_DURATION_MASK (0xffff << 8)
169ce0dbf04SWei Ni #define THROT_PSKIP_RAMP_STEP_MASK 0xff
170ce0dbf04SWei Ni
171ce0dbf04SWei Ni #define THROT_PRIORITY_LITE 0x444
172ce0dbf04SWei Ni #define THROT_PRIORITY_LITE_PRIO_MASK 0xff
173ce0dbf04SWei Ni
174ce0dbf04SWei Ni #define THROT_DELAY_LITE 0x448
175ce0dbf04SWei Ni #define THROT_DELAY_LITE_DELAY_MASK 0xff
176ce0dbf04SWei Ni
177ce0dbf04SWei Ni /* car register offsets needed for enabling HW throttling */
178ce0dbf04SWei Ni #define CAR_SUPER_CCLKG_DIVIDER 0x36c
179ce0dbf04SWei Ni #define CDIVG_USE_THERM_CONTROLS_MASK BIT(30)
180ce0dbf04SWei Ni
1816c7c3245SWei Ni /* ccroc register offsets needed for enabling HW throttling for Tegra132 */
1826c7c3245SWei Ni #define CCROC_SUPER_CCLKG_DIVIDER 0x024
1836c7c3245SWei Ni
1846c7c3245SWei Ni #define CCROC_GLOBAL_CFG 0x148
1856c7c3245SWei Ni
1866c7c3245SWei Ni #define CCROC_THROT_PSKIP_RAMP_CPU 0x150
1876c7c3245SWei Ni #define CCROC_THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK BIT(31)
1886c7c3245SWei Ni #define CCROC_THROT_PSKIP_RAMP_DURATION_MASK (0xffff << 8)
1896c7c3245SWei Ni #define CCROC_THROT_PSKIP_RAMP_STEP_MASK 0xff
1906c7c3245SWei Ni
1916c7c3245SWei Ni #define CCROC_THROT_PSKIP_CTRL_CPU 0x154
1926c7c3245SWei Ni #define CCROC_THROT_PSKIP_CTRL_ENB_MASK BIT(31)
1936c7c3245SWei Ni #define CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK (0xff << 8)
1946c7c3245SWei Ni #define CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK 0xff
1956c7c3245SWei Ni
19665b6d57cSWei Ni /* get val from register(r) mask bits(m) */
19765b6d57cSWei Ni #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
19865b6d57cSWei Ni /* set val(v) to mask bits(m) of register(r) */
19965b6d57cSWei Ni #define REG_SET_MASK(r, m, v) (((r) & ~(m)) | \
20065b6d57cSWei Ni (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
20165b6d57cSWei Ni
202ce0dbf04SWei Ni /* get dividend from the depth */
203ce0dbf04SWei Ni #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
204ce0dbf04SWei Ni
2059d6b4b87SChristophe JAILLET /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h
2066ca29b7eSWei Ni * level vector
2076ca29b7eSWei Ni * NONE 3'b000
2086ca29b7eSWei Ni * LOW 3'b001
2096ca29b7eSWei Ni * MED 3'b011
2106ca29b7eSWei Ni * HIGH 3'b111
2116ca29b7eSWei Ni */
2126ca29b7eSWei Ni #define THROT_LEVEL_TO_DEPTH(level) ((0x1 << (level)) - 1)
2136ca29b7eSWei Ni
214ce0dbf04SWei Ni /* get THROT_PSKIP_xxx offset per LIGHT/HEAVY throt and CPU/GPU dev */
215ce0dbf04SWei Ni #define THROT_OFFSET 0x30
216ce0dbf04SWei Ni #define THROT_PSKIP_CTRL(throt, dev) (THROT_PSKIP_CTRL_LITE_CPU + \
217ce0dbf04SWei Ni (THROT_OFFSET * throt) + (8 * dev))
218ce0dbf04SWei Ni #define THROT_PSKIP_RAMP(throt, dev) (THROT_PSKIP_RAMP_LITE_CPU + \
219ce0dbf04SWei Ni (THROT_OFFSET * throt) + (8 * dev))
220ce0dbf04SWei Ni
221ce0dbf04SWei Ni /* get THROT_xxx_CTRL offset per LIGHT/HEAVY throt */
222ce0dbf04SWei Ni #define THROT_PRIORITY_CTRL(throt) (THROT_PRIORITY_LITE + \
223ce0dbf04SWei Ni (THROT_OFFSET * throt))
224ce0dbf04SWei Ni #define THROT_DELAY_CTRL(throt) (THROT_DELAY_LITE + \
225ce0dbf04SWei Ni (THROT_OFFSET * throt))
226ce0dbf04SWei Ni
2271dcc242cSWei Ni #define ALARM_OFFSET 0x14
2281dcc242cSWei Ni #define ALARM_CFG(throt) (OC1_CFG + \
2291dcc242cSWei Ni (ALARM_OFFSET * (throt - THROTTLE_OC1)))
2301dcc242cSWei Ni
2311dcc242cSWei Ni #define ALARM_CNT_THRESHOLD(throt) (OC1_CNT_THRESHOLD + \
2321dcc242cSWei Ni (ALARM_OFFSET * (throt - THROTTLE_OC1)))
2331dcc242cSWei Ni
2341dcc242cSWei Ni #define ALARM_THROTTLE_PERIOD(throt) (OC1_THROTTLE_PERIOD + \
2351dcc242cSWei Ni (ALARM_OFFSET * (throt - THROTTLE_OC1)))
2361dcc242cSWei Ni
2371dcc242cSWei Ni #define ALARM_ALARM_COUNT(throt) (OC1_ALARM_COUNT + \
2381dcc242cSWei Ni (ALARM_OFFSET * (throt - THROTTLE_OC1)))
2391dcc242cSWei Ni
2401dcc242cSWei Ni #define ALARM_FILTER(throt) (OC1_FILTER + \
2411dcc242cSWei Ni (ALARM_OFFSET * (throt - THROTTLE_OC1)))
2421dcc242cSWei Ni
2431dcc242cSWei Ni #define ALARM_STATS(throt) (OC1_STATS + \
2441dcc242cSWei Ni (4 * (throt - THROTTLE_OC1)))
2451dcc242cSWei Ni
2466c7c3245SWei Ni /* get CCROC_THROT_PSKIP_xxx offset per HIGH/MED/LOW vect*/
2476c7c3245SWei Ni #define CCROC_THROT_OFFSET 0x0c
2486c7c3245SWei Ni #define CCROC_THROT_PSKIP_CTRL_CPU_REG(vect) (CCROC_THROT_PSKIP_CTRL_CPU + \
2496c7c3245SWei Ni (CCROC_THROT_OFFSET * vect))
2506c7c3245SWei Ni #define CCROC_THROT_PSKIP_RAMP_CPU_REG(vect) (CCROC_THROT_PSKIP_RAMP_CPU + \
2516c7c3245SWei Ni (CCROC_THROT_OFFSET * vect))
2526c7c3245SWei Ni
253ce0dbf04SWei Ni /* get THERMCTL_LEVELx offset per CPU/GPU/MEM/TSENSE rg and LEVEL0~3 lv */
254ce0dbf04SWei Ni #define THERMCTL_LVL_REGS_SIZE 0x20
255ce0dbf04SWei Ni #define THERMCTL_LVL_REG(rg, lv) ((rg) + ((lv) * THERMCTL_LVL_REGS_SIZE))
256ce0dbf04SWei Ni
2571dcc242cSWei Ni #define OC_THROTTLE_MODE_DISABLED 0
2581dcc242cSWei Ni #define OC_THROTTLE_MODE_BRIEF 2
2591dcc242cSWei Ni
2602a895871SWei Ni static const int min_low_temp = -127000;
2612a895871SWei Ni static const int max_high_temp = 127000;
2622a895871SWei Ni
263ce0dbf04SWei Ni enum soctherm_throttle_id {
264ce0dbf04SWei Ni THROTTLE_LIGHT = 0,
265ce0dbf04SWei Ni THROTTLE_HEAVY,
2664a04beb1SWei Ni THROTTLE_OC1,
2674a04beb1SWei Ni THROTTLE_OC2,
2684a04beb1SWei Ni THROTTLE_OC3,
2694a04beb1SWei Ni THROTTLE_OC4,
2704a04beb1SWei Ni THROTTLE_OC5, /* OC5 is reserved */
271ce0dbf04SWei Ni THROTTLE_SIZE,
272ce0dbf04SWei Ni };
273ce0dbf04SWei Ni
2744a04beb1SWei Ni enum soctherm_oc_irq_id {
2754a04beb1SWei Ni TEGRA_SOC_OC_IRQ_1,
2764a04beb1SWei Ni TEGRA_SOC_OC_IRQ_2,
2774a04beb1SWei Ni TEGRA_SOC_OC_IRQ_3,
2784a04beb1SWei Ni TEGRA_SOC_OC_IRQ_4,
2794a04beb1SWei Ni TEGRA_SOC_OC_IRQ_5,
2804a04beb1SWei Ni TEGRA_SOC_OC_IRQ_MAX,
2814a04beb1SWei Ni };
2824a04beb1SWei Ni
283ce0dbf04SWei Ni enum soctherm_throttle_dev_id {
284ce0dbf04SWei Ni THROTTLE_DEV_CPU = 0,
285ce0dbf04SWei Ni THROTTLE_DEV_GPU,
286ce0dbf04SWei Ni THROTTLE_DEV_SIZE,
287ce0dbf04SWei Ni };
288ce0dbf04SWei Ni
289ce0dbf04SWei Ni static const char *const throt_names[] = {
290ce0dbf04SWei Ni [THROTTLE_LIGHT] = "light",
291ce0dbf04SWei Ni [THROTTLE_HEAVY] = "heavy",
2924a04beb1SWei Ni [THROTTLE_OC1] = "oc1",
2934a04beb1SWei Ni [THROTTLE_OC2] = "oc2",
2944a04beb1SWei Ni [THROTTLE_OC3] = "oc3",
2954a04beb1SWei Ni [THROTTLE_OC4] = "oc4",
2964a04beb1SWei Ni [THROTTLE_OC5] = "oc5",
297ce0dbf04SWei Ni };
298ce0dbf04SWei Ni
299ce0dbf04SWei Ni struct tegra_soctherm;
30065b6d57cSWei Ni struct tegra_thermctl_zone {
30165b6d57cSWei Ni void __iomem *reg;
3022a895871SWei Ni struct device *dev;
303ce0dbf04SWei Ni struct tegra_soctherm *ts;
3042a895871SWei Ni struct thermal_zone_device *tz;
3052a895871SWei Ni const struct tegra_tsensor_group *sg;
30665b6d57cSWei Ni };
30765b6d57cSWei Ni
3081dcc242cSWei Ni struct soctherm_oc_cfg {
3091dcc242cSWei Ni u32 active_low;
3101dcc242cSWei Ni u32 throt_period;
3111dcc242cSWei Ni u32 alarm_cnt_thresh;
3121dcc242cSWei Ni u32 alarm_filter;
3131dcc242cSWei Ni u32 mode;
3141dcc242cSWei Ni bool intr_en;
3151dcc242cSWei Ni };
3161dcc242cSWei Ni
317ce0dbf04SWei Ni struct soctherm_throt_cfg {
318ce0dbf04SWei Ni const char *name;
319ce0dbf04SWei Ni unsigned int id;
320ce0dbf04SWei Ni u8 priority;
3216c7c3245SWei Ni u8 cpu_throt_level;
322ce0dbf04SWei Ni u32 cpu_throt_depth;
3236ca29b7eSWei Ni u32 gpu_throt_level;
3241dcc242cSWei Ni struct soctherm_oc_cfg oc_cfg;
325ce0dbf04SWei Ni struct thermal_cooling_device *cdev;
326ce0dbf04SWei Ni bool init;
327ce0dbf04SWei Ni };
328ce0dbf04SWei Ni
32965b6d57cSWei Ni struct tegra_soctherm {
33065b6d57cSWei Ni struct reset_control *reset;
33165b6d57cSWei Ni struct clk *clock_tsensor;
33265b6d57cSWei Ni struct clk *clock_soctherm;
33365b6d57cSWei Ni void __iomem *regs;
334ce0dbf04SWei Ni void __iomem *clk_regs;
3356c7c3245SWei Ni void __iomem *ccroc_regs;
33665b6d57cSWei Ni
337d7180be0SWei Ni int thermal_irq;
3384a04beb1SWei Ni int edp_irq;
339d7180be0SWei Ni
34065b6d57cSWei Ni u32 *calib;
341ce0dbf04SWei Ni struct thermal_zone_device **thermctl_tzs;
34265b6d57cSWei Ni struct tegra_soctherm_soc *soc;
343d753b22dSWei Ni
344ce0dbf04SWei Ni struct soctherm_throt_cfg throt_cfgs[THROTTLE_SIZE];
345ce0dbf04SWei Ni
346d753b22dSWei Ni struct dentry *debugfs_dir;
3475c9d6ac2SWei Ni
3485c9d6ac2SWei Ni struct mutex thermctl_lock;
34965b6d57cSWei Ni };
35065b6d57cSWei Ni
3514a04beb1SWei Ni struct soctherm_oc_irq_chip_data {
3524a04beb1SWei Ni struct mutex irq_lock; /* serialize OC IRQs */
3534a04beb1SWei Ni struct irq_chip irq_chip;
3544a04beb1SWei Ni struct irq_domain *domain;
3554a04beb1SWei Ni int irq_enable;
3564a04beb1SWei Ni };
3574a04beb1SWei Ni
3584a04beb1SWei Ni static struct soctherm_oc_irq_chip_data soc_irq_cdata;
3594a04beb1SWei Ni
360ce0dbf04SWei Ni /**
3616c7c3245SWei Ni * ccroc_writel() - writes a value to a CCROC register
3626c7c3245SWei Ni * @ts: pointer to a struct tegra_soctherm
3636a6d634cSAmit Kucheria * @value: the value to write
3646c7c3245SWei Ni * @reg: the register offset
3656c7c3245SWei Ni *
3666c7c3245SWei Ni * Writes @v to @reg. No return value.
3676c7c3245SWei Ni */
ccroc_writel(struct tegra_soctherm * ts,u32 value,u32 reg)3686c7c3245SWei Ni static inline void ccroc_writel(struct tegra_soctherm *ts, u32 value, u32 reg)
3696c7c3245SWei Ni {
3706c7c3245SWei Ni writel(value, (ts->ccroc_regs + reg));
3716c7c3245SWei Ni }
3726c7c3245SWei Ni
3736c7c3245SWei Ni /**
3746c7c3245SWei Ni * ccroc_readl() - reads specified register from CCROC IP block
3756c7c3245SWei Ni * @ts: pointer to a struct tegra_soctherm
3766c7c3245SWei Ni * @reg: register address to be read
3776c7c3245SWei Ni *
3786c7c3245SWei Ni * Return: the value of the register
3796c7c3245SWei Ni */
ccroc_readl(struct tegra_soctherm * ts,u32 reg)3806c7c3245SWei Ni static inline u32 ccroc_readl(struct tegra_soctherm *ts, u32 reg)
3816c7c3245SWei Ni {
3826c7c3245SWei Ni return readl(ts->ccroc_regs + reg);
3836c7c3245SWei Ni }
3846c7c3245SWei Ni
enable_tsensor(struct tegra_soctherm * tegra,unsigned int i)3851ed895c2SWei Ni static void enable_tsensor(struct tegra_soctherm *tegra, unsigned int i)
38665b6d57cSWei Ni {
38765b6d57cSWei Ni const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i];
38865b6d57cSWei Ni void __iomem *base = tegra->regs + sensor->base;
38965b6d57cSWei Ni unsigned int val;
39065b6d57cSWei Ni
39165b6d57cSWei Ni val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT;
39265b6d57cSWei Ni writel(val, base + SENSOR_CONFIG0);
39365b6d57cSWei Ni
39465b6d57cSWei Ni val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT;
39565b6d57cSWei Ni val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
39665b6d57cSWei Ni val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
39765b6d57cSWei Ni val |= SENSOR_CONFIG1_TEMP_ENABLE;
39865b6d57cSWei Ni writel(val, base + SENSOR_CONFIG1);
39965b6d57cSWei Ni
4001ed895c2SWei Ni writel(tegra->calib[i], base + SENSOR_CONFIG2);
40165b6d57cSWei Ni }
40265b6d57cSWei Ni
40365b6d57cSWei Ni /*
40465b6d57cSWei Ni * Translate from soctherm readback format to millicelsius.
40565b6d57cSWei Ni * The soctherm readback format in bits is as follows:
40665b6d57cSWei Ni * TTTTTTTT H______N
40765b6d57cSWei Ni * where T's contain the temperature in Celsius,
40865b6d57cSWei Ni * H denotes an addition of 0.5 Celsius and N denotes negation
40965b6d57cSWei Ni * of the final value.
41065b6d57cSWei Ni */
translate_temp(u16 val)41165b6d57cSWei Ni static int translate_temp(u16 val)
41265b6d57cSWei Ni {
41365b6d57cSWei Ni int t;
41465b6d57cSWei Ni
41565b6d57cSWei Ni t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
41665b6d57cSWei Ni if (val & READBACK_ADD_HALF)
41765b6d57cSWei Ni t += 500;
41865b6d57cSWei Ni if (val & READBACK_NEGATE)
41965b6d57cSWei Ni t *= -1;
42065b6d57cSWei Ni
42165b6d57cSWei Ni return t;
42265b6d57cSWei Ni }
42365b6d57cSWei Ni
tegra_thermctl_get_temp(struct thermal_zone_device * tz,int * out_temp)4246fc2e1a5SDaniel Lezcano static int tegra_thermctl_get_temp(struct thermal_zone_device *tz, int *out_temp)
42565b6d57cSWei Ni {
426*5f68d078SDaniel Lezcano struct tegra_thermctl_zone *zone = thermal_zone_device_priv(tz);
42765b6d57cSWei Ni u32 val;
42865b6d57cSWei Ni
42965b6d57cSWei Ni val = readl(zone->reg);
4302a895871SWei Ni val = REG_GET_MASK(val, zone->sg->sensor_temp_mask);
43165b6d57cSWei Ni *out_temp = translate_temp(val);
43265b6d57cSWei Ni
43365b6d57cSWei Ni return 0;
43465b6d57cSWei Ni }
43565b6d57cSWei Ni
4362a895871SWei Ni /**
4372a895871SWei Ni * enforce_temp_range() - check and enforce temperature range [min, max]
4386a6d634cSAmit Kucheria * @dev: struct device * of the SOC_THERM instance
4392a895871SWei Ni * @trip_temp: the trip temperature to check
4402a895871SWei Ni *
4412a895871SWei Ni * Checks and enforces the permitted temperature range that SOC_THERM
4422a895871SWei Ni * HW can support This is
4432a895871SWei Ni * done while taking care of precision.
4442a895871SWei Ni *
4452a895871SWei Ni * Return: The precision adjusted capped temperature in millicelsius.
4462a895871SWei Ni */
enforce_temp_range(struct device * dev,int trip_temp)4472a895871SWei Ni static int enforce_temp_range(struct device *dev, int trip_temp)
4482a895871SWei Ni {
4492a895871SWei Ni int temp;
4502a895871SWei Ni
4512a895871SWei Ni temp = clamp_val(trip_temp, min_low_temp, max_high_temp);
4522a895871SWei Ni if (temp != trip_temp)
45316f94429SDmitry Osipenko dev_dbg(dev, "soctherm: trip temperature %d forced to %d\n",
4542a895871SWei Ni trip_temp, temp);
4552a895871SWei Ni return temp;
4562a895871SWei Ni }
4572a895871SWei Ni
4582a895871SWei Ni /**
4592a895871SWei Ni * thermtrip_program() - Configures the hardware to shut down the
4602a895871SWei Ni * system if a given sensor group reaches a given temperature
4612a895871SWei Ni * @dev: ptr to the struct device for the SOC_THERM IP block
4622a895871SWei Ni * @sg: pointer to the sensor group to set the thermtrip temperature for
4632a895871SWei Ni * @trip_temp: the temperature in millicelsius to trigger the thermal trip at
4642a895871SWei Ni *
4652a895871SWei Ni * Sets the thermal trip threshold of the given sensor group to be the
4662a895871SWei Ni * @trip_temp. If this threshold is crossed, the hardware will shut
4672a895871SWei Ni * down.
4682a895871SWei Ni *
4692a895871SWei Ni * Note that, although @trip_temp is specified in millicelsius, the
4702a895871SWei Ni * hardware is programmed in degrees Celsius.
4712a895871SWei Ni *
4722a895871SWei Ni * Return: 0 upon success, or %-EINVAL upon failure.
4732a895871SWei Ni */
thermtrip_program(struct device * dev,const struct tegra_tsensor_group * sg,int trip_temp)4742a895871SWei Ni static int thermtrip_program(struct device *dev,
4752a895871SWei Ni const struct tegra_tsensor_group *sg,
4762a895871SWei Ni int trip_temp)
4772a895871SWei Ni {
4782a895871SWei Ni struct tegra_soctherm *ts = dev_get_drvdata(dev);
4792a895871SWei Ni int temp;
4802a895871SWei Ni u32 r;
4812a895871SWei Ni
482f3500980SWei Ni if (!sg || !sg->thermtrip_threshold_mask)
4832a895871SWei Ni return -EINVAL;
4842a895871SWei Ni
4852a895871SWei Ni temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain;
4862a895871SWei Ni
4872a895871SWei Ni r = readl(ts->regs + THERMCTL_THERMTRIP_CTL);
4882a895871SWei Ni r = REG_SET_MASK(r, sg->thermtrip_threshold_mask, temp);
4892a895871SWei Ni r = REG_SET_MASK(r, sg->thermtrip_enable_mask, 1);
4902a895871SWei Ni r = REG_SET_MASK(r, sg->thermtrip_any_en_mask, 0);
4912a895871SWei Ni writel(r, ts->regs + THERMCTL_THERMTRIP_CTL);
4922a895871SWei Ni
4932a895871SWei Ni return 0;
4942a895871SWei Ni }
4952a895871SWei Ni
4962a895871SWei Ni /**
497ce0dbf04SWei Ni * throttrip_program() - Configures the hardware to throttle the
498ce0dbf04SWei Ni * pulse if a given sensor group reaches a given temperature
499ce0dbf04SWei Ni * @dev: ptr to the struct device for the SOC_THERM IP block
500ce0dbf04SWei Ni * @sg: pointer to the sensor group to set the thermtrip temperature for
501ce0dbf04SWei Ni * @stc: pointer to the throttle need to be triggered
502ce0dbf04SWei Ni * @trip_temp: the temperature in millicelsius to trigger the thermal trip at
503ce0dbf04SWei Ni *
504ce0dbf04SWei Ni * Sets the thermal trip threshold and throttle event of the given sensor
505ce0dbf04SWei Ni * group. If this threshold is crossed, the hardware will trigger the
506ce0dbf04SWei Ni * throttle.
507ce0dbf04SWei Ni *
508ce0dbf04SWei Ni * Note that, although @trip_temp is specified in millicelsius, the
509ce0dbf04SWei Ni * hardware is programmed in degrees Celsius.
510ce0dbf04SWei Ni *
511ce0dbf04SWei Ni * Return: 0 upon success, or %-EINVAL upon failure.
512ce0dbf04SWei Ni */
throttrip_program(struct device * dev,const struct tegra_tsensor_group * sg,struct soctherm_throt_cfg * stc,int trip_temp)513ce0dbf04SWei Ni static int throttrip_program(struct device *dev,
514ce0dbf04SWei Ni const struct tegra_tsensor_group *sg,
515ce0dbf04SWei Ni struct soctherm_throt_cfg *stc,
516ce0dbf04SWei Ni int trip_temp)
517ce0dbf04SWei Ni {
518ce0dbf04SWei Ni struct tegra_soctherm *ts = dev_get_drvdata(dev);
519ce0dbf04SWei Ni int temp, cpu_throt, gpu_throt;
520ce0dbf04SWei Ni unsigned int throt;
521ce0dbf04SWei Ni u32 r, reg_off;
522ce0dbf04SWei Ni
5231fba81ccSNicolin Chen if (!sg || !stc || !stc->init)
524ce0dbf04SWei Ni return -EINVAL;
525ce0dbf04SWei Ni
526ce0dbf04SWei Ni temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain;
527ce0dbf04SWei Ni
528ce0dbf04SWei Ni /* Hardcode LIGHT on LEVEL1 and HEAVY on LEVEL2 */
529ce0dbf04SWei Ni throt = stc->id;
530ce0dbf04SWei Ni reg_off = THERMCTL_LVL_REG(sg->thermctl_lvl0_offset, throt + 1);
531ce0dbf04SWei Ni
532ce0dbf04SWei Ni if (throt == THROTTLE_LIGHT) {
533ce0dbf04SWei Ni cpu_throt = THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT;
534ce0dbf04SWei Ni gpu_throt = THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT;
535ce0dbf04SWei Ni } else {
536ce0dbf04SWei Ni cpu_throt = THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY;
537ce0dbf04SWei Ni gpu_throt = THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY;
538ce0dbf04SWei Ni if (throt != THROTTLE_HEAVY)
539ce0dbf04SWei Ni dev_warn(dev,
540ce0dbf04SWei Ni "invalid throt id %d - assuming HEAVY",
541ce0dbf04SWei Ni throt);
542ce0dbf04SWei Ni }
543ce0dbf04SWei Ni
544ce0dbf04SWei Ni r = readl(ts->regs + reg_off);
545ce0dbf04SWei Ni r = REG_SET_MASK(r, sg->thermctl_lvl0_up_thresh_mask, temp);
546ce0dbf04SWei Ni r = REG_SET_MASK(r, sg->thermctl_lvl0_dn_thresh_mask, temp);
547ce0dbf04SWei Ni r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_CPU_THROT_MASK, cpu_throt);
548ce0dbf04SWei Ni r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_GPU_THROT_MASK, gpu_throt);
549ce0dbf04SWei Ni r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1);
550ce0dbf04SWei Ni writel(r, ts->regs + reg_off);
551ce0dbf04SWei Ni
552ce0dbf04SWei Ni return 0;
553ce0dbf04SWei Ni }
554ce0dbf04SWei Ni
555ce0dbf04SWei Ni static struct soctherm_throt_cfg *
find_throttle_cfg_by_name(struct tegra_soctherm * ts,const char * name)556ce0dbf04SWei Ni find_throttle_cfg_by_name(struct tegra_soctherm *ts, const char *name)
557ce0dbf04SWei Ni {
558ce0dbf04SWei Ni unsigned int i;
559ce0dbf04SWei Ni
560ce0dbf04SWei Ni for (i = 0; ts->throt_cfgs[i].name; i++)
561ce0dbf04SWei Ni if (!strcmp(ts->throt_cfgs[i].name, name))
562ce0dbf04SWei Ni return &ts->throt_cfgs[i];
563ce0dbf04SWei Ni
564ce0dbf04SWei Ni return NULL;
565ce0dbf04SWei Ni }
566ce0dbf04SWei Ni
tsensor_group_thermtrip_get(struct tegra_soctherm * ts,int id)5672510aa56SWei Ni static int tsensor_group_thermtrip_get(struct tegra_soctherm *ts, int id)
5682510aa56SWei Ni {
5692510aa56SWei Ni int i, temp = min_low_temp;
5702510aa56SWei Ni struct tsensor_group_thermtrips *tt = ts->soc->thermtrips;
5712510aa56SWei Ni
5722510aa56SWei Ni if (id >= TEGRA124_SOCTHERM_SENSOR_NUM)
5732510aa56SWei Ni return temp;
5742510aa56SWei Ni
5752510aa56SWei Ni if (tt) {
5762510aa56SWei Ni for (i = 0; i < ts->soc->num_ttgs; i++) {
5772510aa56SWei Ni if (tt[i].id == id)
5782510aa56SWei Ni return tt[i].temp;
5792510aa56SWei Ni }
5802510aa56SWei Ni }
5812510aa56SWei Ni
5822510aa56SWei Ni return temp;
5832510aa56SWei Ni }
5842510aa56SWei Ni
tegra_thermctl_set_trip_temp(struct thermal_zone_device * tz,int trip_id,int temp)585735a968dSDaniel Lezcano static int tegra_thermctl_set_trip_temp(struct thermal_zone_device *tz, int trip_id, int temp)
586d790405dSNicolin Chen {
587*5f68d078SDaniel Lezcano struct tegra_thermctl_zone *zone = thermal_zone_device_priv(tz);
588d790405dSNicolin Chen struct tegra_soctherm *ts = zone->ts;
589735a968dSDaniel Lezcano struct thermal_trip trip;
590d790405dSNicolin Chen const struct tegra_tsensor_group *sg = zone->sg;
591d790405dSNicolin Chen struct device *dev = zone->dev;
592d790405dSNicolin Chen int ret;
593d790405dSNicolin Chen
594d790405dSNicolin Chen if (!tz)
595d790405dSNicolin Chen return -EINVAL;
596d790405dSNicolin Chen
597b0b5d063SJohan Hovold ret = __thermal_zone_get_trip(tz, trip_id, &trip);
598d790405dSNicolin Chen if (ret)
599d790405dSNicolin Chen return ret;
600d790405dSNicolin Chen
601735a968dSDaniel Lezcano if (trip.type == THERMAL_TRIP_CRITICAL) {
6022510aa56SWei Ni /*
6032510aa56SWei Ni * If thermtrips property is set in DT,
6042510aa56SWei Ni * doesn't need to program critical type trip to HW,
6052510aa56SWei Ni * if not, program critical trip to HW.
6062510aa56SWei Ni */
6072510aa56SWei Ni if (min_low_temp == tsensor_group_thermtrip_get(ts, sg->id))
608d790405dSNicolin Chen return thermtrip_program(dev, sg, temp);
6092510aa56SWei Ni else
6102510aa56SWei Ni return 0;
6112510aa56SWei Ni
612735a968dSDaniel Lezcano } else if (trip.type == THERMAL_TRIP_HOT) {
613d790405dSNicolin Chen int i;
614d790405dSNicolin Chen
615d790405dSNicolin Chen for (i = 0; i < THROTTLE_SIZE; i++) {
616d790405dSNicolin Chen struct thermal_cooling_device *cdev;
617d790405dSNicolin Chen struct soctherm_throt_cfg *stc;
618d790405dSNicolin Chen
619d790405dSNicolin Chen if (!ts->throt_cfgs[i].init)
620d790405dSNicolin Chen continue;
621d790405dSNicolin Chen
622d790405dSNicolin Chen cdev = ts->throt_cfgs[i].cdev;
623735a968dSDaniel Lezcano if (get_thermal_instance(tz, cdev, trip_id))
624d790405dSNicolin Chen stc = find_throttle_cfg_by_name(ts, cdev->type);
625d790405dSNicolin Chen else
626d790405dSNicolin Chen continue;
627d790405dSNicolin Chen
628d790405dSNicolin Chen return throttrip_program(dev, sg, stc, temp);
629d790405dSNicolin Chen }
630d790405dSNicolin Chen }
631d790405dSNicolin Chen
632d790405dSNicolin Chen return 0;
633d790405dSNicolin Chen }
634d790405dSNicolin Chen
thermal_irq_enable(struct tegra_thermctl_zone * zn)6355c9d6ac2SWei Ni static void thermal_irq_enable(struct tegra_thermctl_zone *zn)
6365c9d6ac2SWei Ni {
6375c9d6ac2SWei Ni u32 r;
6385c9d6ac2SWei Ni
6395c9d6ac2SWei Ni /* multiple zones could be handling and setting trips at once */
6405c9d6ac2SWei Ni mutex_lock(&zn->ts->thermctl_lock);
6415c9d6ac2SWei Ni r = readl(zn->ts->regs + THERMCTL_INTR_ENABLE);
6425c9d6ac2SWei Ni r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, TH_INTR_UP_DN_EN);
6435c9d6ac2SWei Ni writel(r, zn->ts->regs + THERMCTL_INTR_ENABLE);
6445c9d6ac2SWei Ni mutex_unlock(&zn->ts->thermctl_lock);
6455c9d6ac2SWei Ni }
6465c9d6ac2SWei Ni
thermal_irq_disable(struct tegra_thermctl_zone * zn)6475c9d6ac2SWei Ni static void thermal_irq_disable(struct tegra_thermctl_zone *zn)
6485c9d6ac2SWei Ni {
6495c9d6ac2SWei Ni u32 r;
6505c9d6ac2SWei Ni
6515c9d6ac2SWei Ni /* multiple zones could be handling and setting trips at once */
6525c9d6ac2SWei Ni mutex_lock(&zn->ts->thermctl_lock);
6535c9d6ac2SWei Ni r = readl(zn->ts->regs + THERMCTL_INTR_DISABLE);
6545c9d6ac2SWei Ni r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, 0);
6555c9d6ac2SWei Ni writel(r, zn->ts->regs + THERMCTL_INTR_DISABLE);
6565c9d6ac2SWei Ni mutex_unlock(&zn->ts->thermctl_lock);
6575c9d6ac2SWei Ni }
6585c9d6ac2SWei Ni
tegra_thermctl_set_trips(struct thermal_zone_device * tz,int lo,int hi)6596fc2e1a5SDaniel Lezcano static int tegra_thermctl_set_trips(struct thermal_zone_device *tz, int lo, int hi)
6605c9d6ac2SWei Ni {
661*5f68d078SDaniel Lezcano struct tegra_thermctl_zone *zone = thermal_zone_device_priv(tz);
6625c9d6ac2SWei Ni u32 r;
6635c9d6ac2SWei Ni
6645c9d6ac2SWei Ni thermal_irq_disable(zone);
6655c9d6ac2SWei Ni
6665c9d6ac2SWei Ni r = readl(zone->ts->regs + zone->sg->thermctl_lvl0_offset);
6675c9d6ac2SWei Ni r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 0);
6685c9d6ac2SWei Ni writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset);
6695c9d6ac2SWei Ni
6705c9d6ac2SWei Ni lo = enforce_temp_range(zone->dev, lo) / zone->ts->soc->thresh_grain;
6715c9d6ac2SWei Ni hi = enforce_temp_range(zone->dev, hi) / zone->ts->soc->thresh_grain;
6725c9d6ac2SWei Ni dev_dbg(zone->dev, "%s hi:%d, lo:%d\n", __func__, hi, lo);
6735c9d6ac2SWei Ni
6745c9d6ac2SWei Ni r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_up_thresh_mask, hi);
6755c9d6ac2SWei Ni r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_dn_thresh_mask, lo);
6765c9d6ac2SWei Ni r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1);
6775c9d6ac2SWei Ni writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset);
6785c9d6ac2SWei Ni
6795c9d6ac2SWei Ni thermal_irq_enable(zone);
6805c9d6ac2SWei Ni
6815c9d6ac2SWei Ni return 0;
6825c9d6ac2SWei Ni }
6835c9d6ac2SWei Ni
6846fc2e1a5SDaniel Lezcano static const struct thermal_zone_device_ops tegra_of_thermal_ops = {
685d790405dSNicolin Chen .get_temp = tegra_thermctl_get_temp,
686d790405dSNicolin Chen .set_trip_temp = tegra_thermctl_set_trip_temp,
6875c9d6ac2SWei Ni .set_trips = tegra_thermctl_set_trips,
688d790405dSNicolin Chen };
689d790405dSNicolin Chen
get_hot_temp(struct thermal_zone_device * tz,int * trip_id,int * temp)690735a968dSDaniel Lezcano static int get_hot_temp(struct thermal_zone_device *tz, int *trip_id, int *temp)
691ce0dbf04SWei Ni {
692735a968dSDaniel Lezcano int i, ret;
693735a968dSDaniel Lezcano struct thermal_trip trip;
694ce0dbf04SWei Ni
695735a968dSDaniel Lezcano for (i = 0; i < thermal_zone_get_num_trips(tz); i++) {
696ce0dbf04SWei Ni
697735a968dSDaniel Lezcano ret = thermal_zone_get_trip(tz, i, &trip);
698ce0dbf04SWei Ni if (ret)
699ce0dbf04SWei Ni return -EINVAL;
700ce0dbf04SWei Ni
701735a968dSDaniel Lezcano if (trip.type == THERMAL_TRIP_HOT) {
702735a968dSDaniel Lezcano *trip_id = i;
703735a968dSDaniel Lezcano return 0;
704ce0dbf04SWei Ni }
705ce0dbf04SWei Ni }
706ce0dbf04SWei Ni
707ce0dbf04SWei Ni return -EINVAL;
708ce0dbf04SWei Ni }
709ce0dbf04SWei Ni
710ce0dbf04SWei Ni /**
7112a895871SWei Ni * tegra_soctherm_set_hwtrips() - set HW trip point from DT data
7122a895871SWei Ni * @dev: struct device * of the SOC_THERM instance
7136a6d634cSAmit Kucheria * @sg: pointer to the sensor group to set the thermtrip temperature for
7146a6d634cSAmit Kucheria * @tz: struct thermal_zone_device *
7152a895871SWei Ni *
7162a895871SWei Ni * Configure the SOC_THERM HW trip points, setting "THERMTRIP"
7172510aa56SWei Ni * "THROTTLE" trip points , using "thermtrips", "critical" or "hot"
7182510aa56SWei Ni * type trip_temp
719ce0dbf04SWei Ni * from thermal zone.
720ce0dbf04SWei Ni * After they have been configured, THERMTRIP or THROTTLE will take
721ce0dbf04SWei Ni * action when the configured SoC thermal sensor group reaches a
7222a895871SWei Ni * certain temperature.
7232a895871SWei Ni *
7242a895871SWei Ni * Return: 0 upon success, or a negative error code on failure.
7252a895871SWei Ni * "Success" does not mean that trips was enabled; it could also
7262a895871SWei Ni * mean that no node was found in DT.
7272a895871SWei Ni * THERMTRIP has been enabled successfully when a message similar to
7282a895871SWei Ni * this one appears on the serial console:
7292a895871SWei Ni * "thermtrip: will shut down when sensor group XXX reaches YYYYYY mC"
730ce0dbf04SWei Ni * THROTTLE has been enabled successfully when a message similar to
731ce0dbf04SWei Ni * this one appears on the serial console:
732ce0dbf04SWei Ni * ""throttrip: will throttle when sensor group XXX reaches YYYYYY mC"
7332a895871SWei Ni */
tegra_soctherm_set_hwtrips(struct device * dev,const struct tegra_tsensor_group * sg,struct thermal_zone_device * tz)7342a895871SWei Ni static int tegra_soctherm_set_hwtrips(struct device *dev,
7352a895871SWei Ni const struct tegra_tsensor_group *sg,
7362a895871SWei Ni struct thermal_zone_device *tz)
7372a895871SWei Ni {
738ce0dbf04SWei Ni struct tegra_soctherm *ts = dev_get_drvdata(dev);
739ce0dbf04SWei Ni struct soctherm_throt_cfg *stc;
7402510aa56SWei Ni int i, trip, temperature, ret;
7412a895871SWei Ni
7422510aa56SWei Ni /* Get thermtrips. If missing, try to get critical trips. */
7432510aa56SWei Ni temperature = tsensor_group_thermtrip_get(ts, sg->id);
7442510aa56SWei Ni if (min_low_temp == temperature)
7455f28ecc1SJon Hunter if (thermal_zone_get_crit_temp(tz, &temperature))
7462510aa56SWei Ni temperature = max_high_temp;
7472a895871SWei Ni
7482a895871SWei Ni ret = thermtrip_program(dev, sg, temperature);
7492a895871SWei Ni if (ret) {
7502510aa56SWei Ni dev_err(dev, "thermtrip: %s: error during enable\n", sg->name);
7512a895871SWei Ni return ret;
7522a895871SWei Ni }
7532a895871SWei Ni
7542510aa56SWei Ni dev_info(dev, "thermtrip: will shut down when %s reaches %d mC\n",
7552a895871SWei Ni sg->name, temperature);
7562a895871SWei Ni
757ce0dbf04SWei Ni ret = get_hot_temp(tz, &trip, &temperature);
758ce0dbf04SWei Ni if (ret) {
759cd28561dSWei Ni dev_info(dev, "throttrip: %s: missing hot temperature\n",
760ce0dbf04SWei Ni sg->name);
761ce0dbf04SWei Ni return 0;
762ce0dbf04SWei Ni }
763ce0dbf04SWei Ni
7641dcc242cSWei Ni for (i = 0; i < THROTTLE_OC1; i++) {
765ce0dbf04SWei Ni struct thermal_cooling_device *cdev;
766ce0dbf04SWei Ni
767ce0dbf04SWei Ni if (!ts->throt_cfgs[i].init)
768ce0dbf04SWei Ni continue;
769ce0dbf04SWei Ni
770ce0dbf04SWei Ni cdev = ts->throt_cfgs[i].cdev;
771ce0dbf04SWei Ni if (get_thermal_instance(tz, cdev, trip))
772ce0dbf04SWei Ni stc = find_throttle_cfg_by_name(ts, cdev->type);
773ce0dbf04SWei Ni else
774ce0dbf04SWei Ni continue;
775ce0dbf04SWei Ni
776ce0dbf04SWei Ni ret = throttrip_program(dev, sg, stc, temperature);
777ce0dbf04SWei Ni if (ret) {
778ce0dbf04SWei Ni dev_err(dev, "throttrip: %s: error during enable\n",
779ce0dbf04SWei Ni sg->name);
780ce0dbf04SWei Ni return ret;
781ce0dbf04SWei Ni }
782ce0dbf04SWei Ni
783ce0dbf04SWei Ni dev_info(dev,
784ce0dbf04SWei Ni "throttrip: will throttle when %s reaches %d mC\n",
785ce0dbf04SWei Ni sg->name, temperature);
786ce0dbf04SWei Ni break;
787ce0dbf04SWei Ni }
788ce0dbf04SWei Ni
789ce0dbf04SWei Ni if (i == THROTTLE_SIZE)
790cd28561dSWei Ni dev_info(dev, "throttrip: %s: missing throttle cdev\n",
791ce0dbf04SWei Ni sg->name);
792ce0dbf04SWei Ni
7932a895871SWei Ni return 0;
7942a895871SWei Ni }
7952a895871SWei Ni
soctherm_thermal_isr(int irq,void * dev_id)796d7180be0SWei Ni static irqreturn_t soctherm_thermal_isr(int irq, void *dev_id)
797d7180be0SWei Ni {
798d7180be0SWei Ni struct tegra_soctherm *ts = dev_id;
799d7180be0SWei Ni u32 r;
800d7180be0SWei Ni
8015c9d6ac2SWei Ni /* Case for no lock:
8025c9d6ac2SWei Ni * Although interrupts are enabled in set_trips, there is still no need
8035c9d6ac2SWei Ni * to lock here because the interrupts are disabled before programming
8045c9d6ac2SWei Ni * new trip points. Hence there cant be a interrupt on the same sensor.
8055c9d6ac2SWei Ni * An interrupt can however occur on a sensor while trips are being
8065c9d6ac2SWei Ni * programmed on a different one. This beign a LEVEL interrupt won't
8075c9d6ac2SWei Ni * cause a new interrupt but this is taken care of by the re-reading of
8085c9d6ac2SWei Ni * the STATUS register in the thread function.
8095c9d6ac2SWei Ni */
810d7180be0SWei Ni r = readl(ts->regs + THERMCTL_INTR_STATUS);
811d7180be0SWei Ni writel(r, ts->regs + THERMCTL_INTR_DISABLE);
812d7180be0SWei Ni
813d7180be0SWei Ni return IRQ_WAKE_THREAD;
814d7180be0SWei Ni }
815d7180be0SWei Ni
816d7180be0SWei Ni /**
817d7180be0SWei Ni * soctherm_thermal_isr_thread() - Handles a thermal interrupt request
818d7180be0SWei Ni * @irq: The interrupt number being requested; not used
819d7180be0SWei Ni * @dev_id: Opaque pointer to tegra_soctherm;
820d7180be0SWei Ni *
821d7180be0SWei Ni * Clears the interrupt status register if there are expected
822d7180be0SWei Ni * interrupt bits set.
823d7180be0SWei Ni * The interrupt(s) are then handled by updating the corresponding
824d7180be0SWei Ni * thermal zones.
825d7180be0SWei Ni *
826d7180be0SWei Ni * An error is logged if any unexpected interrupt bits are set.
827d7180be0SWei Ni *
828d7180be0SWei Ni * Disabled interrupts are re-enabled.
829d7180be0SWei Ni *
830d7180be0SWei Ni * Return: %IRQ_HANDLED. Interrupt was handled and no further processing
831d7180be0SWei Ni * is needed.
832d7180be0SWei Ni */
soctherm_thermal_isr_thread(int irq,void * dev_id)833d7180be0SWei Ni static irqreturn_t soctherm_thermal_isr_thread(int irq, void *dev_id)
834d7180be0SWei Ni {
835d7180be0SWei Ni struct tegra_soctherm *ts = dev_id;
836d7180be0SWei Ni struct thermal_zone_device *tz;
837d7180be0SWei Ni u32 st, ex = 0, cp = 0, gp = 0, pl = 0, me = 0;
838d7180be0SWei Ni
839d7180be0SWei Ni st = readl(ts->regs + THERMCTL_INTR_STATUS);
840d7180be0SWei Ni
841d7180be0SWei Ni /* deliberately clear expected interrupts handled in SW */
842d7180be0SWei Ni cp |= st & TH_INTR_CD0_MASK;
843d7180be0SWei Ni cp |= st & TH_INTR_CU0_MASK;
844d7180be0SWei Ni
845d7180be0SWei Ni gp |= st & TH_INTR_GD0_MASK;
846d7180be0SWei Ni gp |= st & TH_INTR_GU0_MASK;
847d7180be0SWei Ni
848d7180be0SWei Ni pl |= st & TH_INTR_PD0_MASK;
849d7180be0SWei Ni pl |= st & TH_INTR_PU0_MASK;
850d7180be0SWei Ni
851d7180be0SWei Ni me |= st & TH_INTR_MD0_MASK;
852d7180be0SWei Ni me |= st & TH_INTR_MU0_MASK;
853d7180be0SWei Ni
854d7180be0SWei Ni ex |= cp | gp | pl | me;
855d7180be0SWei Ni if (ex) {
856d7180be0SWei Ni writel(ex, ts->regs + THERMCTL_INTR_STATUS);
857d7180be0SWei Ni st &= ~ex;
858d7180be0SWei Ni
859d7180be0SWei Ni if (cp) {
860d7180be0SWei Ni tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_CPU];
861d7180be0SWei Ni thermal_zone_device_update(tz,
862d7180be0SWei Ni THERMAL_EVENT_UNSPECIFIED);
863d7180be0SWei Ni }
864d7180be0SWei Ni
865d7180be0SWei Ni if (gp) {
866d7180be0SWei Ni tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_GPU];
867d7180be0SWei Ni thermal_zone_device_update(tz,
868d7180be0SWei Ni THERMAL_EVENT_UNSPECIFIED);
869d7180be0SWei Ni }
870d7180be0SWei Ni
871d7180be0SWei Ni if (pl) {
872d7180be0SWei Ni tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_PLLX];
873d7180be0SWei Ni thermal_zone_device_update(tz,
874d7180be0SWei Ni THERMAL_EVENT_UNSPECIFIED);
875d7180be0SWei Ni }
876d7180be0SWei Ni
877d7180be0SWei Ni if (me) {
878d7180be0SWei Ni tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_MEM];
879d7180be0SWei Ni thermal_zone_device_update(tz,
880d7180be0SWei Ni THERMAL_EVENT_UNSPECIFIED);
881d7180be0SWei Ni }
882d7180be0SWei Ni }
883d7180be0SWei Ni
884d7180be0SWei Ni /* deliberately ignore expected interrupts NOT handled in SW */
885d7180be0SWei Ni ex |= TH_INTR_IGNORE_MASK;
886d7180be0SWei Ni st &= ~ex;
887d7180be0SWei Ni
888d7180be0SWei Ni if (st) {
889d7180be0SWei Ni /* Whine about any other unexpected INTR bits still set */
890d7180be0SWei Ni pr_err("soctherm: Ignored unexpected INTRs 0x%08x\n", st);
891d7180be0SWei Ni writel(st, ts->regs + THERMCTL_INTR_STATUS);
892d7180be0SWei Ni }
893d7180be0SWei Ni
894d7180be0SWei Ni return IRQ_HANDLED;
895d7180be0SWei Ni }
896d7180be0SWei Ni
8974a04beb1SWei Ni /**
8984a04beb1SWei Ni * soctherm_oc_intr_enable() - Enables the soctherm over-current interrupt
8996a6d634cSAmit Kucheria * @ts: pointer to a struct tegra_soctherm
9004a04beb1SWei Ni * @alarm: The soctherm throttle id
9014a04beb1SWei Ni * @enable: Flag indicating enable the soctherm over-current
9024a04beb1SWei Ni * interrupt or disable it
9034a04beb1SWei Ni *
9044a04beb1SWei Ni * Enables a specific over-current pins @alarm to raise an interrupt if the flag
9054a04beb1SWei Ni * is set and the alarm corresponds to OC1, OC2, OC3, or OC4.
9064a04beb1SWei Ni */
soctherm_oc_intr_enable(struct tegra_soctherm * ts,enum soctherm_throttle_id alarm,bool enable)9074a04beb1SWei Ni static void soctherm_oc_intr_enable(struct tegra_soctherm *ts,
9084a04beb1SWei Ni enum soctherm_throttle_id alarm,
9094a04beb1SWei Ni bool enable)
9104a04beb1SWei Ni {
9114a04beb1SWei Ni u32 r;
9124a04beb1SWei Ni
9134a04beb1SWei Ni if (!enable)
9144a04beb1SWei Ni return;
9154a04beb1SWei Ni
9164a04beb1SWei Ni r = readl(ts->regs + OC_INTR_ENABLE);
9174a04beb1SWei Ni switch (alarm) {
9184a04beb1SWei Ni case THROTTLE_OC1:
9194a04beb1SWei Ni r = REG_SET_MASK(r, OC_INTR_OC1_MASK, 1);
9204a04beb1SWei Ni break;
9214a04beb1SWei Ni case THROTTLE_OC2:
9224a04beb1SWei Ni r = REG_SET_MASK(r, OC_INTR_OC2_MASK, 1);
9234a04beb1SWei Ni break;
9244a04beb1SWei Ni case THROTTLE_OC3:
9254a04beb1SWei Ni r = REG_SET_MASK(r, OC_INTR_OC3_MASK, 1);
9264a04beb1SWei Ni break;
9274a04beb1SWei Ni case THROTTLE_OC4:
9284a04beb1SWei Ni r = REG_SET_MASK(r, OC_INTR_OC4_MASK, 1);
9294a04beb1SWei Ni break;
9304a04beb1SWei Ni default:
9314a04beb1SWei Ni r = 0;
9324a04beb1SWei Ni break;
9334a04beb1SWei Ni }
9344a04beb1SWei Ni writel(r, ts->regs + OC_INTR_ENABLE);
9354a04beb1SWei Ni }
9364a04beb1SWei Ni
9374a04beb1SWei Ni /**
9384a04beb1SWei Ni * soctherm_handle_alarm() - Handles soctherm alarms
9394a04beb1SWei Ni * @alarm: The soctherm throttle id
9404a04beb1SWei Ni *
9414a04beb1SWei Ni * "Handles" over-current alarms (OC1, OC2, OC3, and OC4) by printing
9424a04beb1SWei Ni * a warning or informative message.
9434a04beb1SWei Ni *
9444a04beb1SWei Ni * Return: -EINVAL for @alarm = THROTTLE_OC3, otherwise 0 (success).
9454a04beb1SWei Ni */
soctherm_handle_alarm(enum soctherm_throttle_id alarm)9464a04beb1SWei Ni static int soctherm_handle_alarm(enum soctherm_throttle_id alarm)
9474a04beb1SWei Ni {
9484a04beb1SWei Ni int rv = -EINVAL;
9494a04beb1SWei Ni
9504a04beb1SWei Ni switch (alarm) {
9514a04beb1SWei Ni case THROTTLE_OC1:
9524a04beb1SWei Ni pr_debug("soctherm: Successfully handled OC1 alarm\n");
9534a04beb1SWei Ni rv = 0;
9544a04beb1SWei Ni break;
9554a04beb1SWei Ni
9564a04beb1SWei Ni case THROTTLE_OC2:
9574a04beb1SWei Ni pr_debug("soctherm: Successfully handled OC2 alarm\n");
9584a04beb1SWei Ni rv = 0;
9594a04beb1SWei Ni break;
9604a04beb1SWei Ni
9614a04beb1SWei Ni case THROTTLE_OC3:
9624a04beb1SWei Ni pr_debug("soctherm: Successfully handled OC3 alarm\n");
9634a04beb1SWei Ni rv = 0;
9644a04beb1SWei Ni break;
9654a04beb1SWei Ni
9664a04beb1SWei Ni case THROTTLE_OC4:
9674a04beb1SWei Ni pr_debug("soctherm: Successfully handled OC4 alarm\n");
9684a04beb1SWei Ni rv = 0;
9694a04beb1SWei Ni break;
9704a04beb1SWei Ni
9714a04beb1SWei Ni default:
9724a04beb1SWei Ni break;
9734a04beb1SWei Ni }
9744a04beb1SWei Ni
9754a04beb1SWei Ni if (rv)
9764a04beb1SWei Ni pr_err("soctherm: ERROR in handling %s alarm\n",
9774a04beb1SWei Ni throt_names[alarm]);
9784a04beb1SWei Ni
9794a04beb1SWei Ni return rv;
9804a04beb1SWei Ni }
9814a04beb1SWei Ni
9824a04beb1SWei Ni /**
9834a04beb1SWei Ni * soctherm_edp_isr_thread() - log an over-current interrupt request
9844a04beb1SWei Ni * @irq: OC irq number. Currently not being used. See description
9854a04beb1SWei Ni * @arg: a void pointer for callback, currently not being used
9864a04beb1SWei Ni *
9874a04beb1SWei Ni * Over-current events are handled in hardware. This function is called to log
9884a04beb1SWei Ni * and handle any OC events that happened. Additionally, it checks every
9894a04beb1SWei Ni * over-current interrupt registers for registers are set but
9904a04beb1SWei Ni * was not expected (i.e. any discrepancy in interrupt status) by the function,
9914a04beb1SWei Ni * the discrepancy will logged.
9924a04beb1SWei Ni *
9934a04beb1SWei Ni * Return: %IRQ_HANDLED
9944a04beb1SWei Ni */
soctherm_edp_isr_thread(int irq,void * arg)9954a04beb1SWei Ni static irqreturn_t soctherm_edp_isr_thread(int irq, void *arg)
9964a04beb1SWei Ni {
9974a04beb1SWei Ni struct tegra_soctherm *ts = arg;
9984a04beb1SWei Ni u32 st, ex, oc1, oc2, oc3, oc4;
9994a04beb1SWei Ni
10004a04beb1SWei Ni st = readl(ts->regs + OC_INTR_STATUS);
10014a04beb1SWei Ni
10024a04beb1SWei Ni /* deliberately clear expected interrupts handled in SW */
10034a04beb1SWei Ni oc1 = st & OC_INTR_OC1_MASK;
10044a04beb1SWei Ni oc2 = st & OC_INTR_OC2_MASK;
10054a04beb1SWei Ni oc3 = st & OC_INTR_OC3_MASK;
10064a04beb1SWei Ni oc4 = st & OC_INTR_OC4_MASK;
10074a04beb1SWei Ni ex = oc1 | oc2 | oc3 | oc4;
10084a04beb1SWei Ni
10094a04beb1SWei Ni pr_err("soctherm: OC ALARM 0x%08x\n", ex);
10104a04beb1SWei Ni if (ex) {
10114a04beb1SWei Ni writel(st, ts->regs + OC_INTR_STATUS);
10124a04beb1SWei Ni st &= ~ex;
10134a04beb1SWei Ni
10144a04beb1SWei Ni if (oc1 && !soctherm_handle_alarm(THROTTLE_OC1))
10154a04beb1SWei Ni soctherm_oc_intr_enable(ts, THROTTLE_OC1, true);
10164a04beb1SWei Ni
10174a04beb1SWei Ni if (oc2 && !soctherm_handle_alarm(THROTTLE_OC2))
10184a04beb1SWei Ni soctherm_oc_intr_enable(ts, THROTTLE_OC2, true);
10194a04beb1SWei Ni
10204a04beb1SWei Ni if (oc3 && !soctherm_handle_alarm(THROTTLE_OC3))
10214a04beb1SWei Ni soctherm_oc_intr_enable(ts, THROTTLE_OC3, true);
10224a04beb1SWei Ni
10234a04beb1SWei Ni if (oc4 && !soctherm_handle_alarm(THROTTLE_OC4))
10244a04beb1SWei Ni soctherm_oc_intr_enable(ts, THROTTLE_OC4, true);
10254a04beb1SWei Ni
10264a04beb1SWei Ni if (oc1 && soc_irq_cdata.irq_enable & BIT(0))
10274a04beb1SWei Ni handle_nested_irq(
10284a04beb1SWei Ni irq_find_mapping(soc_irq_cdata.domain, 0));
10294a04beb1SWei Ni
10304a04beb1SWei Ni if (oc2 && soc_irq_cdata.irq_enable & BIT(1))
10314a04beb1SWei Ni handle_nested_irq(
10324a04beb1SWei Ni irq_find_mapping(soc_irq_cdata.domain, 1));
10334a04beb1SWei Ni
10344a04beb1SWei Ni if (oc3 && soc_irq_cdata.irq_enable & BIT(2))
10354a04beb1SWei Ni handle_nested_irq(
10364a04beb1SWei Ni irq_find_mapping(soc_irq_cdata.domain, 2));
10374a04beb1SWei Ni
10384a04beb1SWei Ni if (oc4 && soc_irq_cdata.irq_enable & BIT(3))
10394a04beb1SWei Ni handle_nested_irq(
10404a04beb1SWei Ni irq_find_mapping(soc_irq_cdata.domain, 3));
10414a04beb1SWei Ni }
10424a04beb1SWei Ni
10434a04beb1SWei Ni if (st) {
10444a04beb1SWei Ni pr_err("soctherm: Ignored unexpected OC ALARM 0x%08x\n", st);
10454a04beb1SWei Ni writel(st, ts->regs + OC_INTR_STATUS);
10464a04beb1SWei Ni }
10474a04beb1SWei Ni
10484a04beb1SWei Ni return IRQ_HANDLED;
10494a04beb1SWei Ni }
10504a04beb1SWei Ni
10514a04beb1SWei Ni /**
10524a04beb1SWei Ni * soctherm_edp_isr() - Disables any active interrupts
10534a04beb1SWei Ni * @irq: The interrupt request number
10544a04beb1SWei Ni * @arg: Opaque pointer to an argument
10554a04beb1SWei Ni *
10564a04beb1SWei Ni * Writes to the OC_INTR_DISABLE register the over current interrupt status,
10574a04beb1SWei Ni * masking any asserted interrupts. Doing this prevents the same interrupts
10584a04beb1SWei Ni * from triggering this isr repeatedly. The thread woken by this isr will
10594a04beb1SWei Ni * handle asserted interrupts and subsequently unmask/re-enable them.
10604a04beb1SWei Ni *
10614a04beb1SWei Ni * The OC_INTR_DISABLE register indicates which OC interrupts
10624a04beb1SWei Ni * have been disabled.
10634a04beb1SWei Ni *
10644a04beb1SWei Ni * Return: %IRQ_WAKE_THREAD, handler requests to wake the handler thread
10654a04beb1SWei Ni */
soctherm_edp_isr(int irq,void * arg)10664a04beb1SWei Ni static irqreturn_t soctherm_edp_isr(int irq, void *arg)
10674a04beb1SWei Ni {
10684a04beb1SWei Ni struct tegra_soctherm *ts = arg;
10694a04beb1SWei Ni u32 r;
10704a04beb1SWei Ni
10714a04beb1SWei Ni if (!ts)
10724a04beb1SWei Ni return IRQ_NONE;
10734a04beb1SWei Ni
10744a04beb1SWei Ni r = readl(ts->regs + OC_INTR_STATUS);
10754a04beb1SWei Ni writel(r, ts->regs + OC_INTR_DISABLE);
10764a04beb1SWei Ni
10774a04beb1SWei Ni return IRQ_WAKE_THREAD;
10784a04beb1SWei Ni }
10794a04beb1SWei Ni
10804a04beb1SWei Ni /**
10814a04beb1SWei Ni * soctherm_oc_irq_lock() - locks the over-current interrupt request
10824a04beb1SWei Ni * @data: Interrupt request data
10834a04beb1SWei Ni *
10844a04beb1SWei Ni * Looks up the chip data from @data and locks the mutex associated with
10854a04beb1SWei Ni * a particular over-current interrupt request.
10864a04beb1SWei Ni */
soctherm_oc_irq_lock(struct irq_data * data)10874a04beb1SWei Ni static void soctherm_oc_irq_lock(struct irq_data *data)
10884a04beb1SWei Ni {
10894a04beb1SWei Ni struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
10904a04beb1SWei Ni
10914a04beb1SWei Ni mutex_lock(&d->irq_lock);
10924a04beb1SWei Ni }
10934a04beb1SWei Ni
10944a04beb1SWei Ni /**
10954a04beb1SWei Ni * soctherm_oc_irq_sync_unlock() - Unlocks the OC interrupt request
10964a04beb1SWei Ni * @data: Interrupt request data
10974a04beb1SWei Ni *
10984a04beb1SWei Ni * Looks up the interrupt request data @data and unlocks the mutex associated
10994a04beb1SWei Ni * with a particular over-current interrupt request.
11004a04beb1SWei Ni */
soctherm_oc_irq_sync_unlock(struct irq_data * data)11014a04beb1SWei Ni static void soctherm_oc_irq_sync_unlock(struct irq_data *data)
11024a04beb1SWei Ni {
11034a04beb1SWei Ni struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
11044a04beb1SWei Ni
11054a04beb1SWei Ni mutex_unlock(&d->irq_lock);
11064a04beb1SWei Ni }
11074a04beb1SWei Ni
11084a04beb1SWei Ni /**
11094a04beb1SWei Ni * soctherm_oc_irq_enable() - Enables the SOC_THERM over-current interrupt queue
11104a04beb1SWei Ni * @data: irq_data structure of the chip
11114a04beb1SWei Ni *
11124a04beb1SWei Ni * Sets the irq_enable bit of SOC_THERM allowing SOC_THERM
11134a04beb1SWei Ni * to respond to over-current interrupts.
11144a04beb1SWei Ni *
11154a04beb1SWei Ni */
soctherm_oc_irq_enable(struct irq_data * data)11164a04beb1SWei Ni static void soctherm_oc_irq_enable(struct irq_data *data)
11174a04beb1SWei Ni {
11184a04beb1SWei Ni struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
11194a04beb1SWei Ni
11204a04beb1SWei Ni d->irq_enable |= BIT(data->hwirq);
11214a04beb1SWei Ni }
11224a04beb1SWei Ni
11234a04beb1SWei Ni /**
11244a04beb1SWei Ni * soctherm_oc_irq_disable() - Disables overcurrent interrupt requests
11256a6d634cSAmit Kucheria * @data: The interrupt request information
11264a04beb1SWei Ni *
11274a04beb1SWei Ni * Clears the interrupt request enable bit of the overcurrent
11284a04beb1SWei Ni * interrupt request chip data.
11294a04beb1SWei Ni *
11304a04beb1SWei Ni * Return: Nothing is returned (void)
11314a04beb1SWei Ni */
soctherm_oc_irq_disable(struct irq_data * data)11324a04beb1SWei Ni static void soctherm_oc_irq_disable(struct irq_data *data)
11334a04beb1SWei Ni {
11344a04beb1SWei Ni struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
11354a04beb1SWei Ni
11364a04beb1SWei Ni d->irq_enable &= ~BIT(data->hwirq);
11374a04beb1SWei Ni }
11384a04beb1SWei Ni
soctherm_oc_irq_set_type(struct irq_data * data,unsigned int type)11394a04beb1SWei Ni static int soctherm_oc_irq_set_type(struct irq_data *data, unsigned int type)
11404a04beb1SWei Ni {
11414a04beb1SWei Ni return 0;
11424a04beb1SWei Ni }
11434a04beb1SWei Ni
11444a04beb1SWei Ni /**
11454a04beb1SWei Ni * soctherm_oc_irq_map() - SOC_THERM interrupt request domain mapper
11464a04beb1SWei Ni * @h: Interrupt request domain
11474a04beb1SWei Ni * @virq: Virtual interrupt request number
11484a04beb1SWei Ni * @hw: Hardware interrupt request number
11494a04beb1SWei Ni *
11504a04beb1SWei Ni * Mapping callback function for SOC_THERM's irq_domain. When a SOC_THERM
11514a04beb1SWei Ni * interrupt request is called, the irq_domain takes the request's virtual
11524a04beb1SWei Ni * request number (much like a virtual memory address) and maps it to a
11534a04beb1SWei Ni * physical hardware request number.
11544a04beb1SWei Ni *
11554a04beb1SWei Ni * When a mapping doesn't already exist for a virtual request number, the
11564a04beb1SWei Ni * irq_domain calls this function to associate the virtual request number with
11574a04beb1SWei Ni * a hardware request number.
11584a04beb1SWei Ni *
11594a04beb1SWei Ni * Return: 0
11604a04beb1SWei Ni */
soctherm_oc_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)11614a04beb1SWei Ni static int soctherm_oc_irq_map(struct irq_domain *h, unsigned int virq,
11624a04beb1SWei Ni irq_hw_number_t hw)
11634a04beb1SWei Ni {
11644a04beb1SWei Ni struct soctherm_oc_irq_chip_data *data = h->host_data;
11654a04beb1SWei Ni
11664a04beb1SWei Ni irq_set_chip_data(virq, data);
11674a04beb1SWei Ni irq_set_chip(virq, &data->irq_chip);
11684a04beb1SWei Ni irq_set_nested_thread(virq, 1);
11694a04beb1SWei Ni return 0;
11704a04beb1SWei Ni }
11714a04beb1SWei Ni
11724a04beb1SWei Ni /**
11734a04beb1SWei Ni * soctherm_irq_domain_xlate_twocell() - xlate for soctherm interrupts
11744a04beb1SWei Ni * @d: Interrupt request domain
11756a6d634cSAmit Kucheria * @ctrlr: Controller device tree node
11764a04beb1SWei Ni * @intspec: Array of u32s from DTs "interrupt" property
11774a04beb1SWei Ni * @intsize: Number of values inside the intspec array
11784a04beb1SWei Ni * @out_hwirq: HW IRQ value associated with this interrupt
11794a04beb1SWei Ni * @out_type: The IRQ SENSE type for this interrupt.
11804a04beb1SWei Ni *
11814a04beb1SWei Ni * This Device Tree IRQ specifier translation function will translate a
11824a04beb1SWei Ni * specific "interrupt" as defined by 2 DT values where the cell values map
11834a04beb1SWei Ni * the hwirq number + 1 and linux irq flags. Since the output is the hwirq
11844a04beb1SWei Ni * number, this function will subtract 1 from the value listed in DT.
11854a04beb1SWei Ni *
11864a04beb1SWei Ni * Return: 0
11874a04beb1SWei Ni */
soctherm_irq_domain_xlate_twocell(struct irq_domain * d,struct device_node * ctrlr,const u32 * intspec,unsigned int intsize,irq_hw_number_t * out_hwirq,unsigned int * out_type)11884a04beb1SWei Ni static int soctherm_irq_domain_xlate_twocell(struct irq_domain *d,
11894a04beb1SWei Ni struct device_node *ctrlr, const u32 *intspec, unsigned int intsize,
11904a04beb1SWei Ni irq_hw_number_t *out_hwirq, unsigned int *out_type)
11914a04beb1SWei Ni {
11924a04beb1SWei Ni if (WARN_ON(intsize < 2))
11934a04beb1SWei Ni return -EINVAL;
11944a04beb1SWei Ni
11954a04beb1SWei Ni /*
11964a04beb1SWei Ni * The HW value is 1 index less than the DT IRQ values.
11974a04beb1SWei Ni * i.e. OC4 goes to HW index 3.
11984a04beb1SWei Ni */
11994a04beb1SWei Ni *out_hwirq = intspec[0] - 1;
12004a04beb1SWei Ni *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
12014a04beb1SWei Ni return 0;
12024a04beb1SWei Ni }
12034a04beb1SWei Ni
12044a04beb1SWei Ni static const struct irq_domain_ops soctherm_oc_domain_ops = {
12054a04beb1SWei Ni .map = soctherm_oc_irq_map,
12064a04beb1SWei Ni .xlate = soctherm_irq_domain_xlate_twocell,
12074a04beb1SWei Ni };
12084a04beb1SWei Ni
12094a04beb1SWei Ni /**
12104a04beb1SWei Ni * soctherm_oc_int_init() - Initial enabling of the over
12114a04beb1SWei Ni * current interrupts
12124a04beb1SWei Ni * @np: The devicetree node for soctherm
12134a04beb1SWei Ni * @num_irqs: The number of new interrupt requests
12144a04beb1SWei Ni *
12154a04beb1SWei Ni * Sets the over current interrupt request chip data
12164a04beb1SWei Ni *
12174a04beb1SWei Ni * Return: 0 on success or if overcurrent interrupts are not enabled,
12184a04beb1SWei Ni * -ENOMEM (out of memory), or irq_base if the function failed to
12194a04beb1SWei Ni * allocate the irqs
12204a04beb1SWei Ni */
soctherm_oc_int_init(struct device_node * np,int num_irqs)12214a04beb1SWei Ni static int soctherm_oc_int_init(struct device_node *np, int num_irqs)
12224a04beb1SWei Ni {
12234a04beb1SWei Ni if (!num_irqs) {
12244a04beb1SWei Ni pr_info("%s(): OC interrupts are not enabled\n", __func__);
12254a04beb1SWei Ni return 0;
12264a04beb1SWei Ni }
12274a04beb1SWei Ni
12284a04beb1SWei Ni mutex_init(&soc_irq_cdata.irq_lock);
12294a04beb1SWei Ni soc_irq_cdata.irq_enable = 0;
12304a04beb1SWei Ni
12314a04beb1SWei Ni soc_irq_cdata.irq_chip.name = "soc_therm_oc";
12324a04beb1SWei Ni soc_irq_cdata.irq_chip.irq_bus_lock = soctherm_oc_irq_lock;
12334a04beb1SWei Ni soc_irq_cdata.irq_chip.irq_bus_sync_unlock =
12344a04beb1SWei Ni soctherm_oc_irq_sync_unlock;
12354a04beb1SWei Ni soc_irq_cdata.irq_chip.irq_disable = soctherm_oc_irq_disable;
12364a04beb1SWei Ni soc_irq_cdata.irq_chip.irq_enable = soctherm_oc_irq_enable;
12374a04beb1SWei Ni soc_irq_cdata.irq_chip.irq_set_type = soctherm_oc_irq_set_type;
12384a04beb1SWei Ni soc_irq_cdata.irq_chip.irq_set_wake = NULL;
12394a04beb1SWei Ni
12404a04beb1SWei Ni soc_irq_cdata.domain = irq_domain_add_linear(np, num_irqs,
12414a04beb1SWei Ni &soctherm_oc_domain_ops,
12424a04beb1SWei Ni &soc_irq_cdata);
12434a04beb1SWei Ni
12444a04beb1SWei Ni if (!soc_irq_cdata.domain) {
12454a04beb1SWei Ni pr_err("%s: Failed to create IRQ domain\n", __func__);
12464a04beb1SWei Ni return -ENOMEM;
12474a04beb1SWei Ni }
12484a04beb1SWei Ni
12494a04beb1SWei Ni pr_debug("%s(): OC interrupts enabled successful\n", __func__);
12504a04beb1SWei Ni return 0;
12514a04beb1SWei Ni }
12524a04beb1SWei Ni
1253d753b22dSWei Ni #ifdef CONFIG_DEBUG_FS
regs_show(struct seq_file * s,void * data)1254d753b22dSWei Ni static int regs_show(struct seq_file *s, void *data)
1255d753b22dSWei Ni {
1256d753b22dSWei Ni struct platform_device *pdev = s->private;
1257d753b22dSWei Ni struct tegra_soctherm *ts = platform_get_drvdata(pdev);
1258d753b22dSWei Ni const struct tegra_tsensor *tsensors = ts->soc->tsensors;
12592a895871SWei Ni const struct tegra_tsensor_group **ttgs = ts->soc->ttgs;
1260d753b22dSWei Ni u32 r, state;
1261ce0dbf04SWei Ni int i, level;
1262d753b22dSWei Ni
1263d753b22dSWei Ni seq_puts(s, "-----TSENSE (convert HW)-----\n");
1264d753b22dSWei Ni
1265d753b22dSWei Ni for (i = 0; i < ts->soc->num_tsensors; i++) {
1266d753b22dSWei Ni r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG1);
1267d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_CONFIG1_TEMP_ENABLE);
1268d753b22dSWei Ni
1269d753b22dSWei Ni seq_printf(s, "%s: ", tsensors[i].name);
1270d753b22dSWei Ni seq_printf(s, "En(%d) ", state);
1271d753b22dSWei Ni
1272d753b22dSWei Ni if (!state) {
1273d753b22dSWei Ni seq_puts(s, "\n");
1274d753b22dSWei Ni continue;
1275d753b22dSWei Ni }
1276d753b22dSWei Ni
1277d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_CONFIG1_TIDDQ_EN_MASK);
1278d753b22dSWei Ni seq_printf(s, "tiddq(%d) ", state);
1279d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_CONFIG1_TEN_COUNT_MASK);
1280d753b22dSWei Ni seq_printf(s, "ten_count(%d) ", state);
1281d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_CONFIG1_TSAMPLE_MASK);
1282d753b22dSWei Ni seq_printf(s, "tsample(%d) ", state + 1);
1283d753b22dSWei Ni
1284d753b22dSWei Ni r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS1);
1285d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_VALID_MASK);
1286d753b22dSWei Ni seq_printf(s, "Temp(%d/", state);
1287d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_MASK);
1288d753b22dSWei Ni seq_printf(s, "%d) ", translate_temp(state));
1289d753b22dSWei Ni
1290d753b22dSWei Ni r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS0);
1291d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_STATUS0_VALID_MASK);
1292d753b22dSWei Ni seq_printf(s, "Capture(%d/", state);
1293d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_STATUS0_CAPTURE_MASK);
1294d753b22dSWei Ni seq_printf(s, "%d) ", state);
1295d753b22dSWei Ni
1296d753b22dSWei Ni r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG0);
1297d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_CONFIG0_STOP);
1298d753b22dSWei Ni seq_printf(s, "Stop(%d) ", state);
1299d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_CONFIG0_TALL_MASK);
1300d753b22dSWei Ni seq_printf(s, "Tall(%d) ", state);
1301d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_CONFIG0_TCALC_OVER);
1302d753b22dSWei Ni seq_printf(s, "Over(%d/", state);
1303d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_CONFIG0_OVER);
1304d753b22dSWei Ni seq_printf(s, "%d/", state);
1305d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_CONFIG0_CPTR_OVER);
1306d753b22dSWei Ni seq_printf(s, "%d) ", state);
1307d753b22dSWei Ni
1308d753b22dSWei Ni r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG2);
1309d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMA_MASK);
1310d753b22dSWei Ni seq_printf(s, "Therm_A/B(%d/", state);
1311d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMB_MASK);
1312d753b22dSWei Ni seq_printf(s, "%d)\n", (s16)state);
1313d753b22dSWei Ni }
1314d753b22dSWei Ni
1315d753b22dSWei Ni r = readl(ts->regs + SENSOR_PDIV);
1316d753b22dSWei Ni seq_printf(s, "PDIV: 0x%x\n", r);
1317d753b22dSWei Ni
1318d753b22dSWei Ni r = readl(ts->regs + SENSOR_HOTSPOT_OFF);
1319d753b22dSWei Ni seq_printf(s, "HOTSPOT: 0x%x\n", r);
1320d753b22dSWei Ni
1321d753b22dSWei Ni seq_puts(s, "\n");
1322d753b22dSWei Ni seq_puts(s, "-----SOC_THERM-----\n");
1323d753b22dSWei Ni
1324d753b22dSWei Ni r = readl(ts->regs + SENSOR_TEMP1);
1325d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_TEMP1_CPU_TEMP_MASK);
1326d753b22dSWei Ni seq_printf(s, "Temperatures: CPU(%d) ", translate_temp(state));
1327d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_TEMP1_GPU_TEMP_MASK);
1328d753b22dSWei Ni seq_printf(s, " GPU(%d) ", translate_temp(state));
1329d753b22dSWei Ni r = readl(ts->regs + SENSOR_TEMP2);
1330d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_TEMP2_PLLX_TEMP_MASK);
1331d753b22dSWei Ni seq_printf(s, " PLLX(%d) ", translate_temp(state));
1332d753b22dSWei Ni state = REG_GET_MASK(r, SENSOR_TEMP2_MEM_TEMP_MASK);
1333d753b22dSWei Ni seq_printf(s, " MEM(%d)\n", translate_temp(state));
1334d753b22dSWei Ni
1335ce0dbf04SWei Ni for (i = 0; i < ts->soc->num_ttgs; i++) {
1336ce0dbf04SWei Ni seq_printf(s, "%s:\n", ttgs[i]->name);
1337ce0dbf04SWei Ni for (level = 0; level < 4; level++) {
1338ce0dbf04SWei Ni s32 v;
1339ce0dbf04SWei Ni u32 mask;
1340ce0dbf04SWei Ni u16 off = ttgs[i]->thermctl_lvl0_offset;
1341ce0dbf04SWei Ni
1342ce0dbf04SWei Ni r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
1343ce0dbf04SWei Ni
1344ce0dbf04SWei Ni mask = ttgs[i]->thermctl_lvl0_up_thresh_mask;
1345ce0dbf04SWei Ni state = REG_GET_MASK(r, mask);
1346ce0dbf04SWei Ni v = sign_extend32(state, ts->soc->bptt - 1);
1347ce0dbf04SWei Ni v *= ts->soc->thresh_grain;
1348ce0dbf04SWei Ni seq_printf(s, " %d: Up/Dn(%d /", level, v);
1349ce0dbf04SWei Ni
1350ce0dbf04SWei Ni mask = ttgs[i]->thermctl_lvl0_dn_thresh_mask;
1351ce0dbf04SWei Ni state = REG_GET_MASK(r, mask);
1352ce0dbf04SWei Ni v = sign_extend32(state, ts->soc->bptt - 1);
1353ce0dbf04SWei Ni v *= ts->soc->thresh_grain;
1354ce0dbf04SWei Ni seq_printf(s, "%d ) ", v);
1355ce0dbf04SWei Ni
1356ce0dbf04SWei Ni mask = THERMCTL_LVL0_CPU0_EN_MASK;
1357ce0dbf04SWei Ni state = REG_GET_MASK(r, mask);
1358ce0dbf04SWei Ni seq_printf(s, "En(%d) ", state);
1359ce0dbf04SWei Ni
1360ce0dbf04SWei Ni mask = THERMCTL_LVL0_CPU0_CPU_THROT_MASK;
1361ce0dbf04SWei Ni state = REG_GET_MASK(r, mask);
1362ce0dbf04SWei Ni seq_puts(s, "CPU Throt");
1363ce0dbf04SWei Ni if (!state)
1364ce0dbf04SWei Ni seq_printf(s, "(%s) ", "none");
1365ce0dbf04SWei Ni else if (state == THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT)
1366ce0dbf04SWei Ni seq_printf(s, "(%s) ", "L");
1367ce0dbf04SWei Ni else if (state == THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY)
1368ce0dbf04SWei Ni seq_printf(s, "(%s) ", "H");
1369ce0dbf04SWei Ni else
1370ce0dbf04SWei Ni seq_printf(s, "(%s) ", "H+L");
1371ce0dbf04SWei Ni
1372ce0dbf04SWei Ni mask = THERMCTL_LVL0_CPU0_GPU_THROT_MASK;
1373ce0dbf04SWei Ni state = REG_GET_MASK(r, mask);
1374ce0dbf04SWei Ni seq_puts(s, "GPU Throt");
1375ce0dbf04SWei Ni if (!state)
1376ce0dbf04SWei Ni seq_printf(s, "(%s) ", "none");
1377ce0dbf04SWei Ni else if (state == THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT)
1378ce0dbf04SWei Ni seq_printf(s, "(%s) ", "L");
1379ce0dbf04SWei Ni else if (state == THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY)
1380ce0dbf04SWei Ni seq_printf(s, "(%s) ", "H");
1381ce0dbf04SWei Ni else
1382ce0dbf04SWei Ni seq_printf(s, "(%s) ", "H+L");
1383ce0dbf04SWei Ni
1384ce0dbf04SWei Ni mask = THERMCTL_LVL0_CPU0_STATUS_MASK;
1385ce0dbf04SWei Ni state = REG_GET_MASK(r, mask);
1386ce0dbf04SWei Ni seq_printf(s, "Status(%s)\n",
1387ce0dbf04SWei Ni state == 0 ? "LO" :
1388ce0dbf04SWei Ni state == 1 ? "In" :
1389ce0dbf04SWei Ni state == 2 ? "Res" : "HI");
1390ce0dbf04SWei Ni }
1391ce0dbf04SWei Ni }
1392ce0dbf04SWei Ni
1393ce0dbf04SWei Ni r = readl(ts->regs + THERMCTL_STATS_CTL);
1394ce0dbf04SWei Ni seq_printf(s, "STATS: Up(%s) Dn(%s)\n",
1395ce0dbf04SWei Ni r & STATS_CTL_EN_UP ? "En" : "--",
1396ce0dbf04SWei Ni r & STATS_CTL_EN_DN ? "En" : "--");
1397ce0dbf04SWei Ni
1398ce0dbf04SWei Ni for (level = 0; level < 4; level++) {
1399ce0dbf04SWei Ni u16 off;
1400ce0dbf04SWei Ni
1401ce0dbf04SWei Ni off = THERMCTL_LVL0_UP_STATS;
1402ce0dbf04SWei Ni r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
1403ce0dbf04SWei Ni seq_printf(s, " Level_%d Up(%d) ", level, r);
1404ce0dbf04SWei Ni
1405ce0dbf04SWei Ni off = THERMCTL_LVL0_DN_STATS;
1406ce0dbf04SWei Ni r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
1407ce0dbf04SWei Ni seq_printf(s, "Dn(%d)\n", r);
1408ce0dbf04SWei Ni }
1409ce0dbf04SWei Ni
14102a895871SWei Ni r = readl(ts->regs + THERMCTL_THERMTRIP_CTL);
14112a895871SWei Ni state = REG_GET_MASK(r, ttgs[0]->thermtrip_any_en_mask);
14122a895871SWei Ni seq_printf(s, "Thermtrip Any En(%d)\n", state);
14132a895871SWei Ni for (i = 0; i < ts->soc->num_ttgs; i++) {
14142a895871SWei Ni state = REG_GET_MASK(r, ttgs[i]->thermtrip_enable_mask);
14152a895871SWei Ni seq_printf(s, " %s En(%d) ", ttgs[i]->name, state);
14162a895871SWei Ni state = REG_GET_MASK(r, ttgs[i]->thermtrip_threshold_mask);
14172a895871SWei Ni state *= ts->soc->thresh_grain;
14182a895871SWei Ni seq_printf(s, "Thresh(%d)\n", state);
14192a895871SWei Ni }
14202a895871SWei Ni
1421ce0dbf04SWei Ni r = readl(ts->regs + THROT_GLOBAL_CFG);
1422ce0dbf04SWei Ni seq_puts(s, "\n");
1423ce0dbf04SWei Ni seq_printf(s, "GLOBAL THROTTLE CONFIG: 0x%08x\n", r);
1424ce0dbf04SWei Ni
1425ce0dbf04SWei Ni seq_puts(s, "---------------------------------------------------\n");
1426ce0dbf04SWei Ni r = readl(ts->regs + THROT_STATUS);
1427ce0dbf04SWei Ni state = REG_GET_MASK(r, THROT_STATUS_BREACH_MASK);
1428ce0dbf04SWei Ni seq_printf(s, "THROT STATUS: breach(%d) ", state);
1429ce0dbf04SWei Ni state = REG_GET_MASK(r, THROT_STATUS_STATE_MASK);
1430ce0dbf04SWei Ni seq_printf(s, "state(%d) ", state);
1431ce0dbf04SWei Ni state = REG_GET_MASK(r, THROT_STATUS_ENABLED_MASK);
1432ce0dbf04SWei Ni seq_printf(s, "enabled(%d)\n", state);
1433ce0dbf04SWei Ni
1434ce0dbf04SWei Ni r = readl(ts->regs + CPU_PSKIP_STATUS);
14356c7c3245SWei Ni if (ts->soc->use_ccroc) {
14366c7c3245SWei Ni state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);
14376c7c3245SWei Ni seq_printf(s, "CPU PSKIP STATUS: enabled(%d)\n", state);
14386c7c3245SWei Ni } else {
1439ce0dbf04SWei Ni state = REG_GET_MASK(r, XPU_PSKIP_STATUS_M_MASK);
1440ce0dbf04SWei Ni seq_printf(s, "CPU PSKIP STATUS: M(%d) ", state);
1441ce0dbf04SWei Ni state = REG_GET_MASK(r, XPU_PSKIP_STATUS_N_MASK);
1442ce0dbf04SWei Ni seq_printf(s, "N(%d) ", state);
1443ce0dbf04SWei Ni state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);
1444ce0dbf04SWei Ni seq_printf(s, "enabled(%d)\n", state);
14456c7c3245SWei Ni }
1446ce0dbf04SWei Ni
1447d753b22dSWei Ni return 0;
1448d753b22dSWei Ni }
1449d753b22dSWei Ni
145005c1b705SYangtao Li DEFINE_SHOW_ATTRIBUTE(regs);
1451d753b22dSWei Ni
soctherm_debug_init(struct platform_device * pdev)1452d753b22dSWei Ni static void soctherm_debug_init(struct platform_device *pdev)
1453d753b22dSWei Ni {
1454d753b22dSWei Ni struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
1455f9d5de40SGreg Kroah-Hartman struct dentry *root;
1456d753b22dSWei Ni
1457d753b22dSWei Ni root = debugfs_create_dir("soctherm", NULL);
1458d753b22dSWei Ni
1459d753b22dSWei Ni tegra->debugfs_dir = root;
1460d753b22dSWei Ni
1461f9d5de40SGreg Kroah-Hartman debugfs_create_file("reg_contents", 0644, root, pdev, ®s_fops);
1462d753b22dSWei Ni }
1463d753b22dSWei Ni #else
soctherm_debug_init(struct platform_device * pdev)1464d753b22dSWei Ni static inline void soctherm_debug_init(struct platform_device *pdev) {}
1465d753b22dSWei Ni #endif
1466d753b22dSWei Ni
soctherm_clk_enable(struct platform_device * pdev,bool enable)14678de2ab02SWei Ni static int soctherm_clk_enable(struct platform_device *pdev, bool enable)
14688de2ab02SWei Ni {
14698de2ab02SWei Ni struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
14708de2ab02SWei Ni int err;
14718de2ab02SWei Ni
14728de2ab02SWei Ni if (!tegra->clock_soctherm || !tegra->clock_tsensor)
14738de2ab02SWei Ni return -EINVAL;
14748de2ab02SWei Ni
14758de2ab02SWei Ni reset_control_assert(tegra->reset);
14768de2ab02SWei Ni
14778de2ab02SWei Ni if (enable) {
14788de2ab02SWei Ni err = clk_prepare_enable(tegra->clock_soctherm);
14798de2ab02SWei Ni if (err) {
14808de2ab02SWei Ni reset_control_deassert(tegra->reset);
14818de2ab02SWei Ni return err;
14828de2ab02SWei Ni }
14838de2ab02SWei Ni
14848de2ab02SWei Ni err = clk_prepare_enable(tegra->clock_tsensor);
14858de2ab02SWei Ni if (err) {
14868de2ab02SWei Ni clk_disable_unprepare(tegra->clock_soctherm);
14878de2ab02SWei Ni reset_control_deassert(tegra->reset);
14888de2ab02SWei Ni return err;
14898de2ab02SWei Ni }
14908de2ab02SWei Ni } else {
14918de2ab02SWei Ni clk_disable_unprepare(tegra->clock_tsensor);
14928de2ab02SWei Ni clk_disable_unprepare(tegra->clock_soctherm);
14938de2ab02SWei Ni }
14948de2ab02SWei Ni
14958de2ab02SWei Ni reset_control_deassert(tegra->reset);
14968de2ab02SWei Ni
14978de2ab02SWei Ni return 0;
14988de2ab02SWei Ni }
14998de2ab02SWei Ni
throt_get_cdev_max_state(struct thermal_cooling_device * cdev,unsigned long * max_state)1500ce0dbf04SWei Ni static int throt_get_cdev_max_state(struct thermal_cooling_device *cdev,
1501ce0dbf04SWei Ni unsigned long *max_state)
1502ce0dbf04SWei Ni {
1503ce0dbf04SWei Ni *max_state = 1;
1504ce0dbf04SWei Ni return 0;
1505ce0dbf04SWei Ni }
1506ce0dbf04SWei Ni
throt_get_cdev_cur_state(struct thermal_cooling_device * cdev,unsigned long * cur_state)1507ce0dbf04SWei Ni static int throt_get_cdev_cur_state(struct thermal_cooling_device *cdev,
1508ce0dbf04SWei Ni unsigned long *cur_state)
1509ce0dbf04SWei Ni {
1510ce0dbf04SWei Ni struct tegra_soctherm *ts = cdev->devdata;
1511ce0dbf04SWei Ni u32 r;
1512ce0dbf04SWei Ni
1513ce0dbf04SWei Ni r = readl(ts->regs + THROT_STATUS);
1514ce0dbf04SWei Ni if (REG_GET_MASK(r, THROT_STATUS_STATE_MASK))
1515ce0dbf04SWei Ni *cur_state = 1;
1516ce0dbf04SWei Ni else
1517ce0dbf04SWei Ni *cur_state = 0;
1518ce0dbf04SWei Ni
1519ce0dbf04SWei Ni return 0;
1520ce0dbf04SWei Ni }
1521ce0dbf04SWei Ni
throt_set_cdev_state(struct thermal_cooling_device * cdev,unsigned long cur_state)1522ce0dbf04SWei Ni static int throt_set_cdev_state(struct thermal_cooling_device *cdev,
1523ce0dbf04SWei Ni unsigned long cur_state)
1524ce0dbf04SWei Ni {
1525ce0dbf04SWei Ni return 0;
1526ce0dbf04SWei Ni }
1527ce0dbf04SWei Ni
1528cc50ba5eSsrplinux2008 static const struct thermal_cooling_device_ops throt_cooling_ops = {
1529ce0dbf04SWei Ni .get_max_state = throt_get_cdev_max_state,
1530ce0dbf04SWei Ni .get_cur_state = throt_get_cdev_cur_state,
1531ce0dbf04SWei Ni .set_cur_state = throt_set_cdev_state,
1532ce0dbf04SWei Ni };
1533ce0dbf04SWei Ni
soctherm_thermtrips_parse(struct platform_device * pdev)15342510aa56SWei Ni static int soctherm_thermtrips_parse(struct platform_device *pdev)
15352510aa56SWei Ni {
15362510aa56SWei Ni struct device *dev = &pdev->dev;
15372510aa56SWei Ni struct tegra_soctherm *ts = dev_get_drvdata(dev);
15382510aa56SWei Ni struct tsensor_group_thermtrips *tt = ts->soc->thermtrips;
15392510aa56SWei Ni const int max_num_prop = ts->soc->num_ttgs * 2;
15402510aa56SWei Ni u32 *tlb;
15412510aa56SWei Ni int i, j, n, ret;
15422510aa56SWei Ni
15432510aa56SWei Ni if (!tt)
15442510aa56SWei Ni return -ENOMEM;
15452510aa56SWei Ni
15462510aa56SWei Ni n = of_property_count_u32_elems(dev->of_node, "nvidia,thermtrips");
15472510aa56SWei Ni if (n <= 0) {
15482510aa56SWei Ni dev_info(dev,
15492510aa56SWei Ni "missing thermtrips, will use critical trips as shut down temp\n");
15502510aa56SWei Ni return n;
15512510aa56SWei Ni }
15522510aa56SWei Ni
15532510aa56SWei Ni n = min(max_num_prop, n);
15542510aa56SWei Ni
15552510aa56SWei Ni tlb = devm_kcalloc(&pdev->dev, max_num_prop, sizeof(u32), GFP_KERNEL);
15562510aa56SWei Ni if (!tlb)
15572510aa56SWei Ni return -ENOMEM;
15582510aa56SWei Ni ret = of_property_read_u32_array(dev->of_node, "nvidia,thermtrips",
15592510aa56SWei Ni tlb, n);
15602510aa56SWei Ni if (ret) {
15612510aa56SWei Ni dev_err(dev, "invalid num ele: thermtrips:%d\n", ret);
15622510aa56SWei Ni return ret;
15632510aa56SWei Ni }
15642510aa56SWei Ni
15652510aa56SWei Ni i = 0;
15662510aa56SWei Ni for (j = 0; j < n; j = j + 2) {
15672510aa56SWei Ni if (tlb[j] >= TEGRA124_SOCTHERM_SENSOR_NUM)
15682510aa56SWei Ni continue;
15692510aa56SWei Ni
15702510aa56SWei Ni tt[i].id = tlb[j];
15712510aa56SWei Ni tt[i].temp = tlb[j + 1];
15722510aa56SWei Ni i++;
15732510aa56SWei Ni }
15742510aa56SWei Ni
15752510aa56SWei Ni return 0;
15762510aa56SWei Ni }
15772510aa56SWei Ni
soctherm_oc_cfg_parse(struct device * dev,struct device_node * np_oc,struct soctherm_throt_cfg * stc)15781dcc242cSWei Ni static void soctherm_oc_cfg_parse(struct device *dev,
15791dcc242cSWei Ni struct device_node *np_oc,
15801dcc242cSWei Ni struct soctherm_throt_cfg *stc)
15811dcc242cSWei Ni {
15821dcc242cSWei Ni u32 val;
15831dcc242cSWei Ni
15841dcc242cSWei Ni if (of_property_read_bool(np_oc, "nvidia,polarity-active-low"))
15851dcc242cSWei Ni stc->oc_cfg.active_low = 1;
15861dcc242cSWei Ni else
15871dcc242cSWei Ni stc->oc_cfg.active_low = 0;
15881dcc242cSWei Ni
15891dcc242cSWei Ni if (!of_property_read_u32(np_oc, "nvidia,count-threshold", &val)) {
15901dcc242cSWei Ni stc->oc_cfg.intr_en = 1;
15911dcc242cSWei Ni stc->oc_cfg.alarm_cnt_thresh = val;
15921dcc242cSWei Ni }
15931dcc242cSWei Ni
15941dcc242cSWei Ni if (!of_property_read_u32(np_oc, "nvidia,throttle-period-us", &val))
15951dcc242cSWei Ni stc->oc_cfg.throt_period = val;
15961dcc242cSWei Ni
15971dcc242cSWei Ni if (!of_property_read_u32(np_oc, "nvidia,alarm-filter", &val))
15981dcc242cSWei Ni stc->oc_cfg.alarm_filter = val;
15991dcc242cSWei Ni
16001dcc242cSWei Ni /* BRIEF throttling by default, do not support STICKY */
16011dcc242cSWei Ni stc->oc_cfg.mode = OC_THROTTLE_MODE_BRIEF;
16021dcc242cSWei Ni }
16031dcc242cSWei Ni
soctherm_throt_cfg_parse(struct device * dev,struct device_node * np,struct soctherm_throt_cfg * stc)16046ca29b7eSWei Ni static int soctherm_throt_cfg_parse(struct device *dev,
16056ca29b7eSWei Ni struct device_node *np,
16066ca29b7eSWei Ni struct soctherm_throt_cfg *stc)
16076ca29b7eSWei Ni {
16086ca29b7eSWei Ni struct tegra_soctherm *ts = dev_get_drvdata(dev);
16096ca29b7eSWei Ni int ret;
16106ca29b7eSWei Ni u32 val;
16116ca29b7eSWei Ni
16126ca29b7eSWei Ni ret = of_property_read_u32(np, "nvidia,priority", &val);
16136ca29b7eSWei Ni if (ret) {
16146ca29b7eSWei Ni dev_err(dev, "throttle-cfg: %s: invalid priority\n", stc->name);
16156ca29b7eSWei Ni return -EINVAL;
16166ca29b7eSWei Ni }
16176ca29b7eSWei Ni stc->priority = val;
16186ca29b7eSWei Ni
16196ca29b7eSWei Ni ret = of_property_read_u32(np, ts->soc->use_ccroc ?
16206ca29b7eSWei Ni "nvidia,cpu-throt-level" :
16216ca29b7eSWei Ni "nvidia,cpu-throt-percent", &val);
16226ca29b7eSWei Ni if (!ret) {
16236ca29b7eSWei Ni if (ts->soc->use_ccroc &&
16246ca29b7eSWei Ni val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
16256ca29b7eSWei Ni stc->cpu_throt_level = val;
16266ca29b7eSWei Ni else if (!ts->soc->use_ccroc && val <= 100)
16276ca29b7eSWei Ni stc->cpu_throt_depth = val;
16286ca29b7eSWei Ni else
16296ca29b7eSWei Ni goto err;
16306ca29b7eSWei Ni } else {
16316ca29b7eSWei Ni goto err;
16326ca29b7eSWei Ni }
16336ca29b7eSWei Ni
16346ca29b7eSWei Ni ret = of_property_read_u32(np, "nvidia,gpu-throt-level", &val);
16356ca29b7eSWei Ni if (!ret && val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
16366ca29b7eSWei Ni stc->gpu_throt_level = val;
16376ca29b7eSWei Ni else
16386ca29b7eSWei Ni goto err;
16396ca29b7eSWei Ni
16406ca29b7eSWei Ni return 0;
16416ca29b7eSWei Ni
16426ca29b7eSWei Ni err:
16436ca29b7eSWei Ni dev_err(dev, "throttle-cfg: %s: no throt prop or invalid prop\n",
16446ca29b7eSWei Ni stc->name);
16456ca29b7eSWei Ni return -EINVAL;
16466ca29b7eSWei Ni }
16476ca29b7eSWei Ni
1648ce0dbf04SWei Ni /**
1649ce0dbf04SWei Ni * soctherm_init_hw_throt_cdev() - Parse the HW throttle configurations
1650ce0dbf04SWei Ni * and register them as cooling devices.
16516a6d634cSAmit Kucheria * @pdev: Pointer to platform_device struct
1652ce0dbf04SWei Ni */
soctherm_init_hw_throt_cdev(struct platform_device * pdev)1653ce0dbf04SWei Ni static void soctherm_init_hw_throt_cdev(struct platform_device *pdev)
1654ce0dbf04SWei Ni {
1655ce0dbf04SWei Ni struct device *dev = &pdev->dev;
1656ce0dbf04SWei Ni struct tegra_soctherm *ts = dev_get_drvdata(dev);
1657ce0dbf04SWei Ni struct device_node *np_stc, *np_stcc;
1658ce0dbf04SWei Ni const char *name;
16596ca29b7eSWei Ni int i;
1660ce0dbf04SWei Ni
1661ce0dbf04SWei Ni for (i = 0; i < THROTTLE_SIZE; i++) {
1662ce0dbf04SWei Ni ts->throt_cfgs[i].name = throt_names[i];
1663ce0dbf04SWei Ni ts->throt_cfgs[i].id = i;
1664ce0dbf04SWei Ni ts->throt_cfgs[i].init = false;
1665ce0dbf04SWei Ni }
1666ce0dbf04SWei Ni
1667ce0dbf04SWei Ni np_stc = of_get_child_by_name(dev->of_node, "throttle-cfgs");
1668ce0dbf04SWei Ni if (!np_stc) {
1669ce0dbf04SWei Ni dev_info(dev,
1670ce0dbf04SWei Ni "throttle-cfg: no throttle-cfgs - not enabling\n");
1671ce0dbf04SWei Ni return;
1672ce0dbf04SWei Ni }
1673ce0dbf04SWei Ni
1674ce0dbf04SWei Ni for_each_child_of_node(np_stc, np_stcc) {
1675ce0dbf04SWei Ni struct soctherm_throt_cfg *stc;
1676ce0dbf04SWei Ni struct thermal_cooling_device *tcd;
16776ca29b7eSWei Ni int err;
1678ce0dbf04SWei Ni
1679ce0dbf04SWei Ni name = np_stcc->name;
1680ce0dbf04SWei Ni stc = find_throttle_cfg_by_name(ts, name);
1681ce0dbf04SWei Ni if (!stc) {
1682ce0dbf04SWei Ni dev_err(dev,
1683ce0dbf04SWei Ni "throttle-cfg: could not find %s\n", name);
1684ce0dbf04SWei Ni continue;
1685ce0dbf04SWei Ni }
1686ce0dbf04SWei Ni
16871dcc242cSWei Ni if (stc->init) {
16881dcc242cSWei Ni dev_err(dev, "throttle-cfg: %s: redefined!\n", name);
16891dcc242cSWei Ni of_node_put(np_stcc);
16901dcc242cSWei Ni break;
16911dcc242cSWei Ni }
1692ce0dbf04SWei Ni
16936ca29b7eSWei Ni err = soctherm_throt_cfg_parse(dev, np_stcc, stc);
16946ca29b7eSWei Ni if (err)
16956c7c3245SWei Ni continue;
1696ce0dbf04SWei Ni
16971dcc242cSWei Ni if (stc->id >= THROTTLE_OC1) {
16981dcc242cSWei Ni soctherm_oc_cfg_parse(dev, np_stcc, stc);
16991dcc242cSWei Ni stc->init = true;
17001dcc242cSWei Ni } else {
17011dcc242cSWei Ni
1702ce0dbf04SWei Ni tcd = thermal_of_cooling_device_register(np_stcc,
1703ce0dbf04SWei Ni (char *)name, ts,
1704ce0dbf04SWei Ni &throt_cooling_ops);
1705ce0dbf04SWei Ni if (IS_ERR_OR_NULL(tcd)) {
1706ce0dbf04SWei Ni dev_err(dev,
1707ce0dbf04SWei Ni "throttle-cfg: %s: failed to register cooling device\n",
1708ce0dbf04SWei Ni name);
1709ce0dbf04SWei Ni continue;
1710ce0dbf04SWei Ni }
1711ce0dbf04SWei Ni stc->cdev = tcd;
1712ce0dbf04SWei Ni stc->init = true;
1713ce0dbf04SWei Ni }
1714ce0dbf04SWei Ni
17151dcc242cSWei Ni }
17161dcc242cSWei Ni
1717ce0dbf04SWei Ni of_node_put(np_stc);
1718ce0dbf04SWei Ni }
1719ce0dbf04SWei Ni
1720ce0dbf04SWei Ni /**
17216c7c3245SWei Ni * throttlectl_cpu_level_cfg() - programs CCROC NV_THERM level config
17226a6d634cSAmit Kucheria * @ts: pointer to a struct tegra_soctherm
17236c7c3245SWei Ni * @level: describing the level LOW/MED/HIGH of throttling
17246c7c3245SWei Ni *
17256c7c3245SWei Ni * It's necessary to set up the CPU-local CCROC NV_THERM instance with
17266c7c3245SWei Ni * the M/N values desired for each level. This function does this.
17276c7c3245SWei Ni *
17286c7c3245SWei Ni * This function pre-programs the CCROC NV_THERM levels in terms of
17296c7c3245SWei Ni * pre-configured "Low", "Medium" or "Heavy" throttle levels which are
17306c7c3245SWei Ni * mapped to THROT_LEVEL_LOW, THROT_LEVEL_MED and THROT_LEVEL_HVY.
17316c7c3245SWei Ni */
throttlectl_cpu_level_cfg(struct tegra_soctherm * ts,int level)17326c7c3245SWei Ni static void throttlectl_cpu_level_cfg(struct tegra_soctherm *ts, int level)
17336c7c3245SWei Ni {
17346c7c3245SWei Ni u8 depth, dividend;
17356c7c3245SWei Ni u32 r;
17366c7c3245SWei Ni
17376c7c3245SWei Ni switch (level) {
17386c7c3245SWei Ni case TEGRA_SOCTHERM_THROT_LEVEL_LOW:
17396c7c3245SWei Ni depth = 50;
17406c7c3245SWei Ni break;
17416c7c3245SWei Ni case TEGRA_SOCTHERM_THROT_LEVEL_MED:
17426c7c3245SWei Ni depth = 75;
17436c7c3245SWei Ni break;
17446c7c3245SWei Ni case TEGRA_SOCTHERM_THROT_LEVEL_HIGH:
17456c7c3245SWei Ni depth = 80;
17466c7c3245SWei Ni break;
17476c7c3245SWei Ni case TEGRA_SOCTHERM_THROT_LEVEL_NONE:
17486c7c3245SWei Ni return;
17496c7c3245SWei Ni default:
17506c7c3245SWei Ni return;
17516c7c3245SWei Ni }
17526c7c3245SWei Ni
17536c7c3245SWei Ni dividend = THROT_DEPTH_DIVIDEND(depth);
17546c7c3245SWei Ni
17556c7c3245SWei Ni /* setup PSKIP in ccroc nv_therm registers */
17566c7c3245SWei Ni r = ccroc_readl(ts, CCROC_THROT_PSKIP_RAMP_CPU_REG(level));
17576c7c3245SWei Ni r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_DURATION_MASK, 0xff);
17586c7c3245SWei Ni r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_STEP_MASK, 0xf);
17596c7c3245SWei Ni ccroc_writel(ts, r, CCROC_THROT_PSKIP_RAMP_CPU_REG(level));
17606c7c3245SWei Ni
17616c7c3245SWei Ni r = ccroc_readl(ts, CCROC_THROT_PSKIP_CTRL_CPU_REG(level));
17626c7c3245SWei Ni r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_ENB_MASK, 1);
17636c7c3245SWei Ni r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend);
17646c7c3245SWei Ni r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff);
17656c7c3245SWei Ni ccroc_writel(ts, r, CCROC_THROT_PSKIP_CTRL_CPU_REG(level));
17666c7c3245SWei Ni }
17676c7c3245SWei Ni
17686c7c3245SWei Ni /**
17696c7c3245SWei Ni * throttlectl_cpu_level_select() - program CPU pulse skipper config
17706a6d634cSAmit Kucheria * @ts: pointer to a struct tegra_soctherm
17716c7c3245SWei Ni * @throt: the LIGHT/HEAVY of throttle event id
17726c7c3245SWei Ni *
17736c7c3245SWei Ni * Pulse skippers are used to throttle clock frequencies. This
17746c7c3245SWei Ni * function programs the pulse skippers based on @throt and platform
17756c7c3245SWei Ni * data. This function is used on SoCs which have CPU-local pulse
17766c7c3245SWei Ni * skipper control, such as T13x. It programs soctherm's interface to
17776c7c3245SWei Ni * Denver:CCROC NV_THERM in terms of Low, Medium and HIGH throttling
17786c7c3245SWei Ni * vectors. PSKIP_BYPASS mode is set as required per HW spec.
17796c7c3245SWei Ni */
throttlectl_cpu_level_select(struct tegra_soctherm * ts,enum soctherm_throttle_id throt)17806c7c3245SWei Ni static void throttlectl_cpu_level_select(struct tegra_soctherm *ts,
17816c7c3245SWei Ni enum soctherm_throttle_id throt)
17826c7c3245SWei Ni {
17836c7c3245SWei Ni u32 r, throt_vect;
17846c7c3245SWei Ni
17856c7c3245SWei Ni /* Denver:CCROC NV_THERM interface N:3 Mapping */
17866c7c3245SWei Ni switch (ts->throt_cfgs[throt].cpu_throt_level) {
17876c7c3245SWei Ni case TEGRA_SOCTHERM_THROT_LEVEL_LOW:
17886c7c3245SWei Ni throt_vect = THROT_VECT_LOW;
17896c7c3245SWei Ni break;
17906c7c3245SWei Ni case TEGRA_SOCTHERM_THROT_LEVEL_MED:
17916c7c3245SWei Ni throt_vect = THROT_VECT_MED;
17926c7c3245SWei Ni break;
17936c7c3245SWei Ni case TEGRA_SOCTHERM_THROT_LEVEL_HIGH:
17946c7c3245SWei Ni throt_vect = THROT_VECT_HIGH;
17956c7c3245SWei Ni break;
17966c7c3245SWei Ni default:
17976c7c3245SWei Ni throt_vect = THROT_VECT_NONE;
17986c7c3245SWei Ni break;
17996c7c3245SWei Ni }
18006c7c3245SWei Ni
18016c7c3245SWei Ni r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
18026c7c3245SWei Ni r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
18036c7c3245SWei Ni r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_CPU_MASK, throt_vect);
18046c7c3245SWei Ni r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT2_CPU_MASK, throt_vect);
18056c7c3245SWei Ni writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
18066c7c3245SWei Ni
18076c7c3245SWei Ni /* bypass sequencer in soc_therm as it is programmed in ccroc */
18086c7c3245SWei Ni r = REG_SET_MASK(0, THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK, 1);
18096c7c3245SWei Ni writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
18106c7c3245SWei Ni }
18116c7c3245SWei Ni
18126c7c3245SWei Ni /**
1813ce0dbf04SWei Ni * throttlectl_cpu_mn() - program CPU pulse skipper configuration
18146a6d634cSAmit Kucheria * @ts: pointer to a struct tegra_soctherm
1815ce0dbf04SWei Ni * @throt: the LIGHT/HEAVY of throttle event id
1816ce0dbf04SWei Ni *
1817ce0dbf04SWei Ni * Pulse skippers are used to throttle clock frequencies. This
1818ce0dbf04SWei Ni * function programs the pulse skippers based on @throt and platform
1819ce0dbf04SWei Ni * data. This function is used for CPUs that have "remote" pulse
1820ce0dbf04SWei Ni * skipper control, e.g., the CPU pulse skipper is controlled by the
1821ce0dbf04SWei Ni * SOC_THERM IP block. (SOC_THERM is located outside the CPU
1822ce0dbf04SWei Ni * complex.)
1823ce0dbf04SWei Ni */
throttlectl_cpu_mn(struct tegra_soctherm * ts,enum soctherm_throttle_id throt)1824ce0dbf04SWei Ni static void throttlectl_cpu_mn(struct tegra_soctherm *ts,
1825ce0dbf04SWei Ni enum soctherm_throttle_id throt)
1826ce0dbf04SWei Ni {
1827ce0dbf04SWei Ni u32 r;
1828ce0dbf04SWei Ni int depth;
1829ce0dbf04SWei Ni u8 dividend;
1830ce0dbf04SWei Ni
1831ce0dbf04SWei Ni depth = ts->throt_cfgs[throt].cpu_throt_depth;
1832ce0dbf04SWei Ni dividend = THROT_DEPTH_DIVIDEND(depth);
1833ce0dbf04SWei Ni
1834ce0dbf04SWei Ni r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
1835ce0dbf04SWei Ni r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
1836ce0dbf04SWei Ni r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend);
1837ce0dbf04SWei Ni r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff);
1838ce0dbf04SWei Ni writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
1839ce0dbf04SWei Ni
1840ce0dbf04SWei Ni r = readl(ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
1841ce0dbf04SWei Ni r = REG_SET_MASK(r, THROT_PSKIP_RAMP_DURATION_MASK, 0xff);
1842ce0dbf04SWei Ni r = REG_SET_MASK(r, THROT_PSKIP_RAMP_STEP_MASK, 0xf);
1843ce0dbf04SWei Ni writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
1844ce0dbf04SWei Ni }
1845ce0dbf04SWei Ni
1846ce0dbf04SWei Ni /**
18476ca29b7eSWei Ni * throttlectl_gpu_level_select() - selects throttling level for GPU
18486a6d634cSAmit Kucheria * @ts: pointer to a struct tegra_soctherm
18496ca29b7eSWei Ni * @throt: the LIGHT/HEAVY of throttle event id
18506ca29b7eSWei Ni *
18516ca29b7eSWei Ni * This function programs soctherm's interface to GK20a NV_THERM to select
18526ca29b7eSWei Ni * pre-configured "Low", "Medium" or "Heavy" throttle levels.
18536ca29b7eSWei Ni *
18546ca29b7eSWei Ni * Return: boolean true if HW was programmed
18556ca29b7eSWei Ni */
throttlectl_gpu_level_select(struct tegra_soctherm * ts,enum soctherm_throttle_id throt)18566ca29b7eSWei Ni static void throttlectl_gpu_level_select(struct tegra_soctherm *ts,
18576ca29b7eSWei Ni enum soctherm_throttle_id throt)
18586ca29b7eSWei Ni {
18596ca29b7eSWei Ni u32 r, level, throt_vect;
18606ca29b7eSWei Ni
18616ca29b7eSWei Ni level = ts->throt_cfgs[throt].gpu_throt_level;
18626ca29b7eSWei Ni throt_vect = THROT_LEVEL_TO_DEPTH(level);
18636ca29b7eSWei Ni r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
18646ca29b7eSWei Ni r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
18656ca29b7eSWei Ni r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_GPU_MASK, throt_vect);
18666ca29b7eSWei Ni writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
18676ca29b7eSWei Ni }
18686ca29b7eSWei Ni
soctherm_oc_cfg_program(struct tegra_soctherm * ts,enum soctherm_throttle_id throt)18691dcc242cSWei Ni static int soctherm_oc_cfg_program(struct tegra_soctherm *ts,
18701dcc242cSWei Ni enum soctherm_throttle_id throt)
18711dcc242cSWei Ni {
18721dcc242cSWei Ni u32 r;
18731dcc242cSWei Ni struct soctherm_oc_cfg *oc = &ts->throt_cfgs[throt].oc_cfg;
18741dcc242cSWei Ni
18751dcc242cSWei Ni if (oc->mode == OC_THROTTLE_MODE_DISABLED)
18761dcc242cSWei Ni return -EINVAL;
18771dcc242cSWei Ni
18781dcc242cSWei Ni r = REG_SET_MASK(0, OC1_CFG_HW_RESTORE_MASK, 1);
18791dcc242cSWei Ni r = REG_SET_MASK(r, OC1_CFG_THROTTLE_MODE_MASK, oc->mode);
18801dcc242cSWei Ni r = REG_SET_MASK(r, OC1_CFG_ALARM_POLARITY_MASK, oc->active_low);
18811dcc242cSWei Ni r = REG_SET_MASK(r, OC1_CFG_EN_THROTTLE_MASK, 1);
18821dcc242cSWei Ni writel(r, ts->regs + ALARM_CFG(throt));
18831dcc242cSWei Ni writel(oc->throt_period, ts->regs + ALARM_THROTTLE_PERIOD(throt));
18841dcc242cSWei Ni writel(oc->alarm_cnt_thresh, ts->regs + ALARM_CNT_THRESHOLD(throt));
18851dcc242cSWei Ni writel(oc->alarm_filter, ts->regs + ALARM_FILTER(throt));
18861dcc242cSWei Ni soctherm_oc_intr_enable(ts, throt, oc->intr_en);
18871dcc242cSWei Ni
18881dcc242cSWei Ni return 0;
18891dcc242cSWei Ni }
18901dcc242cSWei Ni
18916ca29b7eSWei Ni /**
1892ce0dbf04SWei Ni * soctherm_throttle_program() - programs pulse skippers' configuration
18936a6d634cSAmit Kucheria * @ts: pointer to a struct tegra_soctherm
1894ce0dbf04SWei Ni * @throt: the LIGHT/HEAVY of the throttle event id.
1895ce0dbf04SWei Ni *
1896ce0dbf04SWei Ni * Pulse skippers are used to throttle clock frequencies.
1897ce0dbf04SWei Ni * This function programs the pulse skippers.
1898ce0dbf04SWei Ni */
soctherm_throttle_program(struct tegra_soctherm * ts,enum soctherm_throttle_id throt)1899ce0dbf04SWei Ni static void soctherm_throttle_program(struct tegra_soctherm *ts,
1900ce0dbf04SWei Ni enum soctherm_throttle_id throt)
1901ce0dbf04SWei Ni {
1902ce0dbf04SWei Ni u32 r;
1903ce0dbf04SWei Ni struct soctherm_throt_cfg stc = ts->throt_cfgs[throt];
1904ce0dbf04SWei Ni
1905ce0dbf04SWei Ni if (!stc.init)
1906ce0dbf04SWei Ni return;
1907ce0dbf04SWei Ni
19081dcc242cSWei Ni if ((throt >= THROTTLE_OC1) && (soctherm_oc_cfg_program(ts, throt)))
19091dcc242cSWei Ni return;
19101dcc242cSWei Ni
1911ce0dbf04SWei Ni /* Setup PSKIP parameters */
19126c7c3245SWei Ni if (ts->soc->use_ccroc)
19136c7c3245SWei Ni throttlectl_cpu_level_select(ts, throt);
19146c7c3245SWei Ni else
1915ce0dbf04SWei Ni throttlectl_cpu_mn(ts, throt);
1916ce0dbf04SWei Ni
19176ca29b7eSWei Ni throttlectl_gpu_level_select(ts, throt);
19186ca29b7eSWei Ni
1919ce0dbf04SWei Ni r = REG_SET_MASK(0, THROT_PRIORITY_LITE_PRIO_MASK, stc.priority);
1920ce0dbf04SWei Ni writel(r, ts->regs + THROT_PRIORITY_CTRL(throt));
1921ce0dbf04SWei Ni
1922ce0dbf04SWei Ni r = REG_SET_MASK(0, THROT_DELAY_LITE_DELAY_MASK, 0);
1923ce0dbf04SWei Ni writel(r, ts->regs + THROT_DELAY_CTRL(throt));
1924ce0dbf04SWei Ni
1925ce0dbf04SWei Ni r = readl(ts->regs + THROT_PRIORITY_LOCK);
1926ce0dbf04SWei Ni r = REG_GET_MASK(r, THROT_PRIORITY_LOCK_PRIORITY_MASK);
1927ce0dbf04SWei Ni if (r >= stc.priority)
1928ce0dbf04SWei Ni return;
1929ce0dbf04SWei Ni r = REG_SET_MASK(0, THROT_PRIORITY_LOCK_PRIORITY_MASK,
1930ce0dbf04SWei Ni stc.priority);
1931ce0dbf04SWei Ni writel(r, ts->regs + THROT_PRIORITY_LOCK);
1932ce0dbf04SWei Ni }
1933ce0dbf04SWei Ni
tegra_soctherm_throttle(struct device * dev)1934ce0dbf04SWei Ni static void tegra_soctherm_throttle(struct device *dev)
1935ce0dbf04SWei Ni {
1936ce0dbf04SWei Ni struct tegra_soctherm *ts = dev_get_drvdata(dev);
1937ce0dbf04SWei Ni u32 v;
1938ce0dbf04SWei Ni int i;
1939ce0dbf04SWei Ni
19406c7c3245SWei Ni /* configure LOW, MED and HIGH levels for CCROC NV_THERM */
19416c7c3245SWei Ni if (ts->soc->use_ccroc) {
19426c7c3245SWei Ni throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_LOW);
19436c7c3245SWei Ni throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_MED);
19446c7c3245SWei Ni throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_HIGH);
19456c7c3245SWei Ni }
19466c7c3245SWei Ni
1947ce0dbf04SWei Ni /* Thermal HW throttle programming */
1948ce0dbf04SWei Ni for (i = 0; i < THROTTLE_SIZE; i++)
1949ce0dbf04SWei Ni soctherm_throttle_program(ts, i);
1950ce0dbf04SWei Ni
1951ce0dbf04SWei Ni v = REG_SET_MASK(0, THROT_GLOBAL_ENB_MASK, 1);
19526c7c3245SWei Ni if (ts->soc->use_ccroc) {
19536c7c3245SWei Ni ccroc_writel(ts, v, CCROC_GLOBAL_CFG);
19546c7c3245SWei Ni
19556c7c3245SWei Ni v = ccroc_readl(ts, CCROC_SUPER_CCLKG_DIVIDER);
19566c7c3245SWei Ni v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
19576c7c3245SWei Ni ccroc_writel(ts, v, CCROC_SUPER_CCLKG_DIVIDER);
19586c7c3245SWei Ni } else {
1959ce0dbf04SWei Ni writel(v, ts->regs + THROT_GLOBAL_CFG);
1960ce0dbf04SWei Ni
196134283724SEzequiel Garcia v = readl(ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER);
1962ce0dbf04SWei Ni v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
196334283724SEzequiel Garcia writel(v, ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER);
19646c7c3245SWei Ni }
1965ce0dbf04SWei Ni
1966ce0dbf04SWei Ni /* initialize stats collection */
1967ce0dbf04SWei Ni v = STATS_CTL_CLR_DN | STATS_CTL_EN_DN |
1968ce0dbf04SWei Ni STATS_CTL_CLR_UP | STATS_CTL_EN_UP;
1969ce0dbf04SWei Ni writel(v, ts->regs + THERMCTL_STATS_CTL);
1970ce0dbf04SWei Ni }
1971ce0dbf04SWei Ni
soctherm_interrupts_init(struct platform_device * pdev,struct tegra_soctherm * tegra)1972d7180be0SWei Ni static int soctherm_interrupts_init(struct platform_device *pdev,
1973d7180be0SWei Ni struct tegra_soctherm *tegra)
1974d7180be0SWei Ni {
19754a04beb1SWei Ni struct device_node *np = pdev->dev.of_node;
1976d7180be0SWei Ni int ret;
1977d7180be0SWei Ni
19784a04beb1SWei Ni ret = soctherm_oc_int_init(np, TEGRA_SOC_OC_IRQ_MAX);
19794a04beb1SWei Ni if (ret < 0) {
19804a04beb1SWei Ni dev_err(&pdev->dev, "soctherm_oc_int_init failed\n");
19814a04beb1SWei Ni return ret;
19824a04beb1SWei Ni }
19834a04beb1SWei Ni
1984d7180be0SWei Ni tegra->thermal_irq = platform_get_irq(pdev, 0);
1985d7180be0SWei Ni if (tegra->thermal_irq < 0) {
1986d7180be0SWei Ni dev_dbg(&pdev->dev, "get 'thermal_irq' failed.\n");
1987d7180be0SWei Ni return 0;
1988d7180be0SWei Ni }
1989d7180be0SWei Ni
19904a04beb1SWei Ni tegra->edp_irq = platform_get_irq(pdev, 1);
19914a04beb1SWei Ni if (tegra->edp_irq < 0) {
19924a04beb1SWei Ni dev_dbg(&pdev->dev, "get 'edp_irq' failed.\n");
19934a04beb1SWei Ni return 0;
19944a04beb1SWei Ni }
19954a04beb1SWei Ni
1996d7180be0SWei Ni ret = devm_request_threaded_irq(&pdev->dev,
1997d7180be0SWei Ni tegra->thermal_irq,
1998d7180be0SWei Ni soctherm_thermal_isr,
1999d7180be0SWei Ni soctherm_thermal_isr_thread,
2000d7180be0SWei Ni IRQF_ONESHOT,
2001d7180be0SWei Ni dev_name(&pdev->dev),
2002d7180be0SWei Ni tegra);
2003d7180be0SWei Ni if (ret < 0) {
2004d7180be0SWei Ni dev_err(&pdev->dev, "request_irq 'thermal_irq' failed.\n");
2005d7180be0SWei Ni return ret;
2006d7180be0SWei Ni }
2007d7180be0SWei Ni
20084a04beb1SWei Ni ret = devm_request_threaded_irq(&pdev->dev,
20094a04beb1SWei Ni tegra->edp_irq,
20104a04beb1SWei Ni soctherm_edp_isr,
20114a04beb1SWei Ni soctherm_edp_isr_thread,
20124a04beb1SWei Ni IRQF_ONESHOT,
20134a04beb1SWei Ni "soctherm_edp",
20144a04beb1SWei Ni tegra);
20154a04beb1SWei Ni if (ret < 0) {
20164a04beb1SWei Ni dev_err(&pdev->dev, "request_irq 'edp_irq' failed.\n");
20174a04beb1SWei Ni return ret;
20184a04beb1SWei Ni }
20194a04beb1SWei Ni
2020d7180be0SWei Ni return 0;
2021d7180be0SWei Ni }
2022d7180be0SWei Ni
soctherm_init(struct platform_device * pdev)20231ed895c2SWei Ni static void soctherm_init(struct platform_device *pdev)
20241ed895c2SWei Ni {
20251ed895c2SWei Ni struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
20261ed895c2SWei Ni const struct tegra_tsensor_group **ttgs = tegra->soc->ttgs;
20271ed895c2SWei Ni int i;
20281ed895c2SWei Ni u32 pdiv, hotspot;
20291ed895c2SWei Ni
20301ed895c2SWei Ni /* Initialize raw sensors */
20311ed895c2SWei Ni for (i = 0; i < tegra->soc->num_tsensors; ++i)
20321ed895c2SWei Ni enable_tsensor(tegra, i);
20331ed895c2SWei Ni
20341ed895c2SWei Ni /* program pdiv and hotspot offsets per THERM */
20351ed895c2SWei Ni pdiv = readl(tegra->regs + SENSOR_PDIV);
20361ed895c2SWei Ni hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
20371ed895c2SWei Ni for (i = 0; i < tegra->soc->num_ttgs; ++i) {
20381ed895c2SWei Ni pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
20391ed895c2SWei Ni ttgs[i]->pdiv);
20401ed895c2SWei Ni /* hotspot offset from PLLX, doesn't need to configure PLLX */
20411ed895c2SWei Ni if (ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX)
20421ed895c2SWei Ni continue;
20431ed895c2SWei Ni hotspot = REG_SET_MASK(hotspot,
20441ed895c2SWei Ni ttgs[i]->pllx_hotspot_mask,
20451ed895c2SWei Ni ttgs[i]->pllx_hotspot_diff);
20461ed895c2SWei Ni }
20471ed895c2SWei Ni writel(pdiv, tegra->regs + SENSOR_PDIV);
20481ed895c2SWei Ni writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
2049ce0dbf04SWei Ni
2050ce0dbf04SWei Ni /* Configure hw throttle */
2051ce0dbf04SWei Ni tegra_soctherm_throttle(&pdev->dev);
20521ed895c2SWei Ni }
20531ed895c2SWei Ni
205465b6d57cSWei Ni static const struct of_device_id tegra_soctherm_of_match[] = {
205565b6d57cSWei Ni #ifdef CONFIG_ARCH_TEGRA_124_SOC
205665b6d57cSWei Ni {
205765b6d57cSWei Ni .compatible = "nvidia,tegra124-soctherm",
205865b6d57cSWei Ni .data = &tegra124_soctherm,
205965b6d57cSWei Ni },
206065b6d57cSWei Ni #endif
206144cb6a7dSWei Ni #ifdef CONFIG_ARCH_TEGRA_132_SOC
206244cb6a7dSWei Ni {
206344cb6a7dSWei Ni .compatible = "nvidia,tegra132-soctherm",
206444cb6a7dSWei Ni .data = &tegra132_soctherm,
206544cb6a7dSWei Ni },
206644cb6a7dSWei Ni #endif
20678204104fSWei Ni #ifdef CONFIG_ARCH_TEGRA_210_SOC
20688204104fSWei Ni {
20698204104fSWei Ni .compatible = "nvidia,tegra210-soctherm",
20708204104fSWei Ni .data = &tegra210_soctherm,
20718204104fSWei Ni },
20728204104fSWei Ni #endif
207365b6d57cSWei Ni { },
207465b6d57cSWei Ni };
207565b6d57cSWei Ni MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
207665b6d57cSWei Ni
tegra_soctherm_probe(struct platform_device * pdev)207765b6d57cSWei Ni static int tegra_soctherm_probe(struct platform_device *pdev)
207865b6d57cSWei Ni {
207965b6d57cSWei Ni const struct of_device_id *match;
208065b6d57cSWei Ni struct tegra_soctherm *tegra;
208165b6d57cSWei Ni struct thermal_zone_device *z;
208265b6d57cSWei Ni struct tsensor_shared_calib shared_calib;
208365b6d57cSWei Ni struct tegra_soctherm_soc *soc;
208465b6d57cSWei Ni unsigned int i;
208565b6d57cSWei Ni int err;
208665b6d57cSWei Ni
208765b6d57cSWei Ni match = of_match_node(tegra_soctherm_of_match, pdev->dev.of_node);
208865b6d57cSWei Ni if (!match)
208965b6d57cSWei Ni return -ENODEV;
209065b6d57cSWei Ni
209165b6d57cSWei Ni soc = (struct tegra_soctherm_soc *)match->data;
209265b6d57cSWei Ni if (soc->num_ttgs > TEGRA124_SOCTHERM_SENSOR_NUM)
209365b6d57cSWei Ni return -EINVAL;
209465b6d57cSWei Ni
209565b6d57cSWei Ni tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
209665b6d57cSWei Ni if (!tegra)
209765b6d57cSWei Ni return -ENOMEM;
209865b6d57cSWei Ni
20995c9d6ac2SWei Ni mutex_init(&tegra->thermctl_lock);
210065b6d57cSWei Ni dev_set_drvdata(&pdev->dev, tegra);
210165b6d57cSWei Ni
210265b6d57cSWei Ni tegra->soc = soc;
210365b6d57cSWei Ni
2104fc88f7adSdingsenjie tegra->regs = devm_platform_ioremap_resource_byname(pdev, "soctherm-reg");
2105ce0dbf04SWei Ni if (IS_ERR(tegra->regs)) {
2106ce0dbf04SWei Ni dev_err(&pdev->dev, "can't get soctherm registers");
210765b6d57cSWei Ni return PTR_ERR(tegra->regs);
2108ce0dbf04SWei Ni }
2109ce0dbf04SWei Ni
2110ce0dbf04SWei Ni if (!tegra->soc->use_ccroc) {
2111fc88f7adSdingsenjie tegra->clk_regs = devm_platform_ioremap_resource_byname(pdev, "car-reg");
2112ce0dbf04SWei Ni if (IS_ERR(tegra->clk_regs)) {
2113ce0dbf04SWei Ni dev_err(&pdev->dev, "can't get car clk registers");
2114ce0dbf04SWei Ni return PTR_ERR(tegra->clk_regs);
2115ce0dbf04SWei Ni }
21166c7c3245SWei Ni } else {
2117fc88f7adSdingsenjie tegra->ccroc_regs = devm_platform_ioremap_resource_byname(pdev, "ccroc-reg");
21186c7c3245SWei Ni if (IS_ERR(tegra->ccroc_regs)) {
21196c7c3245SWei Ni dev_err(&pdev->dev, "can't get ccroc registers");
21206c7c3245SWei Ni return PTR_ERR(tegra->ccroc_regs);
21216c7c3245SWei Ni }
2122ce0dbf04SWei Ni }
212365b6d57cSWei Ni
212465b6d57cSWei Ni tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
212565b6d57cSWei Ni if (IS_ERR(tegra->reset)) {
212665b6d57cSWei Ni dev_err(&pdev->dev, "can't get soctherm reset\n");
212765b6d57cSWei Ni return PTR_ERR(tegra->reset);
212865b6d57cSWei Ni }
212965b6d57cSWei Ni
213065b6d57cSWei Ni tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
213165b6d57cSWei Ni if (IS_ERR(tegra->clock_tsensor)) {
213265b6d57cSWei Ni dev_err(&pdev->dev, "can't get tsensor clock\n");
213365b6d57cSWei Ni return PTR_ERR(tegra->clock_tsensor);
213465b6d57cSWei Ni }
213565b6d57cSWei Ni
213665b6d57cSWei Ni tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
213765b6d57cSWei Ni if (IS_ERR(tegra->clock_soctherm)) {
213865b6d57cSWei Ni dev_err(&pdev->dev, "can't get soctherm clock\n");
213965b6d57cSWei Ni return PTR_ERR(tegra->clock_soctherm);
214065b6d57cSWei Ni }
214165b6d57cSWei Ni
2142a86854d0SKees Cook tegra->calib = devm_kcalloc(&pdev->dev,
2143a86854d0SKees Cook soc->num_tsensors, sizeof(u32),
21441ed895c2SWei Ni GFP_KERNEL);
21451ed895c2SWei Ni if (!tegra->calib)
21461ed895c2SWei Ni return -ENOMEM;
21471ed895c2SWei Ni
21481ed895c2SWei Ni /* calculate shared calibration data */
21491ed895c2SWei Ni err = tegra_calc_shared_calib(soc->tfuse, &shared_calib);
21501ed895c2SWei Ni if (err)
21511ed895c2SWei Ni return err;
21521ed895c2SWei Ni
215366068001SBhaskar Chowdhury /* calculate tsensor calibration data */
21541ed895c2SWei Ni for (i = 0; i < soc->num_tsensors; ++i) {
21551ed895c2SWei Ni err = tegra_calc_tsensor_calib(&soc->tsensors[i],
21561ed895c2SWei Ni &shared_calib,
21571ed895c2SWei Ni &tegra->calib[i]);
21581ed895c2SWei Ni if (err)
21591ed895c2SWei Ni return err;
21601ed895c2SWei Ni }
21611ed895c2SWei Ni
2162a86854d0SKees Cook tegra->thermctl_tzs = devm_kcalloc(&pdev->dev,
21633d88adf3SWei Ni soc->num_ttgs, sizeof(z),
2164f09d6984SWei Ni GFP_KERNEL);
2165f09d6984SWei Ni if (!tegra->thermctl_tzs)
2166f09d6984SWei Ni return -ENOMEM;
2167f09d6984SWei Ni
21688de2ab02SWei Ni err = soctherm_clk_enable(pdev, true);
216965b6d57cSWei Ni if (err)
217065b6d57cSWei Ni return err;
217165b6d57cSWei Ni
21722510aa56SWei Ni soctherm_thermtrips_parse(pdev);
21732510aa56SWei Ni
2174ce0dbf04SWei Ni soctherm_init_hw_throt_cdev(pdev);
2175ce0dbf04SWei Ni
21761ed895c2SWei Ni soctherm_init(pdev);
217765b6d57cSWei Ni
217865b6d57cSWei Ni for (i = 0; i < soc->num_ttgs; ++i) {
217965b6d57cSWei Ni struct tegra_thermctl_zone *zone =
218065b6d57cSWei Ni devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
218165b6d57cSWei Ni if (!zone) {
218265b6d57cSWei Ni err = -ENOMEM;
218365b6d57cSWei Ni goto disable_clocks;
218465b6d57cSWei Ni }
218565b6d57cSWei Ni
218665b6d57cSWei Ni zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset;
21872a895871SWei Ni zone->dev = &pdev->dev;
21882a895871SWei Ni zone->sg = soc->ttgs[i];
2189ce0dbf04SWei Ni zone->ts = tegra;
219065b6d57cSWei Ni
21916fc2e1a5SDaniel Lezcano z = devm_thermal_of_zone_register(&pdev->dev,
219265b6d57cSWei Ni soc->ttgs[i]->id, zone,
219365b6d57cSWei Ni &tegra_of_thermal_ops);
219465b6d57cSWei Ni if (IS_ERR(z)) {
219565b6d57cSWei Ni err = PTR_ERR(z);
219665b6d57cSWei Ni dev_err(&pdev->dev, "failed to register sensor: %d\n",
219765b6d57cSWei Ni err);
219865b6d57cSWei Ni goto disable_clocks;
219965b6d57cSWei Ni }
22002a895871SWei Ni
22012a895871SWei Ni zone->tz = z;
2202f09d6984SWei Ni tegra->thermctl_tzs[soc->ttgs[i]->id] = z;
22032a895871SWei Ni
22042a895871SWei Ni /* Configure hw trip points */
2205ce0dbf04SWei Ni err = tegra_soctherm_set_hwtrips(&pdev->dev, soc->ttgs[i], z);
2206ce0dbf04SWei Ni if (err)
2207ce0dbf04SWei Ni goto disable_clocks;
220865b6d57cSWei Ni }
220965b6d57cSWei Ni
2210d7180be0SWei Ni err = soctherm_interrupts_init(pdev, tegra);
2211d7180be0SWei Ni
2212d753b22dSWei Ni soctherm_debug_init(pdev);
2213d753b22dSWei Ni
221465b6d57cSWei Ni return 0;
221565b6d57cSWei Ni
221665b6d57cSWei Ni disable_clocks:
22178de2ab02SWei Ni soctherm_clk_enable(pdev, false);
221865b6d57cSWei Ni
221965b6d57cSWei Ni return err;
222065b6d57cSWei Ni }
222165b6d57cSWei Ni
tegra_soctherm_remove(struct platform_device * pdev)222265b6d57cSWei Ni static int tegra_soctherm_remove(struct platform_device *pdev)
222365b6d57cSWei Ni {
222465b6d57cSWei Ni struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
222565b6d57cSWei Ni
2226d753b22dSWei Ni debugfs_remove_recursive(tegra->debugfs_dir);
2227d753b22dSWei Ni
22288de2ab02SWei Ni soctherm_clk_enable(pdev, false);
222965b6d57cSWei Ni
223065b6d57cSWei Ni return 0;
223165b6d57cSWei Ni }
223265b6d57cSWei Ni
soctherm_suspend(struct device * dev)2233a977c41eSArnd Bergmann static int __maybe_unused soctherm_suspend(struct device *dev)
2234f09d6984SWei Ni {
2235f09d6984SWei Ni struct platform_device *pdev = to_platform_device(dev);
2236f09d6984SWei Ni
2237f09d6984SWei Ni soctherm_clk_enable(pdev, false);
2238f09d6984SWei Ni
2239f09d6984SWei Ni return 0;
2240f09d6984SWei Ni }
2241f09d6984SWei Ni
soctherm_resume(struct device * dev)2242a977c41eSArnd Bergmann static int __maybe_unused soctherm_resume(struct device *dev)
2243f09d6984SWei Ni {
2244f09d6984SWei Ni struct platform_device *pdev = to_platform_device(dev);
2245f09d6984SWei Ni struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
2246f09d6984SWei Ni struct tegra_soctherm_soc *soc = tegra->soc;
2247f09d6984SWei Ni int err, i;
2248f09d6984SWei Ni
2249f09d6984SWei Ni err = soctherm_clk_enable(pdev, true);
2250f09d6984SWei Ni if (err) {
2251f09d6984SWei Ni dev_err(&pdev->dev,
2252f09d6984SWei Ni "Resume failed: enable clocks failed\n");
2253f09d6984SWei Ni return err;
2254f09d6984SWei Ni }
2255f09d6984SWei Ni
2256f09d6984SWei Ni soctherm_init(pdev);
2257f09d6984SWei Ni
2258f09d6984SWei Ni for (i = 0; i < soc->num_ttgs; ++i) {
2259f09d6984SWei Ni struct thermal_zone_device *tz;
2260f09d6984SWei Ni
2261f09d6984SWei Ni tz = tegra->thermctl_tzs[soc->ttgs[i]->id];
2262ce0dbf04SWei Ni err = tegra_soctherm_set_hwtrips(dev, soc->ttgs[i], tz);
2263ce0dbf04SWei Ni if (err) {
2264ce0dbf04SWei Ni dev_err(&pdev->dev,
2265ce0dbf04SWei Ni "Resume failed: set hwtrips failed\n");
2266ce0dbf04SWei Ni return err;
2267ce0dbf04SWei Ni }
2268f09d6984SWei Ni }
2269f09d6984SWei Ni
2270f09d6984SWei Ni return 0;
2271f09d6984SWei Ni }
2272f09d6984SWei Ni
2273f09d6984SWei Ni static SIMPLE_DEV_PM_OPS(tegra_soctherm_pm, soctherm_suspend, soctherm_resume);
2274f09d6984SWei Ni
227565b6d57cSWei Ni static struct platform_driver tegra_soctherm_driver = {
227665b6d57cSWei Ni .probe = tegra_soctherm_probe,
227765b6d57cSWei Ni .remove = tegra_soctherm_remove,
227865b6d57cSWei Ni .driver = {
227965b6d57cSWei Ni .name = "tegra_soctherm",
2280f09d6984SWei Ni .pm = &tegra_soctherm_pm,
228165b6d57cSWei Ni .of_match_table = tegra_soctherm_of_match,
228265b6d57cSWei Ni },
228365b6d57cSWei Ni };
228465b6d57cSWei Ni module_platform_driver(tegra_soctherm_driver);
228565b6d57cSWei Ni
228665b6d57cSWei Ni MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
228765b6d57cSWei Ni MODULE_DESCRIPTION("NVIDIA Tegra SOCTHERM thermal management driver");
228865b6d57cSWei Ni MODULE_LICENSE("GPL v2");
2289