xref: /openbmc/linux/drivers/thermal/tegra/soctherm.c (revision 5f68d078)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2014 - 2018, NVIDIA CORPORATION.  All rights reserved.
4  *
5  * Author:
6  *	Mikko Perttunen <mperttunen@nvidia.com>
7  *
8  * This software is licensed under the terms of the GNU General Public
9  * License version 2, as published by the Free Software Foundation, and
10  * may be copied, distributed, and modified under those terms.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  */
18 
19 #include <linux/debugfs.h>
20 #include <linux/bitops.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/err.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/irq.h>
27 #include <linux/irqdomain.h>
28 #include <linux/module.h>
29 #include <linux/of.h>
30 #include <linux/platform_device.h>
31 #include <linux/reset.h>
32 #include <linux/thermal.h>
33 
34 #include <dt-bindings/thermal/tegra124-soctherm.h>
35 
36 #include "../thermal_core.h"
37 #include "soctherm.h"
38 
39 #define SENSOR_CONFIG0				0
40 #define SENSOR_CONFIG0_STOP			BIT(0)
41 #define SENSOR_CONFIG0_CPTR_OVER		BIT(2)
42 #define SENSOR_CONFIG0_OVER			BIT(3)
43 #define SENSOR_CONFIG0_TCALC_OVER		BIT(4)
44 #define SENSOR_CONFIG0_TALL_MASK		(0xfffff << 8)
45 #define SENSOR_CONFIG0_TALL_SHIFT		8
46 
47 #define SENSOR_CONFIG1				4
48 #define SENSOR_CONFIG1_TSAMPLE_MASK		0x3ff
49 #define SENSOR_CONFIG1_TSAMPLE_SHIFT		0
50 #define SENSOR_CONFIG1_TIDDQ_EN_MASK		(0x3f << 15)
51 #define SENSOR_CONFIG1_TIDDQ_EN_SHIFT		15
52 #define SENSOR_CONFIG1_TEN_COUNT_MASK		(0x3f << 24)
53 #define SENSOR_CONFIG1_TEN_COUNT_SHIFT		24
54 #define SENSOR_CONFIG1_TEMP_ENABLE		BIT(31)
55 
56 /*
57  * SENSOR_CONFIG2 is defined in soctherm.h
58  * because, it will be used by tegra_soctherm_fuse.c
59  */
60 
61 #define SENSOR_STATUS0				0xc
62 #define SENSOR_STATUS0_VALID_MASK		BIT(31)
63 #define SENSOR_STATUS0_CAPTURE_MASK		0xffff
64 
65 #define SENSOR_STATUS1				0x10
66 #define SENSOR_STATUS1_TEMP_VALID_MASK		BIT(31)
67 #define SENSOR_STATUS1_TEMP_MASK		0xffff
68 
69 #define READBACK_VALUE_MASK			0xff00
70 #define READBACK_VALUE_SHIFT			8
71 #define READBACK_ADD_HALF			BIT(7)
72 #define READBACK_NEGATE				BIT(0)
73 
74 /*
75  * THERMCTL_LEVEL0_GROUP_CPU is defined in soctherm.h
76  * because it will be used by tegraxxx_soctherm.c
77  */
78 #define THERMCTL_LVL0_CPU0_EN_MASK		BIT(8)
79 #define THERMCTL_LVL0_CPU0_CPU_THROT_MASK	(0x3 << 5)
80 #define THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT	0x1
81 #define THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY	0x2
82 #define THERMCTL_LVL0_CPU0_GPU_THROT_MASK	(0x3 << 3)
83 #define THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT	0x1
84 #define THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY	0x2
85 #define THERMCTL_LVL0_CPU0_MEM_THROT_MASK	BIT(2)
86 #define THERMCTL_LVL0_CPU0_STATUS_MASK		0x3
87 
88 #define THERMCTL_LVL0_UP_STATS			0x10
89 #define THERMCTL_LVL0_DN_STATS			0x14
90 
91 #define THERMCTL_INTR_STATUS			0x84
92 
93 #define TH_INTR_MD0_MASK			BIT(25)
94 #define TH_INTR_MU0_MASK			BIT(24)
95 #define TH_INTR_GD0_MASK			BIT(17)
96 #define TH_INTR_GU0_MASK			BIT(16)
97 #define TH_INTR_CD0_MASK			BIT(9)
98 #define TH_INTR_CU0_MASK			BIT(8)
99 #define TH_INTR_PD0_MASK			BIT(1)
100 #define TH_INTR_PU0_MASK			BIT(0)
101 #define TH_INTR_IGNORE_MASK			0xFCFCFCFC
102 
103 #define THERMCTL_STATS_CTL			0x94
104 #define STATS_CTL_CLR_DN			0x8
105 #define STATS_CTL_EN_DN				0x4
106 #define STATS_CTL_CLR_UP			0x2
107 #define STATS_CTL_EN_UP				0x1
108 
109 #define OC1_CFG					0x310
110 #define OC1_CFG_LONG_LATENCY_MASK		BIT(6)
111 #define OC1_CFG_HW_RESTORE_MASK			BIT(5)
112 #define OC1_CFG_PWR_GOOD_MASK_MASK		BIT(4)
113 #define OC1_CFG_THROTTLE_MODE_MASK		(0x3 << 2)
114 #define OC1_CFG_ALARM_POLARITY_MASK		BIT(1)
115 #define OC1_CFG_EN_THROTTLE_MASK		BIT(0)
116 
117 #define OC1_CNT_THRESHOLD			0x314
118 #define OC1_THROTTLE_PERIOD			0x318
119 #define OC1_ALARM_COUNT				0x31c
120 #define OC1_FILTER				0x320
121 #define OC1_STATS				0x3a8
122 
123 #define OC_INTR_STATUS				0x39c
124 #define OC_INTR_ENABLE				0x3a0
125 #define OC_INTR_DISABLE				0x3a4
126 #define OC_STATS_CTL				0x3c4
127 #define OC_STATS_CTL_CLR_ALL			0x2
128 #define OC_STATS_CTL_EN_ALL			0x1
129 
130 #define OC_INTR_OC1_MASK			BIT(0)
131 #define OC_INTR_OC2_MASK			BIT(1)
132 #define OC_INTR_OC3_MASK			BIT(2)
133 #define OC_INTR_OC4_MASK			BIT(3)
134 #define OC_INTR_OC5_MASK			BIT(4)
135 
136 #define THROT_GLOBAL_CFG			0x400
137 #define THROT_GLOBAL_ENB_MASK			BIT(0)
138 
139 #define CPU_PSKIP_STATUS			0x418
140 #define XPU_PSKIP_STATUS_M_MASK			(0xff << 12)
141 #define XPU_PSKIP_STATUS_N_MASK			(0xff << 4)
142 #define XPU_PSKIP_STATUS_SW_OVERRIDE_MASK	BIT(1)
143 #define XPU_PSKIP_STATUS_ENABLED_MASK		BIT(0)
144 
145 #define THROT_PRIORITY_LOCK			0x424
146 #define THROT_PRIORITY_LOCK_PRIORITY_MASK	0xff
147 
148 #define THROT_STATUS				0x428
149 #define THROT_STATUS_BREACH_MASK		BIT(12)
150 #define THROT_STATUS_STATE_MASK			(0xff << 4)
151 #define THROT_STATUS_ENABLED_MASK		BIT(0)
152 
153 #define THROT_PSKIP_CTRL_LITE_CPU		0x430
154 #define THROT_PSKIP_CTRL_ENABLE_MASK            BIT(31)
155 #define THROT_PSKIP_CTRL_DIVIDEND_MASK          (0xff << 8)
156 #define THROT_PSKIP_CTRL_DIVISOR_MASK           0xff
157 #define THROT_PSKIP_CTRL_VECT_GPU_MASK          (0x7 << 16)
158 #define THROT_PSKIP_CTRL_VECT_CPU_MASK          (0x7 << 8)
159 #define THROT_PSKIP_CTRL_VECT2_CPU_MASK         0x7
160 
161 #define THROT_VECT_NONE				0x0 /* 3'b000 */
162 #define THROT_VECT_LOW				0x1 /* 3'b001 */
163 #define THROT_VECT_MED				0x3 /* 3'b011 */
164 #define THROT_VECT_HIGH				0x7 /* 3'b111 */
165 
166 #define THROT_PSKIP_RAMP_LITE_CPU		0x434
167 #define THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK	BIT(31)
168 #define THROT_PSKIP_RAMP_DURATION_MASK		(0xffff << 8)
169 #define THROT_PSKIP_RAMP_STEP_MASK		0xff
170 
171 #define THROT_PRIORITY_LITE			0x444
172 #define THROT_PRIORITY_LITE_PRIO_MASK		0xff
173 
174 #define THROT_DELAY_LITE			0x448
175 #define THROT_DELAY_LITE_DELAY_MASK		0xff
176 
177 /* car register offsets needed for enabling HW throttling */
178 #define CAR_SUPER_CCLKG_DIVIDER			0x36c
179 #define CDIVG_USE_THERM_CONTROLS_MASK		BIT(30)
180 
181 /* ccroc register offsets needed for enabling HW throttling for Tegra132 */
182 #define CCROC_SUPER_CCLKG_DIVIDER		0x024
183 
184 #define CCROC_GLOBAL_CFG			0x148
185 
186 #define CCROC_THROT_PSKIP_RAMP_CPU		0x150
187 #define CCROC_THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK	BIT(31)
188 #define CCROC_THROT_PSKIP_RAMP_DURATION_MASK	(0xffff << 8)
189 #define CCROC_THROT_PSKIP_RAMP_STEP_MASK	0xff
190 
191 #define CCROC_THROT_PSKIP_CTRL_CPU		0x154
192 #define CCROC_THROT_PSKIP_CTRL_ENB_MASK		BIT(31)
193 #define CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK	(0xff << 8)
194 #define CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK	0xff
195 
196 /* get val from register(r) mask bits(m) */
197 #define REG_GET_MASK(r, m)	(((r) & (m)) >> (ffs(m) - 1))
198 /* set val(v) to mask bits(m) of register(r) */
199 #define REG_SET_MASK(r, m, v)	(((r) & ~(m)) | \
200 				 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
201 
202 /* get dividend from the depth */
203 #define THROT_DEPTH_DIVIDEND(depth)	((256 * (100 - (depth)) / 100) - 1)
204 
205 /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h
206  * level	vector
207  * NONE		3'b000
208  * LOW		3'b001
209  * MED		3'b011
210  * HIGH		3'b111
211  */
212 #define THROT_LEVEL_TO_DEPTH(level)	((0x1 << (level)) - 1)
213 
214 /* get THROT_PSKIP_xxx offset per LIGHT/HEAVY throt and CPU/GPU dev */
215 #define THROT_OFFSET			0x30
216 #define THROT_PSKIP_CTRL(throt, dev)	(THROT_PSKIP_CTRL_LITE_CPU + \
217 					(THROT_OFFSET * throt) + (8 * dev))
218 #define THROT_PSKIP_RAMP(throt, dev)	(THROT_PSKIP_RAMP_LITE_CPU + \
219 					(THROT_OFFSET * throt) + (8 * dev))
220 
221 /* get THROT_xxx_CTRL offset per LIGHT/HEAVY throt */
222 #define THROT_PRIORITY_CTRL(throt)	(THROT_PRIORITY_LITE + \
223 					(THROT_OFFSET * throt))
224 #define THROT_DELAY_CTRL(throt)		(THROT_DELAY_LITE + \
225 					(THROT_OFFSET * throt))
226 
227 #define ALARM_OFFSET			0x14
228 #define ALARM_CFG(throt)		(OC1_CFG + \
229 					(ALARM_OFFSET * (throt - THROTTLE_OC1)))
230 
231 #define ALARM_CNT_THRESHOLD(throt)	(OC1_CNT_THRESHOLD + \
232 					(ALARM_OFFSET * (throt - THROTTLE_OC1)))
233 
234 #define ALARM_THROTTLE_PERIOD(throt)	(OC1_THROTTLE_PERIOD + \
235 					(ALARM_OFFSET * (throt - THROTTLE_OC1)))
236 
237 #define ALARM_ALARM_COUNT(throt)	(OC1_ALARM_COUNT + \
238 					(ALARM_OFFSET * (throt - THROTTLE_OC1)))
239 
240 #define ALARM_FILTER(throt)		(OC1_FILTER + \
241 					(ALARM_OFFSET * (throt - THROTTLE_OC1)))
242 
243 #define ALARM_STATS(throt)		(OC1_STATS + \
244 					(4 * (throt - THROTTLE_OC1)))
245 
246 /* get CCROC_THROT_PSKIP_xxx offset per HIGH/MED/LOW vect*/
247 #define CCROC_THROT_OFFSET			0x0c
248 #define CCROC_THROT_PSKIP_CTRL_CPU_REG(vect)    (CCROC_THROT_PSKIP_CTRL_CPU + \
249 						(CCROC_THROT_OFFSET * vect))
250 #define CCROC_THROT_PSKIP_RAMP_CPU_REG(vect)    (CCROC_THROT_PSKIP_RAMP_CPU + \
251 						(CCROC_THROT_OFFSET * vect))
252 
253 /* get THERMCTL_LEVELx offset per CPU/GPU/MEM/TSENSE rg and LEVEL0~3 lv */
254 #define THERMCTL_LVL_REGS_SIZE		0x20
255 #define THERMCTL_LVL_REG(rg, lv)	((rg) + ((lv) * THERMCTL_LVL_REGS_SIZE))
256 
257 #define OC_THROTTLE_MODE_DISABLED	0
258 #define OC_THROTTLE_MODE_BRIEF		2
259 
260 static const int min_low_temp = -127000;
261 static const int max_high_temp = 127000;
262 
263 enum soctherm_throttle_id {
264 	THROTTLE_LIGHT = 0,
265 	THROTTLE_HEAVY,
266 	THROTTLE_OC1,
267 	THROTTLE_OC2,
268 	THROTTLE_OC3,
269 	THROTTLE_OC4,
270 	THROTTLE_OC5, /* OC5 is reserved */
271 	THROTTLE_SIZE,
272 };
273 
274 enum soctherm_oc_irq_id {
275 	TEGRA_SOC_OC_IRQ_1,
276 	TEGRA_SOC_OC_IRQ_2,
277 	TEGRA_SOC_OC_IRQ_3,
278 	TEGRA_SOC_OC_IRQ_4,
279 	TEGRA_SOC_OC_IRQ_5,
280 	TEGRA_SOC_OC_IRQ_MAX,
281 };
282 
283 enum soctherm_throttle_dev_id {
284 	THROTTLE_DEV_CPU = 0,
285 	THROTTLE_DEV_GPU,
286 	THROTTLE_DEV_SIZE,
287 };
288 
289 static const char *const throt_names[] = {
290 	[THROTTLE_LIGHT] = "light",
291 	[THROTTLE_HEAVY] = "heavy",
292 	[THROTTLE_OC1]   = "oc1",
293 	[THROTTLE_OC2]   = "oc2",
294 	[THROTTLE_OC3]   = "oc3",
295 	[THROTTLE_OC4]   = "oc4",
296 	[THROTTLE_OC5]   = "oc5",
297 };
298 
299 struct tegra_soctherm;
300 struct tegra_thermctl_zone {
301 	void __iomem *reg;
302 	struct device *dev;
303 	struct tegra_soctherm *ts;
304 	struct thermal_zone_device *tz;
305 	const struct tegra_tsensor_group *sg;
306 };
307 
308 struct soctherm_oc_cfg {
309 	u32 active_low;
310 	u32 throt_period;
311 	u32 alarm_cnt_thresh;
312 	u32 alarm_filter;
313 	u32 mode;
314 	bool intr_en;
315 };
316 
317 struct soctherm_throt_cfg {
318 	const char *name;
319 	unsigned int id;
320 	u8 priority;
321 	u8 cpu_throt_level;
322 	u32 cpu_throt_depth;
323 	u32 gpu_throt_level;
324 	struct soctherm_oc_cfg oc_cfg;
325 	struct thermal_cooling_device *cdev;
326 	bool init;
327 };
328 
329 struct tegra_soctherm {
330 	struct reset_control *reset;
331 	struct clk *clock_tsensor;
332 	struct clk *clock_soctherm;
333 	void __iomem *regs;
334 	void __iomem *clk_regs;
335 	void __iomem *ccroc_regs;
336 
337 	int thermal_irq;
338 	int edp_irq;
339 
340 	u32 *calib;
341 	struct thermal_zone_device **thermctl_tzs;
342 	struct tegra_soctherm_soc *soc;
343 
344 	struct soctherm_throt_cfg throt_cfgs[THROTTLE_SIZE];
345 
346 	struct dentry *debugfs_dir;
347 
348 	struct mutex thermctl_lock;
349 };
350 
351 struct soctherm_oc_irq_chip_data {
352 	struct mutex		irq_lock; /* serialize OC IRQs */
353 	struct irq_chip		irq_chip;
354 	struct irq_domain	*domain;
355 	int			irq_enable;
356 };
357 
358 static struct soctherm_oc_irq_chip_data soc_irq_cdata;
359 
360 /**
361  * ccroc_writel() - writes a value to a CCROC register
362  * @ts: pointer to a struct tegra_soctherm
363  * @value: the value to write
364  * @reg: the register offset
365  *
366  * Writes @v to @reg.  No return value.
367  */
ccroc_writel(struct tegra_soctherm * ts,u32 value,u32 reg)368 static inline void ccroc_writel(struct tegra_soctherm *ts, u32 value, u32 reg)
369 {
370 	writel(value, (ts->ccroc_regs + reg));
371 }
372 
373 /**
374  * ccroc_readl() - reads specified register from CCROC IP block
375  * @ts: pointer to a struct tegra_soctherm
376  * @reg: register address to be read
377  *
378  * Return: the value of the register
379  */
ccroc_readl(struct tegra_soctherm * ts,u32 reg)380 static inline u32 ccroc_readl(struct tegra_soctherm *ts, u32 reg)
381 {
382 	return readl(ts->ccroc_regs + reg);
383 }
384 
enable_tsensor(struct tegra_soctherm * tegra,unsigned int i)385 static void enable_tsensor(struct tegra_soctherm *tegra, unsigned int i)
386 {
387 	const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i];
388 	void __iomem *base = tegra->regs + sensor->base;
389 	unsigned int val;
390 
391 	val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT;
392 	writel(val, base + SENSOR_CONFIG0);
393 
394 	val  = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT;
395 	val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
396 	val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
397 	val |= SENSOR_CONFIG1_TEMP_ENABLE;
398 	writel(val, base + SENSOR_CONFIG1);
399 
400 	writel(tegra->calib[i], base + SENSOR_CONFIG2);
401 }
402 
403 /*
404  * Translate from soctherm readback format to millicelsius.
405  * The soctherm readback format in bits is as follows:
406  *   TTTTTTTT H______N
407  * where T's contain the temperature in Celsius,
408  * H denotes an addition of 0.5 Celsius and N denotes negation
409  * of the final value.
410  */
translate_temp(u16 val)411 static int translate_temp(u16 val)
412 {
413 	int t;
414 
415 	t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
416 	if (val & READBACK_ADD_HALF)
417 		t += 500;
418 	if (val & READBACK_NEGATE)
419 		t *= -1;
420 
421 	return t;
422 }
423 
tegra_thermctl_get_temp(struct thermal_zone_device * tz,int * out_temp)424 static int tegra_thermctl_get_temp(struct thermal_zone_device *tz, int *out_temp)
425 {
426 	struct tegra_thermctl_zone *zone = thermal_zone_device_priv(tz);
427 	u32 val;
428 
429 	val = readl(zone->reg);
430 	val = REG_GET_MASK(val, zone->sg->sensor_temp_mask);
431 	*out_temp = translate_temp(val);
432 
433 	return 0;
434 }
435 
436 /**
437  * enforce_temp_range() - check and enforce temperature range [min, max]
438  * @dev: struct device * of the SOC_THERM instance
439  * @trip_temp: the trip temperature to check
440  *
441  * Checks and enforces the permitted temperature range that SOC_THERM
442  * HW can support This is
443  * done while taking care of precision.
444  *
445  * Return: The precision adjusted capped temperature in millicelsius.
446  */
enforce_temp_range(struct device * dev,int trip_temp)447 static int enforce_temp_range(struct device *dev, int trip_temp)
448 {
449 	int temp;
450 
451 	temp = clamp_val(trip_temp, min_low_temp, max_high_temp);
452 	if (temp != trip_temp)
453 		dev_dbg(dev, "soctherm: trip temperature %d forced to %d\n",
454 			trip_temp, temp);
455 	return temp;
456 }
457 
458 /**
459  * thermtrip_program() - Configures the hardware to shut down the
460  * system if a given sensor group reaches a given temperature
461  * @dev: ptr to the struct device for the SOC_THERM IP block
462  * @sg: pointer to the sensor group to set the thermtrip temperature for
463  * @trip_temp: the temperature in millicelsius to trigger the thermal trip at
464  *
465  * Sets the thermal trip threshold of the given sensor group to be the
466  * @trip_temp.  If this threshold is crossed, the hardware will shut
467  * down.
468  *
469  * Note that, although @trip_temp is specified in millicelsius, the
470  * hardware is programmed in degrees Celsius.
471  *
472  * Return: 0 upon success, or %-EINVAL upon failure.
473  */
thermtrip_program(struct device * dev,const struct tegra_tsensor_group * sg,int trip_temp)474 static int thermtrip_program(struct device *dev,
475 			     const struct tegra_tsensor_group *sg,
476 			     int trip_temp)
477 {
478 	struct tegra_soctherm *ts = dev_get_drvdata(dev);
479 	int temp;
480 	u32 r;
481 
482 	if (!sg || !sg->thermtrip_threshold_mask)
483 		return -EINVAL;
484 
485 	temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain;
486 
487 	r = readl(ts->regs + THERMCTL_THERMTRIP_CTL);
488 	r = REG_SET_MASK(r, sg->thermtrip_threshold_mask, temp);
489 	r = REG_SET_MASK(r, sg->thermtrip_enable_mask, 1);
490 	r = REG_SET_MASK(r, sg->thermtrip_any_en_mask, 0);
491 	writel(r, ts->regs + THERMCTL_THERMTRIP_CTL);
492 
493 	return 0;
494 }
495 
496 /**
497  * throttrip_program() - Configures the hardware to throttle the
498  * pulse if a given sensor group reaches a given temperature
499  * @dev: ptr to the struct device for the SOC_THERM IP block
500  * @sg: pointer to the sensor group to set the thermtrip temperature for
501  * @stc: pointer to the throttle need to be triggered
502  * @trip_temp: the temperature in millicelsius to trigger the thermal trip at
503  *
504  * Sets the thermal trip threshold and throttle event of the given sensor
505  * group. If this threshold is crossed, the hardware will trigger the
506  * throttle.
507  *
508  * Note that, although @trip_temp is specified in millicelsius, the
509  * hardware is programmed in degrees Celsius.
510  *
511  * Return: 0 upon success, or %-EINVAL upon failure.
512  */
throttrip_program(struct device * dev,const struct tegra_tsensor_group * sg,struct soctherm_throt_cfg * stc,int trip_temp)513 static int throttrip_program(struct device *dev,
514 			     const struct tegra_tsensor_group *sg,
515 			     struct soctherm_throt_cfg *stc,
516 			     int trip_temp)
517 {
518 	struct tegra_soctherm *ts = dev_get_drvdata(dev);
519 	int temp, cpu_throt, gpu_throt;
520 	unsigned int throt;
521 	u32 r, reg_off;
522 
523 	if (!sg || !stc || !stc->init)
524 		return -EINVAL;
525 
526 	temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain;
527 
528 	/* Hardcode LIGHT on LEVEL1 and HEAVY on LEVEL2 */
529 	throt = stc->id;
530 	reg_off = THERMCTL_LVL_REG(sg->thermctl_lvl0_offset, throt + 1);
531 
532 	if (throt == THROTTLE_LIGHT) {
533 		cpu_throt = THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT;
534 		gpu_throt = THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT;
535 	} else {
536 		cpu_throt = THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY;
537 		gpu_throt = THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY;
538 		if (throt != THROTTLE_HEAVY)
539 			dev_warn(dev,
540 				 "invalid throt id %d - assuming HEAVY",
541 				 throt);
542 	}
543 
544 	r = readl(ts->regs + reg_off);
545 	r = REG_SET_MASK(r, sg->thermctl_lvl0_up_thresh_mask, temp);
546 	r = REG_SET_MASK(r, sg->thermctl_lvl0_dn_thresh_mask, temp);
547 	r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_CPU_THROT_MASK, cpu_throt);
548 	r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_GPU_THROT_MASK, gpu_throt);
549 	r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1);
550 	writel(r, ts->regs + reg_off);
551 
552 	return 0;
553 }
554 
555 static struct soctherm_throt_cfg *
find_throttle_cfg_by_name(struct tegra_soctherm * ts,const char * name)556 find_throttle_cfg_by_name(struct tegra_soctherm *ts, const char *name)
557 {
558 	unsigned int i;
559 
560 	for (i = 0; ts->throt_cfgs[i].name; i++)
561 		if (!strcmp(ts->throt_cfgs[i].name, name))
562 			return &ts->throt_cfgs[i];
563 
564 	return NULL;
565 }
566 
tsensor_group_thermtrip_get(struct tegra_soctherm * ts,int id)567 static int tsensor_group_thermtrip_get(struct tegra_soctherm *ts, int id)
568 {
569 	int i, temp = min_low_temp;
570 	struct tsensor_group_thermtrips *tt = ts->soc->thermtrips;
571 
572 	if (id >= TEGRA124_SOCTHERM_SENSOR_NUM)
573 		return temp;
574 
575 	if (tt) {
576 		for (i = 0; i < ts->soc->num_ttgs; i++) {
577 			if (tt[i].id == id)
578 				return tt[i].temp;
579 		}
580 	}
581 
582 	return temp;
583 }
584 
tegra_thermctl_set_trip_temp(struct thermal_zone_device * tz,int trip_id,int temp)585 static int tegra_thermctl_set_trip_temp(struct thermal_zone_device *tz, int trip_id, int temp)
586 {
587 	struct tegra_thermctl_zone *zone = thermal_zone_device_priv(tz);
588 	struct tegra_soctherm *ts = zone->ts;
589 	struct thermal_trip trip;
590 	const struct tegra_tsensor_group *sg = zone->sg;
591 	struct device *dev = zone->dev;
592 	int ret;
593 
594 	if (!tz)
595 		return -EINVAL;
596 
597 	ret = __thermal_zone_get_trip(tz, trip_id, &trip);
598 	if (ret)
599 		return ret;
600 
601 	if (trip.type == THERMAL_TRIP_CRITICAL) {
602 		/*
603 		 * If thermtrips property is set in DT,
604 		 * doesn't need to program critical type trip to HW,
605 		 * if not, program critical trip to HW.
606 		 */
607 		if (min_low_temp == tsensor_group_thermtrip_get(ts, sg->id))
608 			return thermtrip_program(dev, sg, temp);
609 		else
610 			return 0;
611 
612 	} else if (trip.type == THERMAL_TRIP_HOT) {
613 		int i;
614 
615 		for (i = 0; i < THROTTLE_SIZE; i++) {
616 			struct thermal_cooling_device *cdev;
617 			struct soctherm_throt_cfg *stc;
618 
619 			if (!ts->throt_cfgs[i].init)
620 				continue;
621 
622 			cdev = ts->throt_cfgs[i].cdev;
623 			if (get_thermal_instance(tz, cdev, trip_id))
624 				stc = find_throttle_cfg_by_name(ts, cdev->type);
625 			else
626 				continue;
627 
628 			return throttrip_program(dev, sg, stc, temp);
629 		}
630 	}
631 
632 	return 0;
633 }
634 
thermal_irq_enable(struct tegra_thermctl_zone * zn)635 static void thermal_irq_enable(struct tegra_thermctl_zone *zn)
636 {
637 	u32 r;
638 
639 	/* multiple zones could be handling and setting trips at once */
640 	mutex_lock(&zn->ts->thermctl_lock);
641 	r = readl(zn->ts->regs + THERMCTL_INTR_ENABLE);
642 	r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, TH_INTR_UP_DN_EN);
643 	writel(r, zn->ts->regs + THERMCTL_INTR_ENABLE);
644 	mutex_unlock(&zn->ts->thermctl_lock);
645 }
646 
thermal_irq_disable(struct tegra_thermctl_zone * zn)647 static void thermal_irq_disable(struct tegra_thermctl_zone *zn)
648 {
649 	u32 r;
650 
651 	/* multiple zones could be handling and setting trips at once */
652 	mutex_lock(&zn->ts->thermctl_lock);
653 	r = readl(zn->ts->regs + THERMCTL_INTR_DISABLE);
654 	r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, 0);
655 	writel(r, zn->ts->regs + THERMCTL_INTR_DISABLE);
656 	mutex_unlock(&zn->ts->thermctl_lock);
657 }
658 
tegra_thermctl_set_trips(struct thermal_zone_device * tz,int lo,int hi)659 static int tegra_thermctl_set_trips(struct thermal_zone_device *tz, int lo, int hi)
660 {
661 	struct tegra_thermctl_zone *zone = thermal_zone_device_priv(tz);
662 	u32 r;
663 
664 	thermal_irq_disable(zone);
665 
666 	r = readl(zone->ts->regs + zone->sg->thermctl_lvl0_offset);
667 	r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 0);
668 	writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset);
669 
670 	lo = enforce_temp_range(zone->dev, lo) / zone->ts->soc->thresh_grain;
671 	hi = enforce_temp_range(zone->dev, hi) / zone->ts->soc->thresh_grain;
672 	dev_dbg(zone->dev, "%s hi:%d, lo:%d\n", __func__, hi, lo);
673 
674 	r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_up_thresh_mask, hi);
675 	r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_dn_thresh_mask, lo);
676 	r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1);
677 	writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset);
678 
679 	thermal_irq_enable(zone);
680 
681 	return 0;
682 }
683 
684 static const struct thermal_zone_device_ops tegra_of_thermal_ops = {
685 	.get_temp = tegra_thermctl_get_temp,
686 	.set_trip_temp = tegra_thermctl_set_trip_temp,
687 	.set_trips = tegra_thermctl_set_trips,
688 };
689 
get_hot_temp(struct thermal_zone_device * tz,int * trip_id,int * temp)690 static int get_hot_temp(struct thermal_zone_device *tz, int *trip_id, int *temp)
691 {
692 	int i, ret;
693 	struct thermal_trip trip;
694 
695 	for (i = 0; i < thermal_zone_get_num_trips(tz); i++) {
696 
697 		ret = thermal_zone_get_trip(tz, i, &trip);
698 		if (ret)
699 			return -EINVAL;
700 
701 		if (trip.type == THERMAL_TRIP_HOT) {
702 			*trip_id = i;
703 			return 0;
704 		}
705 	}
706 
707 	return -EINVAL;
708 }
709 
710 /**
711  * tegra_soctherm_set_hwtrips() - set HW trip point from DT data
712  * @dev: struct device * of the SOC_THERM instance
713  * @sg: pointer to the sensor group to set the thermtrip temperature for
714  * @tz: struct thermal_zone_device *
715  *
716  * Configure the SOC_THERM HW trip points, setting "THERMTRIP"
717  * "THROTTLE" trip points , using "thermtrips", "critical" or "hot"
718  * type trip_temp
719  * from thermal zone.
720  * After they have been configured, THERMTRIP or THROTTLE will take
721  * action when the configured SoC thermal sensor group reaches a
722  * certain temperature.
723  *
724  * Return: 0 upon success, or a negative error code on failure.
725  * "Success" does not mean that trips was enabled; it could also
726  * mean that no node was found in DT.
727  * THERMTRIP has been enabled successfully when a message similar to
728  * this one appears on the serial console:
729  * "thermtrip: will shut down when sensor group XXX reaches YYYYYY mC"
730  * THROTTLE has been enabled successfully when a message similar to
731  * this one appears on the serial console:
732  * ""throttrip: will throttle when sensor group XXX reaches YYYYYY mC"
733  */
tegra_soctherm_set_hwtrips(struct device * dev,const struct tegra_tsensor_group * sg,struct thermal_zone_device * tz)734 static int tegra_soctherm_set_hwtrips(struct device *dev,
735 				      const struct tegra_tsensor_group *sg,
736 				      struct thermal_zone_device *tz)
737 {
738 	struct tegra_soctherm *ts = dev_get_drvdata(dev);
739 	struct soctherm_throt_cfg *stc;
740 	int i, trip, temperature, ret;
741 
742 	/* Get thermtrips. If missing, try to get critical trips. */
743 	temperature = tsensor_group_thermtrip_get(ts, sg->id);
744 	if (min_low_temp == temperature)
745 		if (thermal_zone_get_crit_temp(tz, &temperature))
746 			temperature = max_high_temp;
747 
748 	ret = thermtrip_program(dev, sg, temperature);
749 	if (ret) {
750 		dev_err(dev, "thermtrip: %s: error during enable\n", sg->name);
751 		return ret;
752 	}
753 
754 	dev_info(dev, "thermtrip: will shut down when %s reaches %d mC\n",
755 		 sg->name, temperature);
756 
757 	ret = get_hot_temp(tz, &trip, &temperature);
758 	if (ret) {
759 		dev_info(dev, "throttrip: %s: missing hot temperature\n",
760 			 sg->name);
761 		return 0;
762 	}
763 
764 	for (i = 0; i < THROTTLE_OC1; i++) {
765 		struct thermal_cooling_device *cdev;
766 
767 		if (!ts->throt_cfgs[i].init)
768 			continue;
769 
770 		cdev = ts->throt_cfgs[i].cdev;
771 		if (get_thermal_instance(tz, cdev, trip))
772 			stc = find_throttle_cfg_by_name(ts, cdev->type);
773 		else
774 			continue;
775 
776 		ret = throttrip_program(dev, sg, stc, temperature);
777 		if (ret) {
778 			dev_err(dev, "throttrip: %s: error during enable\n",
779 				sg->name);
780 			return ret;
781 		}
782 
783 		dev_info(dev,
784 			 "throttrip: will throttle when %s reaches %d mC\n",
785 			 sg->name, temperature);
786 		break;
787 	}
788 
789 	if (i == THROTTLE_SIZE)
790 		dev_info(dev, "throttrip: %s: missing throttle cdev\n",
791 			 sg->name);
792 
793 	return 0;
794 }
795 
soctherm_thermal_isr(int irq,void * dev_id)796 static irqreturn_t soctherm_thermal_isr(int irq, void *dev_id)
797 {
798 	struct tegra_soctherm *ts = dev_id;
799 	u32 r;
800 
801 	/* Case for no lock:
802 	 * Although interrupts are enabled in set_trips, there is still no need
803 	 * to lock here because the interrupts are disabled before programming
804 	 * new trip points. Hence there cant be a interrupt on the same sensor.
805 	 * An interrupt can however occur on a sensor while trips are being
806 	 * programmed on a different one. This beign a LEVEL interrupt won't
807 	 * cause a new interrupt but this is taken care of by the re-reading of
808 	 * the STATUS register in the thread function.
809 	 */
810 	r = readl(ts->regs + THERMCTL_INTR_STATUS);
811 	writel(r, ts->regs + THERMCTL_INTR_DISABLE);
812 
813 	return IRQ_WAKE_THREAD;
814 }
815 
816 /**
817  * soctherm_thermal_isr_thread() - Handles a thermal interrupt request
818  * @irq:       The interrupt number being requested; not used
819  * @dev_id:    Opaque pointer to tegra_soctherm;
820  *
821  * Clears the interrupt status register if there are expected
822  * interrupt bits set.
823  * The interrupt(s) are then handled by updating the corresponding
824  * thermal zones.
825  *
826  * An error is logged if any unexpected interrupt bits are set.
827  *
828  * Disabled interrupts are re-enabled.
829  *
830  * Return: %IRQ_HANDLED. Interrupt was handled and no further processing
831  * is needed.
832  */
soctherm_thermal_isr_thread(int irq,void * dev_id)833 static irqreturn_t soctherm_thermal_isr_thread(int irq, void *dev_id)
834 {
835 	struct tegra_soctherm *ts = dev_id;
836 	struct thermal_zone_device *tz;
837 	u32 st, ex = 0, cp = 0, gp = 0, pl = 0, me = 0;
838 
839 	st = readl(ts->regs + THERMCTL_INTR_STATUS);
840 
841 	/* deliberately clear expected interrupts handled in SW */
842 	cp |= st & TH_INTR_CD0_MASK;
843 	cp |= st & TH_INTR_CU0_MASK;
844 
845 	gp |= st & TH_INTR_GD0_MASK;
846 	gp |= st & TH_INTR_GU0_MASK;
847 
848 	pl |= st & TH_INTR_PD0_MASK;
849 	pl |= st & TH_INTR_PU0_MASK;
850 
851 	me |= st & TH_INTR_MD0_MASK;
852 	me |= st & TH_INTR_MU0_MASK;
853 
854 	ex |= cp | gp | pl | me;
855 	if (ex) {
856 		writel(ex, ts->regs + THERMCTL_INTR_STATUS);
857 		st &= ~ex;
858 
859 		if (cp) {
860 			tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_CPU];
861 			thermal_zone_device_update(tz,
862 						   THERMAL_EVENT_UNSPECIFIED);
863 		}
864 
865 		if (gp) {
866 			tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_GPU];
867 			thermal_zone_device_update(tz,
868 						   THERMAL_EVENT_UNSPECIFIED);
869 		}
870 
871 		if (pl) {
872 			tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_PLLX];
873 			thermal_zone_device_update(tz,
874 						   THERMAL_EVENT_UNSPECIFIED);
875 		}
876 
877 		if (me) {
878 			tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_MEM];
879 			thermal_zone_device_update(tz,
880 						   THERMAL_EVENT_UNSPECIFIED);
881 		}
882 	}
883 
884 	/* deliberately ignore expected interrupts NOT handled in SW */
885 	ex |= TH_INTR_IGNORE_MASK;
886 	st &= ~ex;
887 
888 	if (st) {
889 		/* Whine about any other unexpected INTR bits still set */
890 		pr_err("soctherm: Ignored unexpected INTRs 0x%08x\n", st);
891 		writel(st, ts->regs + THERMCTL_INTR_STATUS);
892 	}
893 
894 	return IRQ_HANDLED;
895 }
896 
897 /**
898  * soctherm_oc_intr_enable() - Enables the soctherm over-current interrupt
899  * @ts:		pointer to a struct tegra_soctherm
900  * @alarm:		The soctherm throttle id
901  * @enable:		Flag indicating enable the soctherm over-current
902  *			interrupt or disable it
903  *
904  * Enables a specific over-current pins @alarm to raise an interrupt if the flag
905  * is set and the alarm corresponds to OC1, OC2, OC3, or OC4.
906  */
soctherm_oc_intr_enable(struct tegra_soctherm * ts,enum soctherm_throttle_id alarm,bool enable)907 static void soctherm_oc_intr_enable(struct tegra_soctherm *ts,
908 				    enum soctherm_throttle_id alarm,
909 				    bool enable)
910 {
911 	u32 r;
912 
913 	if (!enable)
914 		return;
915 
916 	r = readl(ts->regs + OC_INTR_ENABLE);
917 	switch (alarm) {
918 	case THROTTLE_OC1:
919 		r = REG_SET_MASK(r, OC_INTR_OC1_MASK, 1);
920 		break;
921 	case THROTTLE_OC2:
922 		r = REG_SET_MASK(r, OC_INTR_OC2_MASK, 1);
923 		break;
924 	case THROTTLE_OC3:
925 		r = REG_SET_MASK(r, OC_INTR_OC3_MASK, 1);
926 		break;
927 	case THROTTLE_OC4:
928 		r = REG_SET_MASK(r, OC_INTR_OC4_MASK, 1);
929 		break;
930 	default:
931 		r = 0;
932 		break;
933 	}
934 	writel(r, ts->regs + OC_INTR_ENABLE);
935 }
936 
937 /**
938  * soctherm_handle_alarm() - Handles soctherm alarms
939  * @alarm:		The soctherm throttle id
940  *
941  * "Handles" over-current alarms (OC1, OC2, OC3, and OC4) by printing
942  * a warning or informative message.
943  *
944  * Return: -EINVAL for @alarm = THROTTLE_OC3, otherwise 0 (success).
945  */
soctherm_handle_alarm(enum soctherm_throttle_id alarm)946 static int soctherm_handle_alarm(enum soctherm_throttle_id alarm)
947 {
948 	int rv = -EINVAL;
949 
950 	switch (alarm) {
951 	case THROTTLE_OC1:
952 		pr_debug("soctherm: Successfully handled OC1 alarm\n");
953 		rv = 0;
954 		break;
955 
956 	case THROTTLE_OC2:
957 		pr_debug("soctherm: Successfully handled OC2 alarm\n");
958 		rv = 0;
959 		break;
960 
961 	case THROTTLE_OC3:
962 		pr_debug("soctherm: Successfully handled OC3 alarm\n");
963 		rv = 0;
964 		break;
965 
966 	case THROTTLE_OC4:
967 		pr_debug("soctherm: Successfully handled OC4 alarm\n");
968 		rv = 0;
969 		break;
970 
971 	default:
972 		break;
973 	}
974 
975 	if (rv)
976 		pr_err("soctherm: ERROR in handling %s alarm\n",
977 		       throt_names[alarm]);
978 
979 	return rv;
980 }
981 
982 /**
983  * soctherm_edp_isr_thread() - log an over-current interrupt request
984  * @irq:	OC irq number. Currently not being used. See description
985  * @arg:	a void pointer for callback, currently not being used
986  *
987  * Over-current events are handled in hardware. This function is called to log
988  * and handle any OC events that happened. Additionally, it checks every
989  * over-current interrupt registers for registers are set but
990  * was not expected (i.e. any discrepancy in interrupt status) by the function,
991  * the discrepancy will logged.
992  *
993  * Return: %IRQ_HANDLED
994  */
soctherm_edp_isr_thread(int irq,void * arg)995 static irqreturn_t soctherm_edp_isr_thread(int irq, void *arg)
996 {
997 	struct tegra_soctherm *ts = arg;
998 	u32 st, ex, oc1, oc2, oc3, oc4;
999 
1000 	st = readl(ts->regs + OC_INTR_STATUS);
1001 
1002 	/* deliberately clear expected interrupts handled in SW */
1003 	oc1 = st & OC_INTR_OC1_MASK;
1004 	oc2 = st & OC_INTR_OC2_MASK;
1005 	oc3 = st & OC_INTR_OC3_MASK;
1006 	oc4 = st & OC_INTR_OC4_MASK;
1007 	ex = oc1 | oc2 | oc3 | oc4;
1008 
1009 	pr_err("soctherm: OC ALARM 0x%08x\n", ex);
1010 	if (ex) {
1011 		writel(st, ts->regs + OC_INTR_STATUS);
1012 		st &= ~ex;
1013 
1014 		if (oc1 && !soctherm_handle_alarm(THROTTLE_OC1))
1015 			soctherm_oc_intr_enable(ts, THROTTLE_OC1, true);
1016 
1017 		if (oc2 && !soctherm_handle_alarm(THROTTLE_OC2))
1018 			soctherm_oc_intr_enable(ts, THROTTLE_OC2, true);
1019 
1020 		if (oc3 && !soctherm_handle_alarm(THROTTLE_OC3))
1021 			soctherm_oc_intr_enable(ts, THROTTLE_OC3, true);
1022 
1023 		if (oc4 && !soctherm_handle_alarm(THROTTLE_OC4))
1024 			soctherm_oc_intr_enable(ts, THROTTLE_OC4, true);
1025 
1026 		if (oc1 && soc_irq_cdata.irq_enable & BIT(0))
1027 			handle_nested_irq(
1028 				irq_find_mapping(soc_irq_cdata.domain, 0));
1029 
1030 		if (oc2 && soc_irq_cdata.irq_enable & BIT(1))
1031 			handle_nested_irq(
1032 				irq_find_mapping(soc_irq_cdata.domain, 1));
1033 
1034 		if (oc3 && soc_irq_cdata.irq_enable & BIT(2))
1035 			handle_nested_irq(
1036 				irq_find_mapping(soc_irq_cdata.domain, 2));
1037 
1038 		if (oc4 && soc_irq_cdata.irq_enable & BIT(3))
1039 			handle_nested_irq(
1040 				irq_find_mapping(soc_irq_cdata.domain, 3));
1041 	}
1042 
1043 	if (st) {
1044 		pr_err("soctherm: Ignored unexpected OC ALARM 0x%08x\n", st);
1045 		writel(st, ts->regs + OC_INTR_STATUS);
1046 	}
1047 
1048 	return IRQ_HANDLED;
1049 }
1050 
1051 /**
1052  * soctherm_edp_isr() - Disables any active interrupts
1053  * @irq:	The interrupt request number
1054  * @arg:	Opaque pointer to an argument
1055  *
1056  * Writes to the OC_INTR_DISABLE register the over current interrupt status,
1057  * masking any asserted interrupts. Doing this prevents the same interrupts
1058  * from triggering this isr repeatedly. The thread woken by this isr will
1059  * handle asserted interrupts and subsequently unmask/re-enable them.
1060  *
1061  * The OC_INTR_DISABLE register indicates which OC interrupts
1062  * have been disabled.
1063  *
1064  * Return: %IRQ_WAKE_THREAD, handler requests to wake the handler thread
1065  */
soctherm_edp_isr(int irq,void * arg)1066 static irqreturn_t soctherm_edp_isr(int irq, void *arg)
1067 {
1068 	struct tegra_soctherm *ts = arg;
1069 	u32 r;
1070 
1071 	if (!ts)
1072 		return IRQ_NONE;
1073 
1074 	r = readl(ts->regs + OC_INTR_STATUS);
1075 	writel(r, ts->regs + OC_INTR_DISABLE);
1076 
1077 	return IRQ_WAKE_THREAD;
1078 }
1079 
1080 /**
1081  * soctherm_oc_irq_lock() - locks the over-current interrupt request
1082  * @data:	Interrupt request data
1083  *
1084  * Looks up the chip data from @data and locks the mutex associated with
1085  * a particular over-current interrupt request.
1086  */
soctherm_oc_irq_lock(struct irq_data * data)1087 static void soctherm_oc_irq_lock(struct irq_data *data)
1088 {
1089 	struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
1090 
1091 	mutex_lock(&d->irq_lock);
1092 }
1093 
1094 /**
1095  * soctherm_oc_irq_sync_unlock() - Unlocks the OC interrupt request
1096  * @data:		Interrupt request data
1097  *
1098  * Looks up the interrupt request data @data and unlocks the mutex associated
1099  * with a particular over-current interrupt request.
1100  */
soctherm_oc_irq_sync_unlock(struct irq_data * data)1101 static void soctherm_oc_irq_sync_unlock(struct irq_data *data)
1102 {
1103 	struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
1104 
1105 	mutex_unlock(&d->irq_lock);
1106 }
1107 
1108 /**
1109  * soctherm_oc_irq_enable() - Enables the SOC_THERM over-current interrupt queue
1110  * @data:       irq_data structure of the chip
1111  *
1112  * Sets the irq_enable bit of SOC_THERM allowing SOC_THERM
1113  * to respond to over-current interrupts.
1114  *
1115  */
soctherm_oc_irq_enable(struct irq_data * data)1116 static void soctherm_oc_irq_enable(struct irq_data *data)
1117 {
1118 	struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
1119 
1120 	d->irq_enable |= BIT(data->hwirq);
1121 }
1122 
1123 /**
1124  * soctherm_oc_irq_disable() - Disables overcurrent interrupt requests
1125  * @data:	The interrupt request information
1126  *
1127  * Clears the interrupt request enable bit of the overcurrent
1128  * interrupt request chip data.
1129  *
1130  * Return: Nothing is returned (void)
1131  */
soctherm_oc_irq_disable(struct irq_data * data)1132 static void soctherm_oc_irq_disable(struct irq_data *data)
1133 {
1134 	struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
1135 
1136 	d->irq_enable &= ~BIT(data->hwirq);
1137 }
1138 
soctherm_oc_irq_set_type(struct irq_data * data,unsigned int type)1139 static int soctherm_oc_irq_set_type(struct irq_data *data, unsigned int type)
1140 {
1141 	return 0;
1142 }
1143 
1144 /**
1145  * soctherm_oc_irq_map() - SOC_THERM interrupt request domain mapper
1146  * @h:		Interrupt request domain
1147  * @virq:	Virtual interrupt request number
1148  * @hw:		Hardware interrupt request number
1149  *
1150  * Mapping callback function for SOC_THERM's irq_domain. When a SOC_THERM
1151  * interrupt request is called, the irq_domain takes the request's virtual
1152  * request number (much like a virtual memory address) and maps it to a
1153  * physical hardware request number.
1154  *
1155  * When a mapping doesn't already exist for a virtual request number, the
1156  * irq_domain calls this function to associate the virtual request number with
1157  * a hardware request number.
1158  *
1159  * Return: 0
1160  */
soctherm_oc_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)1161 static int soctherm_oc_irq_map(struct irq_domain *h, unsigned int virq,
1162 		irq_hw_number_t hw)
1163 {
1164 	struct soctherm_oc_irq_chip_data *data = h->host_data;
1165 
1166 	irq_set_chip_data(virq, data);
1167 	irq_set_chip(virq, &data->irq_chip);
1168 	irq_set_nested_thread(virq, 1);
1169 	return 0;
1170 }
1171 
1172 /**
1173  * soctherm_irq_domain_xlate_twocell() - xlate for soctherm interrupts
1174  * @d:      Interrupt request domain
1175  * @ctrlr:      Controller device tree node
1176  * @intspec:    Array of u32s from DTs "interrupt" property
1177  * @intsize:    Number of values inside the intspec array
1178  * @out_hwirq:  HW IRQ value associated with this interrupt
1179  * @out_type:   The IRQ SENSE type for this interrupt.
1180  *
1181  * This Device Tree IRQ specifier translation function will translate a
1182  * specific "interrupt" as defined by 2 DT values where the cell values map
1183  * the hwirq number + 1 and linux irq flags. Since the output is the hwirq
1184  * number, this function will subtract 1 from the value listed in DT.
1185  *
1186  * Return: 0
1187  */
soctherm_irq_domain_xlate_twocell(struct irq_domain * d,struct device_node * ctrlr,const u32 * intspec,unsigned int intsize,irq_hw_number_t * out_hwirq,unsigned int * out_type)1188 static int soctherm_irq_domain_xlate_twocell(struct irq_domain *d,
1189 	struct device_node *ctrlr, const u32 *intspec, unsigned int intsize,
1190 	irq_hw_number_t *out_hwirq, unsigned int *out_type)
1191 {
1192 	if (WARN_ON(intsize < 2))
1193 		return -EINVAL;
1194 
1195 	/*
1196 	 * The HW value is 1 index less than the DT IRQ values.
1197 	 * i.e. OC4 goes to HW index 3.
1198 	 */
1199 	*out_hwirq = intspec[0] - 1;
1200 	*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
1201 	return 0;
1202 }
1203 
1204 static const struct irq_domain_ops soctherm_oc_domain_ops = {
1205 	.map	= soctherm_oc_irq_map,
1206 	.xlate	= soctherm_irq_domain_xlate_twocell,
1207 };
1208 
1209 /**
1210  * soctherm_oc_int_init() - Initial enabling of the over
1211  * current interrupts
1212  * @np:	The devicetree node for soctherm
1213  * @num_irqs:	The number of new interrupt requests
1214  *
1215  * Sets the over current interrupt request chip data
1216  *
1217  * Return: 0 on success or if overcurrent interrupts are not enabled,
1218  * -ENOMEM (out of memory), or irq_base if the function failed to
1219  * allocate the irqs
1220  */
soctherm_oc_int_init(struct device_node * np,int num_irqs)1221 static int soctherm_oc_int_init(struct device_node *np, int num_irqs)
1222 {
1223 	if (!num_irqs) {
1224 		pr_info("%s(): OC interrupts are not enabled\n", __func__);
1225 		return 0;
1226 	}
1227 
1228 	mutex_init(&soc_irq_cdata.irq_lock);
1229 	soc_irq_cdata.irq_enable = 0;
1230 
1231 	soc_irq_cdata.irq_chip.name = "soc_therm_oc";
1232 	soc_irq_cdata.irq_chip.irq_bus_lock = soctherm_oc_irq_lock;
1233 	soc_irq_cdata.irq_chip.irq_bus_sync_unlock =
1234 		soctherm_oc_irq_sync_unlock;
1235 	soc_irq_cdata.irq_chip.irq_disable = soctherm_oc_irq_disable;
1236 	soc_irq_cdata.irq_chip.irq_enable = soctherm_oc_irq_enable;
1237 	soc_irq_cdata.irq_chip.irq_set_type = soctherm_oc_irq_set_type;
1238 	soc_irq_cdata.irq_chip.irq_set_wake = NULL;
1239 
1240 	soc_irq_cdata.domain = irq_domain_add_linear(np, num_irqs,
1241 						     &soctherm_oc_domain_ops,
1242 						     &soc_irq_cdata);
1243 
1244 	if (!soc_irq_cdata.domain) {
1245 		pr_err("%s: Failed to create IRQ domain\n", __func__);
1246 		return -ENOMEM;
1247 	}
1248 
1249 	pr_debug("%s(): OC interrupts enabled successful\n", __func__);
1250 	return 0;
1251 }
1252 
1253 #ifdef CONFIG_DEBUG_FS
regs_show(struct seq_file * s,void * data)1254 static int regs_show(struct seq_file *s, void *data)
1255 {
1256 	struct platform_device *pdev = s->private;
1257 	struct tegra_soctherm *ts = platform_get_drvdata(pdev);
1258 	const struct tegra_tsensor *tsensors = ts->soc->tsensors;
1259 	const struct tegra_tsensor_group **ttgs = ts->soc->ttgs;
1260 	u32 r, state;
1261 	int i, level;
1262 
1263 	seq_puts(s, "-----TSENSE (convert HW)-----\n");
1264 
1265 	for (i = 0; i < ts->soc->num_tsensors; i++) {
1266 		r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG1);
1267 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TEMP_ENABLE);
1268 
1269 		seq_printf(s, "%s: ", tsensors[i].name);
1270 		seq_printf(s, "En(%d) ", state);
1271 
1272 		if (!state) {
1273 			seq_puts(s, "\n");
1274 			continue;
1275 		}
1276 
1277 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TIDDQ_EN_MASK);
1278 		seq_printf(s, "tiddq(%d) ", state);
1279 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TEN_COUNT_MASK);
1280 		seq_printf(s, "ten_count(%d) ", state);
1281 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TSAMPLE_MASK);
1282 		seq_printf(s, "tsample(%d) ", state + 1);
1283 
1284 		r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS1);
1285 		state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_VALID_MASK);
1286 		seq_printf(s, "Temp(%d/", state);
1287 		state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_MASK);
1288 		seq_printf(s, "%d) ", translate_temp(state));
1289 
1290 		r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS0);
1291 		state = REG_GET_MASK(r, SENSOR_STATUS0_VALID_MASK);
1292 		seq_printf(s, "Capture(%d/", state);
1293 		state = REG_GET_MASK(r, SENSOR_STATUS0_CAPTURE_MASK);
1294 		seq_printf(s, "%d) ", state);
1295 
1296 		r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG0);
1297 		state = REG_GET_MASK(r, SENSOR_CONFIG0_STOP);
1298 		seq_printf(s, "Stop(%d) ", state);
1299 		state = REG_GET_MASK(r, SENSOR_CONFIG0_TALL_MASK);
1300 		seq_printf(s, "Tall(%d) ", state);
1301 		state = REG_GET_MASK(r, SENSOR_CONFIG0_TCALC_OVER);
1302 		seq_printf(s, "Over(%d/", state);
1303 		state = REG_GET_MASK(r, SENSOR_CONFIG0_OVER);
1304 		seq_printf(s, "%d/", state);
1305 		state = REG_GET_MASK(r, SENSOR_CONFIG0_CPTR_OVER);
1306 		seq_printf(s, "%d) ", state);
1307 
1308 		r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG2);
1309 		state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMA_MASK);
1310 		seq_printf(s, "Therm_A/B(%d/", state);
1311 		state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMB_MASK);
1312 		seq_printf(s, "%d)\n", (s16)state);
1313 	}
1314 
1315 	r = readl(ts->regs + SENSOR_PDIV);
1316 	seq_printf(s, "PDIV: 0x%x\n", r);
1317 
1318 	r = readl(ts->regs + SENSOR_HOTSPOT_OFF);
1319 	seq_printf(s, "HOTSPOT: 0x%x\n", r);
1320 
1321 	seq_puts(s, "\n");
1322 	seq_puts(s, "-----SOC_THERM-----\n");
1323 
1324 	r = readl(ts->regs + SENSOR_TEMP1);
1325 	state = REG_GET_MASK(r, SENSOR_TEMP1_CPU_TEMP_MASK);
1326 	seq_printf(s, "Temperatures: CPU(%d) ", translate_temp(state));
1327 	state = REG_GET_MASK(r, SENSOR_TEMP1_GPU_TEMP_MASK);
1328 	seq_printf(s, " GPU(%d) ", translate_temp(state));
1329 	r = readl(ts->regs + SENSOR_TEMP2);
1330 	state = REG_GET_MASK(r, SENSOR_TEMP2_PLLX_TEMP_MASK);
1331 	seq_printf(s, " PLLX(%d) ", translate_temp(state));
1332 	state = REG_GET_MASK(r, SENSOR_TEMP2_MEM_TEMP_MASK);
1333 	seq_printf(s, " MEM(%d)\n", translate_temp(state));
1334 
1335 	for (i = 0; i < ts->soc->num_ttgs; i++) {
1336 		seq_printf(s, "%s:\n", ttgs[i]->name);
1337 		for (level = 0; level < 4; level++) {
1338 			s32 v;
1339 			u32 mask;
1340 			u16 off = ttgs[i]->thermctl_lvl0_offset;
1341 
1342 			r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
1343 
1344 			mask = ttgs[i]->thermctl_lvl0_up_thresh_mask;
1345 			state = REG_GET_MASK(r, mask);
1346 			v = sign_extend32(state, ts->soc->bptt - 1);
1347 			v *= ts->soc->thresh_grain;
1348 			seq_printf(s, "   %d: Up/Dn(%d /", level, v);
1349 
1350 			mask = ttgs[i]->thermctl_lvl0_dn_thresh_mask;
1351 			state = REG_GET_MASK(r, mask);
1352 			v = sign_extend32(state, ts->soc->bptt - 1);
1353 			v *= ts->soc->thresh_grain;
1354 			seq_printf(s, "%d ) ", v);
1355 
1356 			mask = THERMCTL_LVL0_CPU0_EN_MASK;
1357 			state = REG_GET_MASK(r, mask);
1358 			seq_printf(s, "En(%d) ", state);
1359 
1360 			mask = THERMCTL_LVL0_CPU0_CPU_THROT_MASK;
1361 			state = REG_GET_MASK(r, mask);
1362 			seq_puts(s, "CPU Throt");
1363 			if (!state)
1364 				seq_printf(s, "(%s) ", "none");
1365 			else if (state == THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT)
1366 				seq_printf(s, "(%s) ", "L");
1367 			else if (state == THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY)
1368 				seq_printf(s, "(%s) ", "H");
1369 			else
1370 				seq_printf(s, "(%s) ", "H+L");
1371 
1372 			mask = THERMCTL_LVL0_CPU0_GPU_THROT_MASK;
1373 			state = REG_GET_MASK(r, mask);
1374 			seq_puts(s, "GPU Throt");
1375 			if (!state)
1376 				seq_printf(s, "(%s) ", "none");
1377 			else if (state == THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT)
1378 				seq_printf(s, "(%s) ", "L");
1379 			else if (state == THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY)
1380 				seq_printf(s, "(%s) ", "H");
1381 			else
1382 				seq_printf(s, "(%s) ", "H+L");
1383 
1384 			mask = THERMCTL_LVL0_CPU0_STATUS_MASK;
1385 			state = REG_GET_MASK(r, mask);
1386 			seq_printf(s, "Status(%s)\n",
1387 				   state == 0 ? "LO" :
1388 				   state == 1 ? "In" :
1389 				   state == 2 ? "Res" : "HI");
1390 		}
1391 	}
1392 
1393 	r = readl(ts->regs + THERMCTL_STATS_CTL);
1394 	seq_printf(s, "STATS: Up(%s) Dn(%s)\n",
1395 		   r & STATS_CTL_EN_UP ? "En" : "--",
1396 		   r & STATS_CTL_EN_DN ? "En" : "--");
1397 
1398 	for (level = 0; level < 4; level++) {
1399 		u16 off;
1400 
1401 		off = THERMCTL_LVL0_UP_STATS;
1402 		r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
1403 		seq_printf(s, "  Level_%d Up(%d) ", level, r);
1404 
1405 		off = THERMCTL_LVL0_DN_STATS;
1406 		r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
1407 		seq_printf(s, "Dn(%d)\n", r);
1408 	}
1409 
1410 	r = readl(ts->regs + THERMCTL_THERMTRIP_CTL);
1411 	state = REG_GET_MASK(r, ttgs[0]->thermtrip_any_en_mask);
1412 	seq_printf(s, "Thermtrip Any En(%d)\n", state);
1413 	for (i = 0; i < ts->soc->num_ttgs; i++) {
1414 		state = REG_GET_MASK(r, ttgs[i]->thermtrip_enable_mask);
1415 		seq_printf(s, "     %s En(%d) ", ttgs[i]->name, state);
1416 		state = REG_GET_MASK(r, ttgs[i]->thermtrip_threshold_mask);
1417 		state *= ts->soc->thresh_grain;
1418 		seq_printf(s, "Thresh(%d)\n", state);
1419 	}
1420 
1421 	r = readl(ts->regs + THROT_GLOBAL_CFG);
1422 	seq_puts(s, "\n");
1423 	seq_printf(s, "GLOBAL THROTTLE CONFIG: 0x%08x\n", r);
1424 
1425 	seq_puts(s, "---------------------------------------------------\n");
1426 	r = readl(ts->regs + THROT_STATUS);
1427 	state = REG_GET_MASK(r, THROT_STATUS_BREACH_MASK);
1428 	seq_printf(s, "THROT STATUS: breach(%d) ", state);
1429 	state = REG_GET_MASK(r, THROT_STATUS_STATE_MASK);
1430 	seq_printf(s, "state(%d) ", state);
1431 	state = REG_GET_MASK(r, THROT_STATUS_ENABLED_MASK);
1432 	seq_printf(s, "enabled(%d)\n", state);
1433 
1434 	r = readl(ts->regs + CPU_PSKIP_STATUS);
1435 	if (ts->soc->use_ccroc) {
1436 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);
1437 		seq_printf(s, "CPU PSKIP STATUS: enabled(%d)\n", state);
1438 	} else {
1439 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_M_MASK);
1440 		seq_printf(s, "CPU PSKIP STATUS: M(%d) ", state);
1441 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_N_MASK);
1442 		seq_printf(s, "N(%d) ", state);
1443 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);
1444 		seq_printf(s, "enabled(%d)\n", state);
1445 	}
1446 
1447 	return 0;
1448 }
1449 
1450 DEFINE_SHOW_ATTRIBUTE(regs);
1451 
soctherm_debug_init(struct platform_device * pdev)1452 static void soctherm_debug_init(struct platform_device *pdev)
1453 {
1454 	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
1455 	struct dentry *root;
1456 
1457 	root = debugfs_create_dir("soctherm", NULL);
1458 
1459 	tegra->debugfs_dir = root;
1460 
1461 	debugfs_create_file("reg_contents", 0644, root, pdev, &regs_fops);
1462 }
1463 #else
soctherm_debug_init(struct platform_device * pdev)1464 static inline void soctherm_debug_init(struct platform_device *pdev) {}
1465 #endif
1466 
soctherm_clk_enable(struct platform_device * pdev,bool enable)1467 static int soctherm_clk_enable(struct platform_device *pdev, bool enable)
1468 {
1469 	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
1470 	int err;
1471 
1472 	if (!tegra->clock_soctherm || !tegra->clock_tsensor)
1473 		return -EINVAL;
1474 
1475 	reset_control_assert(tegra->reset);
1476 
1477 	if (enable) {
1478 		err = clk_prepare_enable(tegra->clock_soctherm);
1479 		if (err) {
1480 			reset_control_deassert(tegra->reset);
1481 			return err;
1482 		}
1483 
1484 		err = clk_prepare_enable(tegra->clock_tsensor);
1485 		if (err) {
1486 			clk_disable_unprepare(tegra->clock_soctherm);
1487 			reset_control_deassert(tegra->reset);
1488 			return err;
1489 		}
1490 	} else {
1491 		clk_disable_unprepare(tegra->clock_tsensor);
1492 		clk_disable_unprepare(tegra->clock_soctherm);
1493 	}
1494 
1495 	reset_control_deassert(tegra->reset);
1496 
1497 	return 0;
1498 }
1499 
throt_get_cdev_max_state(struct thermal_cooling_device * cdev,unsigned long * max_state)1500 static int throt_get_cdev_max_state(struct thermal_cooling_device *cdev,
1501 				    unsigned long *max_state)
1502 {
1503 	*max_state = 1;
1504 	return 0;
1505 }
1506 
throt_get_cdev_cur_state(struct thermal_cooling_device * cdev,unsigned long * cur_state)1507 static int throt_get_cdev_cur_state(struct thermal_cooling_device *cdev,
1508 				    unsigned long *cur_state)
1509 {
1510 	struct tegra_soctherm *ts = cdev->devdata;
1511 	u32 r;
1512 
1513 	r = readl(ts->regs + THROT_STATUS);
1514 	if (REG_GET_MASK(r, THROT_STATUS_STATE_MASK))
1515 		*cur_state = 1;
1516 	else
1517 		*cur_state = 0;
1518 
1519 	return 0;
1520 }
1521 
throt_set_cdev_state(struct thermal_cooling_device * cdev,unsigned long cur_state)1522 static int throt_set_cdev_state(struct thermal_cooling_device *cdev,
1523 				unsigned long cur_state)
1524 {
1525 	return 0;
1526 }
1527 
1528 static const struct thermal_cooling_device_ops throt_cooling_ops = {
1529 	.get_max_state = throt_get_cdev_max_state,
1530 	.get_cur_state = throt_get_cdev_cur_state,
1531 	.set_cur_state = throt_set_cdev_state,
1532 };
1533 
soctherm_thermtrips_parse(struct platform_device * pdev)1534 static int soctherm_thermtrips_parse(struct platform_device *pdev)
1535 {
1536 	struct device *dev = &pdev->dev;
1537 	struct tegra_soctherm *ts = dev_get_drvdata(dev);
1538 	struct tsensor_group_thermtrips *tt = ts->soc->thermtrips;
1539 	const int max_num_prop = ts->soc->num_ttgs * 2;
1540 	u32 *tlb;
1541 	int i, j, n, ret;
1542 
1543 	if (!tt)
1544 		return -ENOMEM;
1545 
1546 	n = of_property_count_u32_elems(dev->of_node, "nvidia,thermtrips");
1547 	if (n <= 0) {
1548 		dev_info(dev,
1549 			 "missing thermtrips, will use critical trips as shut down temp\n");
1550 		return n;
1551 	}
1552 
1553 	n = min(max_num_prop, n);
1554 
1555 	tlb = devm_kcalloc(&pdev->dev, max_num_prop, sizeof(u32), GFP_KERNEL);
1556 	if (!tlb)
1557 		return -ENOMEM;
1558 	ret = of_property_read_u32_array(dev->of_node, "nvidia,thermtrips",
1559 					 tlb, n);
1560 	if (ret) {
1561 		dev_err(dev, "invalid num ele: thermtrips:%d\n", ret);
1562 		return ret;
1563 	}
1564 
1565 	i = 0;
1566 	for (j = 0; j < n; j = j + 2) {
1567 		if (tlb[j] >= TEGRA124_SOCTHERM_SENSOR_NUM)
1568 			continue;
1569 
1570 		tt[i].id = tlb[j];
1571 		tt[i].temp = tlb[j + 1];
1572 		i++;
1573 	}
1574 
1575 	return 0;
1576 }
1577 
soctherm_oc_cfg_parse(struct device * dev,struct device_node * np_oc,struct soctherm_throt_cfg * stc)1578 static void soctherm_oc_cfg_parse(struct device *dev,
1579 				struct device_node *np_oc,
1580 				struct soctherm_throt_cfg *stc)
1581 {
1582 	u32 val;
1583 
1584 	if (of_property_read_bool(np_oc, "nvidia,polarity-active-low"))
1585 		stc->oc_cfg.active_low = 1;
1586 	else
1587 		stc->oc_cfg.active_low = 0;
1588 
1589 	if (!of_property_read_u32(np_oc, "nvidia,count-threshold", &val)) {
1590 		stc->oc_cfg.intr_en = 1;
1591 		stc->oc_cfg.alarm_cnt_thresh = val;
1592 	}
1593 
1594 	if (!of_property_read_u32(np_oc, "nvidia,throttle-period-us", &val))
1595 		stc->oc_cfg.throt_period = val;
1596 
1597 	if (!of_property_read_u32(np_oc, "nvidia,alarm-filter", &val))
1598 		stc->oc_cfg.alarm_filter = val;
1599 
1600 	/* BRIEF throttling by default, do not support STICKY */
1601 	stc->oc_cfg.mode = OC_THROTTLE_MODE_BRIEF;
1602 }
1603 
soctherm_throt_cfg_parse(struct device * dev,struct device_node * np,struct soctherm_throt_cfg * stc)1604 static int soctherm_throt_cfg_parse(struct device *dev,
1605 				    struct device_node *np,
1606 				    struct soctherm_throt_cfg *stc)
1607 {
1608 	struct tegra_soctherm *ts = dev_get_drvdata(dev);
1609 	int ret;
1610 	u32 val;
1611 
1612 	ret = of_property_read_u32(np, "nvidia,priority", &val);
1613 	if (ret) {
1614 		dev_err(dev, "throttle-cfg: %s: invalid priority\n", stc->name);
1615 		return -EINVAL;
1616 	}
1617 	stc->priority = val;
1618 
1619 	ret = of_property_read_u32(np, ts->soc->use_ccroc ?
1620 				   "nvidia,cpu-throt-level" :
1621 				   "nvidia,cpu-throt-percent", &val);
1622 	if (!ret) {
1623 		if (ts->soc->use_ccroc &&
1624 		    val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
1625 			stc->cpu_throt_level = val;
1626 		else if (!ts->soc->use_ccroc && val <= 100)
1627 			stc->cpu_throt_depth = val;
1628 		else
1629 			goto err;
1630 	} else {
1631 		goto err;
1632 	}
1633 
1634 	ret = of_property_read_u32(np, "nvidia,gpu-throt-level", &val);
1635 	if (!ret && val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
1636 		stc->gpu_throt_level = val;
1637 	else
1638 		goto err;
1639 
1640 	return 0;
1641 
1642 err:
1643 	dev_err(dev, "throttle-cfg: %s: no throt prop or invalid prop\n",
1644 		stc->name);
1645 	return -EINVAL;
1646 }
1647 
1648 /**
1649  * soctherm_init_hw_throt_cdev() - Parse the HW throttle configurations
1650  * and register them as cooling devices.
1651  * @pdev: Pointer to platform_device struct
1652  */
soctherm_init_hw_throt_cdev(struct platform_device * pdev)1653 static void soctherm_init_hw_throt_cdev(struct platform_device *pdev)
1654 {
1655 	struct device *dev = &pdev->dev;
1656 	struct tegra_soctherm *ts = dev_get_drvdata(dev);
1657 	struct device_node *np_stc, *np_stcc;
1658 	const char *name;
1659 	int i;
1660 
1661 	for (i = 0; i < THROTTLE_SIZE; i++) {
1662 		ts->throt_cfgs[i].name = throt_names[i];
1663 		ts->throt_cfgs[i].id = i;
1664 		ts->throt_cfgs[i].init = false;
1665 	}
1666 
1667 	np_stc = of_get_child_by_name(dev->of_node, "throttle-cfgs");
1668 	if (!np_stc) {
1669 		dev_info(dev,
1670 			 "throttle-cfg: no throttle-cfgs - not enabling\n");
1671 		return;
1672 	}
1673 
1674 	for_each_child_of_node(np_stc, np_stcc) {
1675 		struct soctherm_throt_cfg *stc;
1676 		struct thermal_cooling_device *tcd;
1677 		int err;
1678 
1679 		name = np_stcc->name;
1680 		stc = find_throttle_cfg_by_name(ts, name);
1681 		if (!stc) {
1682 			dev_err(dev,
1683 				"throttle-cfg: could not find %s\n", name);
1684 			continue;
1685 		}
1686 
1687 		if (stc->init) {
1688 			dev_err(dev, "throttle-cfg: %s: redefined!\n", name);
1689 			of_node_put(np_stcc);
1690 			break;
1691 		}
1692 
1693 		err = soctherm_throt_cfg_parse(dev, np_stcc, stc);
1694 		if (err)
1695 			continue;
1696 
1697 		if (stc->id >= THROTTLE_OC1) {
1698 			soctherm_oc_cfg_parse(dev, np_stcc, stc);
1699 			stc->init = true;
1700 		} else {
1701 
1702 			tcd = thermal_of_cooling_device_register(np_stcc,
1703 							 (char *)name, ts,
1704 							 &throt_cooling_ops);
1705 			if (IS_ERR_OR_NULL(tcd)) {
1706 				dev_err(dev,
1707 					"throttle-cfg: %s: failed to register cooling device\n",
1708 					name);
1709 				continue;
1710 			}
1711 			stc->cdev = tcd;
1712 			stc->init = true;
1713 		}
1714 
1715 	}
1716 
1717 	of_node_put(np_stc);
1718 }
1719 
1720 /**
1721  * throttlectl_cpu_level_cfg() - programs CCROC NV_THERM level config
1722  * @ts: pointer to a struct tegra_soctherm
1723  * @level: describing the level LOW/MED/HIGH of throttling
1724  *
1725  * It's necessary to set up the CPU-local CCROC NV_THERM instance with
1726  * the M/N values desired for each level. This function does this.
1727  *
1728  * This function pre-programs the CCROC NV_THERM levels in terms of
1729  * pre-configured "Low", "Medium" or "Heavy" throttle levels which are
1730  * mapped to THROT_LEVEL_LOW, THROT_LEVEL_MED and THROT_LEVEL_HVY.
1731  */
throttlectl_cpu_level_cfg(struct tegra_soctherm * ts,int level)1732 static void throttlectl_cpu_level_cfg(struct tegra_soctherm *ts, int level)
1733 {
1734 	u8 depth, dividend;
1735 	u32 r;
1736 
1737 	switch (level) {
1738 	case TEGRA_SOCTHERM_THROT_LEVEL_LOW:
1739 		depth = 50;
1740 		break;
1741 	case TEGRA_SOCTHERM_THROT_LEVEL_MED:
1742 		depth = 75;
1743 		break;
1744 	case TEGRA_SOCTHERM_THROT_LEVEL_HIGH:
1745 		depth = 80;
1746 		break;
1747 	case TEGRA_SOCTHERM_THROT_LEVEL_NONE:
1748 		return;
1749 	default:
1750 		return;
1751 	}
1752 
1753 	dividend = THROT_DEPTH_DIVIDEND(depth);
1754 
1755 	/* setup PSKIP in ccroc nv_therm registers */
1756 	r = ccroc_readl(ts, CCROC_THROT_PSKIP_RAMP_CPU_REG(level));
1757 	r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_DURATION_MASK, 0xff);
1758 	r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_STEP_MASK, 0xf);
1759 	ccroc_writel(ts, r, CCROC_THROT_PSKIP_RAMP_CPU_REG(level));
1760 
1761 	r = ccroc_readl(ts, CCROC_THROT_PSKIP_CTRL_CPU_REG(level));
1762 	r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_ENB_MASK, 1);
1763 	r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend);
1764 	r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff);
1765 	ccroc_writel(ts, r, CCROC_THROT_PSKIP_CTRL_CPU_REG(level));
1766 }
1767 
1768 /**
1769  * throttlectl_cpu_level_select() - program CPU pulse skipper config
1770  * @ts: pointer to a struct tegra_soctherm
1771  * @throt: the LIGHT/HEAVY of throttle event id
1772  *
1773  * Pulse skippers are used to throttle clock frequencies.  This
1774  * function programs the pulse skippers based on @throt and platform
1775  * data.  This function is used on SoCs which have CPU-local pulse
1776  * skipper control, such as T13x. It programs soctherm's interface to
1777  * Denver:CCROC NV_THERM in terms of Low, Medium and HIGH throttling
1778  * vectors. PSKIP_BYPASS mode is set as required per HW spec.
1779  */
throttlectl_cpu_level_select(struct tegra_soctherm * ts,enum soctherm_throttle_id throt)1780 static void throttlectl_cpu_level_select(struct tegra_soctherm *ts,
1781 					 enum soctherm_throttle_id throt)
1782 {
1783 	u32 r, throt_vect;
1784 
1785 	/* Denver:CCROC NV_THERM interface N:3 Mapping */
1786 	switch (ts->throt_cfgs[throt].cpu_throt_level) {
1787 	case TEGRA_SOCTHERM_THROT_LEVEL_LOW:
1788 		throt_vect = THROT_VECT_LOW;
1789 		break;
1790 	case TEGRA_SOCTHERM_THROT_LEVEL_MED:
1791 		throt_vect = THROT_VECT_MED;
1792 		break;
1793 	case TEGRA_SOCTHERM_THROT_LEVEL_HIGH:
1794 		throt_vect = THROT_VECT_HIGH;
1795 		break;
1796 	default:
1797 		throt_vect = THROT_VECT_NONE;
1798 		break;
1799 	}
1800 
1801 	r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
1802 	r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
1803 	r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_CPU_MASK, throt_vect);
1804 	r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT2_CPU_MASK, throt_vect);
1805 	writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
1806 
1807 	/* bypass sequencer in soc_therm as it is programmed in ccroc */
1808 	r = REG_SET_MASK(0, THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK, 1);
1809 	writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
1810 }
1811 
1812 /**
1813  * throttlectl_cpu_mn() - program CPU pulse skipper configuration
1814  * @ts: pointer to a struct tegra_soctherm
1815  * @throt: the LIGHT/HEAVY of throttle event id
1816  *
1817  * Pulse skippers are used to throttle clock frequencies.  This
1818  * function programs the pulse skippers based on @throt and platform
1819  * data.  This function is used for CPUs that have "remote" pulse
1820  * skipper control, e.g., the CPU pulse skipper is controlled by the
1821  * SOC_THERM IP block.  (SOC_THERM is located outside the CPU
1822  * complex.)
1823  */
throttlectl_cpu_mn(struct tegra_soctherm * ts,enum soctherm_throttle_id throt)1824 static void throttlectl_cpu_mn(struct tegra_soctherm *ts,
1825 			       enum soctherm_throttle_id throt)
1826 {
1827 	u32 r;
1828 	int depth;
1829 	u8 dividend;
1830 
1831 	depth = ts->throt_cfgs[throt].cpu_throt_depth;
1832 	dividend = THROT_DEPTH_DIVIDEND(depth);
1833 
1834 	r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
1835 	r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
1836 	r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend);
1837 	r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff);
1838 	writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
1839 
1840 	r = readl(ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
1841 	r = REG_SET_MASK(r, THROT_PSKIP_RAMP_DURATION_MASK, 0xff);
1842 	r = REG_SET_MASK(r, THROT_PSKIP_RAMP_STEP_MASK, 0xf);
1843 	writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
1844 }
1845 
1846 /**
1847  * throttlectl_gpu_level_select() - selects throttling level for GPU
1848  * @ts: pointer to a struct tegra_soctherm
1849  * @throt: the LIGHT/HEAVY of throttle event id
1850  *
1851  * This function programs soctherm's interface to GK20a NV_THERM to select
1852  * pre-configured "Low", "Medium" or "Heavy" throttle levels.
1853  *
1854  * Return: boolean true if HW was programmed
1855  */
throttlectl_gpu_level_select(struct tegra_soctherm * ts,enum soctherm_throttle_id throt)1856 static void throttlectl_gpu_level_select(struct tegra_soctherm *ts,
1857 					 enum soctherm_throttle_id throt)
1858 {
1859 	u32 r, level, throt_vect;
1860 
1861 	level = ts->throt_cfgs[throt].gpu_throt_level;
1862 	throt_vect = THROT_LEVEL_TO_DEPTH(level);
1863 	r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
1864 	r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
1865 	r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_GPU_MASK, throt_vect);
1866 	writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
1867 }
1868 
soctherm_oc_cfg_program(struct tegra_soctherm * ts,enum soctherm_throttle_id throt)1869 static int soctherm_oc_cfg_program(struct tegra_soctherm *ts,
1870 				      enum soctherm_throttle_id throt)
1871 {
1872 	u32 r;
1873 	struct soctherm_oc_cfg *oc = &ts->throt_cfgs[throt].oc_cfg;
1874 
1875 	if (oc->mode == OC_THROTTLE_MODE_DISABLED)
1876 		return -EINVAL;
1877 
1878 	r = REG_SET_MASK(0, OC1_CFG_HW_RESTORE_MASK, 1);
1879 	r = REG_SET_MASK(r, OC1_CFG_THROTTLE_MODE_MASK, oc->mode);
1880 	r = REG_SET_MASK(r, OC1_CFG_ALARM_POLARITY_MASK, oc->active_low);
1881 	r = REG_SET_MASK(r, OC1_CFG_EN_THROTTLE_MASK, 1);
1882 	writel(r, ts->regs + ALARM_CFG(throt));
1883 	writel(oc->throt_period, ts->regs + ALARM_THROTTLE_PERIOD(throt));
1884 	writel(oc->alarm_cnt_thresh, ts->regs + ALARM_CNT_THRESHOLD(throt));
1885 	writel(oc->alarm_filter, ts->regs + ALARM_FILTER(throt));
1886 	soctherm_oc_intr_enable(ts, throt, oc->intr_en);
1887 
1888 	return 0;
1889 }
1890 
1891 /**
1892  * soctherm_throttle_program() - programs pulse skippers' configuration
1893  * @ts: pointer to a struct tegra_soctherm
1894  * @throt: the LIGHT/HEAVY of the throttle event id.
1895  *
1896  * Pulse skippers are used to throttle clock frequencies.
1897  * This function programs the pulse skippers.
1898  */
soctherm_throttle_program(struct tegra_soctherm * ts,enum soctherm_throttle_id throt)1899 static void soctherm_throttle_program(struct tegra_soctherm *ts,
1900 				      enum soctherm_throttle_id throt)
1901 {
1902 	u32 r;
1903 	struct soctherm_throt_cfg stc = ts->throt_cfgs[throt];
1904 
1905 	if (!stc.init)
1906 		return;
1907 
1908 	if ((throt >= THROTTLE_OC1) && (soctherm_oc_cfg_program(ts, throt)))
1909 		return;
1910 
1911 	/* Setup PSKIP parameters */
1912 	if (ts->soc->use_ccroc)
1913 		throttlectl_cpu_level_select(ts, throt);
1914 	else
1915 		throttlectl_cpu_mn(ts, throt);
1916 
1917 	throttlectl_gpu_level_select(ts, throt);
1918 
1919 	r = REG_SET_MASK(0, THROT_PRIORITY_LITE_PRIO_MASK, stc.priority);
1920 	writel(r, ts->regs + THROT_PRIORITY_CTRL(throt));
1921 
1922 	r = REG_SET_MASK(0, THROT_DELAY_LITE_DELAY_MASK, 0);
1923 	writel(r, ts->regs + THROT_DELAY_CTRL(throt));
1924 
1925 	r = readl(ts->regs + THROT_PRIORITY_LOCK);
1926 	r = REG_GET_MASK(r, THROT_PRIORITY_LOCK_PRIORITY_MASK);
1927 	if (r >= stc.priority)
1928 		return;
1929 	r = REG_SET_MASK(0, THROT_PRIORITY_LOCK_PRIORITY_MASK,
1930 			 stc.priority);
1931 	writel(r, ts->regs + THROT_PRIORITY_LOCK);
1932 }
1933 
tegra_soctherm_throttle(struct device * dev)1934 static void tegra_soctherm_throttle(struct device *dev)
1935 {
1936 	struct tegra_soctherm *ts = dev_get_drvdata(dev);
1937 	u32 v;
1938 	int i;
1939 
1940 	/* configure LOW, MED and HIGH levels for CCROC NV_THERM */
1941 	if (ts->soc->use_ccroc) {
1942 		throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_LOW);
1943 		throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_MED);
1944 		throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_HIGH);
1945 	}
1946 
1947 	/* Thermal HW throttle programming */
1948 	for (i = 0; i < THROTTLE_SIZE; i++)
1949 		soctherm_throttle_program(ts, i);
1950 
1951 	v = REG_SET_MASK(0, THROT_GLOBAL_ENB_MASK, 1);
1952 	if (ts->soc->use_ccroc) {
1953 		ccroc_writel(ts, v, CCROC_GLOBAL_CFG);
1954 
1955 		v = ccroc_readl(ts, CCROC_SUPER_CCLKG_DIVIDER);
1956 		v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
1957 		ccroc_writel(ts, v, CCROC_SUPER_CCLKG_DIVIDER);
1958 	} else {
1959 		writel(v, ts->regs + THROT_GLOBAL_CFG);
1960 
1961 		v = readl(ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER);
1962 		v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
1963 		writel(v, ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER);
1964 	}
1965 
1966 	/* initialize stats collection */
1967 	v = STATS_CTL_CLR_DN | STATS_CTL_EN_DN |
1968 	    STATS_CTL_CLR_UP | STATS_CTL_EN_UP;
1969 	writel(v, ts->regs + THERMCTL_STATS_CTL);
1970 }
1971 
soctherm_interrupts_init(struct platform_device * pdev,struct tegra_soctherm * tegra)1972 static int soctherm_interrupts_init(struct platform_device *pdev,
1973 				    struct tegra_soctherm *tegra)
1974 {
1975 	struct device_node *np = pdev->dev.of_node;
1976 	int ret;
1977 
1978 	ret = soctherm_oc_int_init(np, TEGRA_SOC_OC_IRQ_MAX);
1979 	if (ret < 0) {
1980 		dev_err(&pdev->dev, "soctherm_oc_int_init failed\n");
1981 		return ret;
1982 	}
1983 
1984 	tegra->thermal_irq = platform_get_irq(pdev, 0);
1985 	if (tegra->thermal_irq < 0) {
1986 		dev_dbg(&pdev->dev, "get 'thermal_irq' failed.\n");
1987 		return 0;
1988 	}
1989 
1990 	tegra->edp_irq = platform_get_irq(pdev, 1);
1991 	if (tegra->edp_irq < 0) {
1992 		dev_dbg(&pdev->dev, "get 'edp_irq' failed.\n");
1993 		return 0;
1994 	}
1995 
1996 	ret = devm_request_threaded_irq(&pdev->dev,
1997 					tegra->thermal_irq,
1998 					soctherm_thermal_isr,
1999 					soctherm_thermal_isr_thread,
2000 					IRQF_ONESHOT,
2001 					dev_name(&pdev->dev),
2002 					tegra);
2003 	if (ret < 0) {
2004 		dev_err(&pdev->dev, "request_irq 'thermal_irq' failed.\n");
2005 		return ret;
2006 	}
2007 
2008 	ret = devm_request_threaded_irq(&pdev->dev,
2009 					tegra->edp_irq,
2010 					soctherm_edp_isr,
2011 					soctherm_edp_isr_thread,
2012 					IRQF_ONESHOT,
2013 					"soctherm_edp",
2014 					tegra);
2015 	if (ret < 0) {
2016 		dev_err(&pdev->dev, "request_irq 'edp_irq' failed.\n");
2017 		return ret;
2018 	}
2019 
2020 	return 0;
2021 }
2022 
soctherm_init(struct platform_device * pdev)2023 static void soctherm_init(struct platform_device *pdev)
2024 {
2025 	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
2026 	const struct tegra_tsensor_group **ttgs = tegra->soc->ttgs;
2027 	int i;
2028 	u32 pdiv, hotspot;
2029 
2030 	/* Initialize raw sensors */
2031 	for (i = 0; i < tegra->soc->num_tsensors; ++i)
2032 		enable_tsensor(tegra, i);
2033 
2034 	/* program pdiv and hotspot offsets per THERM */
2035 	pdiv = readl(tegra->regs + SENSOR_PDIV);
2036 	hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
2037 	for (i = 0; i < tegra->soc->num_ttgs; ++i) {
2038 		pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
2039 				    ttgs[i]->pdiv);
2040 		/* hotspot offset from PLLX, doesn't need to configure PLLX */
2041 		if (ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX)
2042 			continue;
2043 		hotspot =  REG_SET_MASK(hotspot,
2044 					ttgs[i]->pllx_hotspot_mask,
2045 					ttgs[i]->pllx_hotspot_diff);
2046 	}
2047 	writel(pdiv, tegra->regs + SENSOR_PDIV);
2048 	writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
2049 
2050 	/* Configure hw throttle */
2051 	tegra_soctherm_throttle(&pdev->dev);
2052 }
2053 
2054 static const struct of_device_id tegra_soctherm_of_match[] = {
2055 #ifdef CONFIG_ARCH_TEGRA_124_SOC
2056 	{
2057 		.compatible = "nvidia,tegra124-soctherm",
2058 		.data = &tegra124_soctherm,
2059 	},
2060 #endif
2061 #ifdef CONFIG_ARCH_TEGRA_132_SOC
2062 	{
2063 		.compatible = "nvidia,tegra132-soctherm",
2064 		.data = &tegra132_soctherm,
2065 	},
2066 #endif
2067 #ifdef CONFIG_ARCH_TEGRA_210_SOC
2068 	{
2069 		.compatible = "nvidia,tegra210-soctherm",
2070 		.data = &tegra210_soctherm,
2071 	},
2072 #endif
2073 	{ },
2074 };
2075 MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
2076 
tegra_soctherm_probe(struct platform_device * pdev)2077 static int tegra_soctherm_probe(struct platform_device *pdev)
2078 {
2079 	const struct of_device_id *match;
2080 	struct tegra_soctherm *tegra;
2081 	struct thermal_zone_device *z;
2082 	struct tsensor_shared_calib shared_calib;
2083 	struct tegra_soctherm_soc *soc;
2084 	unsigned int i;
2085 	int err;
2086 
2087 	match = of_match_node(tegra_soctherm_of_match, pdev->dev.of_node);
2088 	if (!match)
2089 		return -ENODEV;
2090 
2091 	soc = (struct tegra_soctherm_soc *)match->data;
2092 	if (soc->num_ttgs > TEGRA124_SOCTHERM_SENSOR_NUM)
2093 		return -EINVAL;
2094 
2095 	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
2096 	if (!tegra)
2097 		return -ENOMEM;
2098 
2099 	mutex_init(&tegra->thermctl_lock);
2100 	dev_set_drvdata(&pdev->dev, tegra);
2101 
2102 	tegra->soc = soc;
2103 
2104 	tegra->regs = devm_platform_ioremap_resource_byname(pdev, "soctherm-reg");
2105 	if (IS_ERR(tegra->regs)) {
2106 		dev_err(&pdev->dev, "can't get soctherm registers");
2107 		return PTR_ERR(tegra->regs);
2108 	}
2109 
2110 	if (!tegra->soc->use_ccroc) {
2111 		tegra->clk_regs = devm_platform_ioremap_resource_byname(pdev, "car-reg");
2112 		if (IS_ERR(tegra->clk_regs)) {
2113 			dev_err(&pdev->dev, "can't get car clk registers");
2114 			return PTR_ERR(tegra->clk_regs);
2115 		}
2116 	} else {
2117 		tegra->ccroc_regs = devm_platform_ioremap_resource_byname(pdev, "ccroc-reg");
2118 		if (IS_ERR(tegra->ccroc_regs)) {
2119 			dev_err(&pdev->dev, "can't get ccroc registers");
2120 			return PTR_ERR(tegra->ccroc_regs);
2121 		}
2122 	}
2123 
2124 	tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
2125 	if (IS_ERR(tegra->reset)) {
2126 		dev_err(&pdev->dev, "can't get soctherm reset\n");
2127 		return PTR_ERR(tegra->reset);
2128 	}
2129 
2130 	tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
2131 	if (IS_ERR(tegra->clock_tsensor)) {
2132 		dev_err(&pdev->dev, "can't get tsensor clock\n");
2133 		return PTR_ERR(tegra->clock_tsensor);
2134 	}
2135 
2136 	tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
2137 	if (IS_ERR(tegra->clock_soctherm)) {
2138 		dev_err(&pdev->dev, "can't get soctherm clock\n");
2139 		return PTR_ERR(tegra->clock_soctherm);
2140 	}
2141 
2142 	tegra->calib = devm_kcalloc(&pdev->dev,
2143 				    soc->num_tsensors, sizeof(u32),
2144 				    GFP_KERNEL);
2145 	if (!tegra->calib)
2146 		return -ENOMEM;
2147 
2148 	/* calculate shared calibration data */
2149 	err = tegra_calc_shared_calib(soc->tfuse, &shared_calib);
2150 	if (err)
2151 		return err;
2152 
2153 	/* calculate tsensor calibration data */
2154 	for (i = 0; i < soc->num_tsensors; ++i) {
2155 		err = tegra_calc_tsensor_calib(&soc->tsensors[i],
2156 					       &shared_calib,
2157 					       &tegra->calib[i]);
2158 		if (err)
2159 			return err;
2160 	}
2161 
2162 	tegra->thermctl_tzs = devm_kcalloc(&pdev->dev,
2163 					   soc->num_ttgs, sizeof(z),
2164 					   GFP_KERNEL);
2165 	if (!tegra->thermctl_tzs)
2166 		return -ENOMEM;
2167 
2168 	err = soctherm_clk_enable(pdev, true);
2169 	if (err)
2170 		return err;
2171 
2172 	soctherm_thermtrips_parse(pdev);
2173 
2174 	soctherm_init_hw_throt_cdev(pdev);
2175 
2176 	soctherm_init(pdev);
2177 
2178 	for (i = 0; i < soc->num_ttgs; ++i) {
2179 		struct tegra_thermctl_zone *zone =
2180 			devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
2181 		if (!zone) {
2182 			err = -ENOMEM;
2183 			goto disable_clocks;
2184 		}
2185 
2186 		zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset;
2187 		zone->dev = &pdev->dev;
2188 		zone->sg = soc->ttgs[i];
2189 		zone->ts = tegra;
2190 
2191 		z = devm_thermal_of_zone_register(&pdev->dev,
2192 						  soc->ttgs[i]->id, zone,
2193 						  &tegra_of_thermal_ops);
2194 		if (IS_ERR(z)) {
2195 			err = PTR_ERR(z);
2196 			dev_err(&pdev->dev, "failed to register sensor: %d\n",
2197 				err);
2198 			goto disable_clocks;
2199 		}
2200 
2201 		zone->tz = z;
2202 		tegra->thermctl_tzs[soc->ttgs[i]->id] = z;
2203 
2204 		/* Configure hw trip points */
2205 		err = tegra_soctherm_set_hwtrips(&pdev->dev, soc->ttgs[i], z);
2206 		if (err)
2207 			goto disable_clocks;
2208 	}
2209 
2210 	err = soctherm_interrupts_init(pdev, tegra);
2211 
2212 	soctherm_debug_init(pdev);
2213 
2214 	return 0;
2215 
2216 disable_clocks:
2217 	soctherm_clk_enable(pdev, false);
2218 
2219 	return err;
2220 }
2221 
tegra_soctherm_remove(struct platform_device * pdev)2222 static int tegra_soctherm_remove(struct platform_device *pdev)
2223 {
2224 	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
2225 
2226 	debugfs_remove_recursive(tegra->debugfs_dir);
2227 
2228 	soctherm_clk_enable(pdev, false);
2229 
2230 	return 0;
2231 }
2232 
soctherm_suspend(struct device * dev)2233 static int __maybe_unused soctherm_suspend(struct device *dev)
2234 {
2235 	struct platform_device *pdev = to_platform_device(dev);
2236 
2237 	soctherm_clk_enable(pdev, false);
2238 
2239 	return 0;
2240 }
2241 
soctherm_resume(struct device * dev)2242 static int __maybe_unused soctherm_resume(struct device *dev)
2243 {
2244 	struct platform_device *pdev = to_platform_device(dev);
2245 	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
2246 	struct tegra_soctherm_soc *soc = tegra->soc;
2247 	int err, i;
2248 
2249 	err = soctherm_clk_enable(pdev, true);
2250 	if (err) {
2251 		dev_err(&pdev->dev,
2252 			"Resume failed: enable clocks failed\n");
2253 		return err;
2254 	}
2255 
2256 	soctherm_init(pdev);
2257 
2258 	for (i = 0; i < soc->num_ttgs; ++i) {
2259 		struct thermal_zone_device *tz;
2260 
2261 		tz = tegra->thermctl_tzs[soc->ttgs[i]->id];
2262 		err = tegra_soctherm_set_hwtrips(dev, soc->ttgs[i], tz);
2263 		if (err) {
2264 			dev_err(&pdev->dev,
2265 				"Resume failed: set hwtrips failed\n");
2266 			return err;
2267 		}
2268 	}
2269 
2270 	return 0;
2271 }
2272 
2273 static SIMPLE_DEV_PM_OPS(tegra_soctherm_pm, soctherm_suspend, soctherm_resume);
2274 
2275 static struct platform_driver tegra_soctherm_driver = {
2276 	.probe = tegra_soctherm_probe,
2277 	.remove = tegra_soctherm_remove,
2278 	.driver = {
2279 		.name = "tegra_soctherm",
2280 		.pm = &tegra_soctherm_pm,
2281 		.of_match_table = tegra_soctherm_of_match,
2282 	},
2283 };
2284 module_platform_driver(tegra_soctherm_driver);
2285 
2286 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
2287 MODULE_DESCRIPTION("NVIDIA Tegra SOCTHERM thermal management driver");
2288 MODULE_LICENSE("GPL v2");
2289