152cd8451SLina IyerQCOM Idle States for cpuidle driver 252cd8451SLina Iyer 352cd8451SLina IyerARM provides idle-state node to define the cpuidle states, as defined in [1]. 452cd8451SLina Iyercpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle 552cd8451SLina Iyerstates. Idle states have different enter/exit latency and residency values. 652cd8451SLina IyerThe idle states supported by the QCOM SoC are defined as - 752cd8451SLina Iyer 852cd8451SLina Iyer * Standby 952cd8451SLina Iyer * Retention 1052cd8451SLina Iyer * Standalone Power Collapse (Standalone PC or SPC) 1152cd8451SLina Iyer * Power Collapse (PC) 1252cd8451SLina Iyer 1352cd8451SLina IyerStandby: Standby does a little more in addition to architectural clock gating. 1452cd8451SLina IyerWhen the WFI instruction is executed the ARM core would gate its internal 1552cd8451SLina Iyerclocks. In addition to gating the clocks, QCOM cpus use this instruction as a 1652cd8451SLina Iyertrigger to execute the SPM state machine. The SPM state machine waits for the 1752cd8451SLina Iyerinterrupt to trigger the core back in to active. This triggers the cache 1852cd8451SLina Iyerhierarchy to enter standby states, when all cpus are idle. An interrupt brings 1952cd8451SLina Iyerthe SPM state machine out of its wait, the next step is to ensure that the 2052cd8451SLina Iyercache hierarchy is also out of standby, and then the cpu is allowed to resume 2152cd8451SLina Iyerexecution. This state is defined as a generic ARM WFI state by the ARM cpuidle 2252cd8451SLina Iyerdriver and is not defined in the DT. The SPM state machine should be 2352cd8451SLina Iyerconfigured to execute this state by default and after executing every other 2452cd8451SLina Iyerstate below. 2552cd8451SLina Iyer 2652cd8451SLina IyerRetention: Retention is a low power state where the core is clock gated and 2752cd8451SLina Iyerthe memory and the registers associated with the core are retained. The 2852cd8451SLina Iyervoltage may be reduced to the minimum value needed to keep the processor 2952cd8451SLina Iyerregisters active. The SPM should be configured to execute the retention 3052cd8451SLina Iyersequence and would wait for interrupt, before restoring the cpu to execution 3152cd8451SLina Iyerstate. Retention may have a slightly higher latency than Standby. 3252cd8451SLina Iyer 3352cd8451SLina IyerStandalone PC: A cpu can power down and warmboot if there is a sufficient time 3452cd8451SLina Iyerbetween the time it enters idle and the next known wake up. SPC mode is used 3552cd8451SLina Iyerto indicate a core entering a power down state without consulting any other 3652cd8451SLina Iyercpu or the system resources. This helps save power only on that core. The SPM 3752cd8451SLina Iyersequence for this idle state is programmed to power down the supply to the 3852cd8451SLina Iyercore, wait for the interrupt, restore power to the core, and ensure the 3952cd8451SLina Iyersystem state including cache hierarchy is ready before allowing core to 4052cd8451SLina Iyerresume. Applying power and resetting the core causes the core to warmboot 4152cd8451SLina Iyerback into Elevation Level (EL) which trampolines the control back to the 4252cd8451SLina Iyerkernel. Entering a power down state for the cpu, needs to be done by trapping 4352cd8451SLina Iyerinto a EL. Failing to do so, would result in a crash enforced by the warm boot 4452cd8451SLina Iyercode in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to 4552cd8451SLina Iyerbe flushed in s/w, before powering down the core. 4652cd8451SLina Iyer 4752cd8451SLina IyerPower Collapse: This state is similar to the SPC mode, but distinguishes 4852cd8451SLina Iyeritself in that the cpu acknowledges and permits the SoC to enter deeper sleep 4952cd8451SLina Iyermodes. In a hierarchical power domain SoC, this means L2 and other caches can 5052cd8451SLina Iyerbe flushed, system bus, clocks - lowered, and SoC main XO clock gated and 5152cd8451SLina Iyervoltages reduced, provided all cpus enter this state. Since the span of low 5252cd8451SLina Iyerpower modes possible at this state is vast, the exit latency and the residency 5352cd8451SLina Iyerof this low power mode would be considered high even though at a cpu level, 5452cd8451SLina Iyerthis essentially is cpu power down. The SPM in this state also may handshake 5552cd8451SLina Iyerwith the Resource power manager (RPM) processor in the SoC to indicate a 5652cd8451SLina Iyercomplete application processor subsystem shut down. 5752cd8451SLina Iyer 5852cd8451SLina IyerThe idle-state for QCOM SoCs are distinguished by the compatible property of 5952cd8451SLina Iyerthe idle-states device node. 6052cd8451SLina Iyer 6152cd8451SLina IyerThe devicetree representation of the idle state should be - 6252cd8451SLina Iyer 6352cd8451SLina IyerRequired properties: 6452cd8451SLina Iyer 6552cd8451SLina Iyer- compatible: Must be one of - 6652cd8451SLina Iyer "qcom,idle-state-ret", 6752cd8451SLina Iyer "qcom,idle-state-spc", 6852cd8451SLina Iyer "qcom,idle-state-pc", 6952cd8451SLina Iyer and "arm,idle-state". 7052cd8451SLina Iyer 7152cd8451SLina IyerOther required and optional properties are specified in [1]. 7252cd8451SLina Iyer 7352cd8451SLina IyerExample: 7452cd8451SLina Iyer 7552cd8451SLina Iyer idle-states { 7652cd8451SLina Iyer CPU_SPC: spc { 7752cd8451SLina Iyer compatible = "qcom,idle-state-spc", "arm,idle-state"; 7852cd8451SLina Iyer entry-latency-us = <150>; 7952cd8451SLina Iyer exit-latency-us = <200>; 8052cd8451SLina Iyer min-residency-us = <2000>; 8152cd8451SLina Iyer }; 8252cd8451SLina Iyer }; 8352cd8451SLina Iyer 84*1bd524f7SAnup Patel[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml 85