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Searched full:serirq (Results 1 – 25 of 25) sorted by relevance

/openbmc/qemu/hw/ppc/
H A Dpnv_lpc.c424 /* Program the POWER9 LPC irq to PSI serirq routing table */
433 "OPB: setting serirq routing on POWER8 system, ignoring.\n"); in pnv_lpc_eval_serirq_routes()
439 * Each of the ISA irqs is routed to one of the 4 SERIRQ irqs with 2 in pnv_lpc_eval_serirq_routes()
443 int serirq = extract32(lpc->opb_irq_route1, in pnv_lpc_eval_serirq_routes() local
445 lpc->irq_to_serirq_route[irq] = serirq; in pnv_lpc_eval_serirq_routes()
449 int serirq = extract32(lpc->opb_irq_route0, in pnv_lpc_eval_serirq_routes() local
451 lpc->irq_to_serirq_route[irq] = serirq; in pnv_lpc_eval_serirq_routes()
492 * send LPC irqs to 4 output lines that raise the PSI SERIRQ irqs. in pnv_lpc_eval_irqs()
736 object_property_set_bool(OBJECT(lpc), "psi-serirq", true, &error_abort); in pnv_lpc_power9_realize()
748 /* P9 LPC routes ISA irqs to 4 PSI SERIRQ lines */ in pnv_lpc_power9_realize()
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H A Dpnv.c791 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 0, irq); in pnv_chip_power9_isa_create()
793 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 1, irq); in pnv_chip_power9_isa_create()
795 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 2, irq); in pnv_chip_power9_isa_create()
797 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 3, irq); in pnv_chip_power9_isa_create()
811 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 0, irq); in pnv_chip_power10_isa_create()
813 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 1, irq); in pnv_chip_power10_isa_create()
815 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 2, irq); in pnv_chip_power10_isa_create()
817 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 3, irq); in pnv_chip_power10_isa_create()
/openbmc/u-boot/board/imgtec/malta/
H A Dmalta.c202 /* mux SERIRQ onto SERIRQ pin */ in pci_init_board()
207 /* enable SERIRQ - Linux currently depends upon this */ in pci_init_board()
/openbmc/qemu/include/hw/ppc/
H A Dpnv_lpc.h94 * drive PSI SERIRQ irqs, routing according to OPB routing registers.
101 /* P9 serirq lines and irq routing table */
/openbmc/linux/arch/mips/pci/
H A Dfixup-malta.c103 /* Mux SERIRQ to its pin */ in malta_piix_func0_fixup()
108 /* Enable SERIRQ */ in malta_piix_func0_fixup()
/openbmc/linux/drivers/char/ipmi/
H A Dkcs_bmc_aspeed.c36 * IRQxEy Assert SerIRQ x for LPC channel y (Deprecated, use IDyIRQX, IRQXEy)
37 * IDyIRQX Use the specified 4-bit SerIRQ for LPC channel y
38 * SELyIRQX SerIRQ polarity for LPC channel y (low: 0, high: 1)
39 * IRQXEy Assert the SerIRQ specified in IDyIRQX for LPC channel y
349 "SerIRQ configuration not supported on KCS channel %d\n", in aspeed_kcs_config_upstream_irq()
H A Dkcs_bmc_cdev_raw.c286 /* Always write status before data, we generate the SerIRQ by writing ODR */ in kcs_bmc_raw_write()
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnuvoton,npcm845-pinctrl.yaml87 mmcrst, clkout, serirq, scipme, smi, smb6, smb6b, smb6c,
110 mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, scipme, smi,
H A Dnuvoton,npcm7xx-pinctrl.txt86 "GPIO162/SERIRQ", "GPIO163/LCLK/ESPICLK", "GPIO164/LAD0/ESPI_IO0",
151 r2, r2err, r2md, sd1, sd1pwr, wdog1, wdog2, scipme, sci, serirq,
/openbmc/linux/arch/mips/include/asm/mips-boards/
H A Dpiix4.h17 /* SERIRQ Control */
/openbmc/linux/Documentation/devicetree/bindings/ipmi/
H A Daspeed,ast2400-kcs-bmc.yaml57 A 2-cell property expressing the LPC SerIRQ number and the interrupt
/openbmc/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-npcm750-pincfg-evb.dtsi67 pins = "GPIO162/SERIRQ";
H A Dnuvoton-common-npcm7xx.dtsi987 serirq_pins: serirq-pins {
988 groups = "serirq";
989 function = "serirq";
H A Dnuvoton-npcm730-gsj-gpio.dtsi357 pins = "GPIO162/SERIRQ";
/openbmc/linux/drivers/char/tpm/st33zp24/
H A Dst33zp24.c505 IRQF_TRIGGER_HIGH, "TPM SERIRQ management", in st33zp24_probe()
508 dev_err(&chip->dev, "TPM SERIRQ signals %d not available\n", in st33zp24_probe()
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-asrock-e3c246d4i.dts194 "CK_33M_BMC", "LFRAME", "SERIRQ", "S_PLTRST";
/openbmc/docs/designs/
H A Dbmc-service-failure-debug-and-recovery.md348 A SerIRQ is unnecessary for correct operation of the protocol. The BMC-side
362 The uni-directional writes and the lack of SerIRQ reduce the features required
/openbmc/u-boot/arch/x86/dts/
H A Dbaytrail_som-db5800-som-6867.dts68 /* SERIRQ */
/openbmc/linux/drivers/pinctrl/intel/
H A Dpinctrl-lewisburg.c35 PINCTRL_PIN(6, "SERIRQ"),
H A Dpinctrl-cannonlake.c53 PINCTRL_PIN(6, "SERIRQ"),
469 PINCTRL_PIN(6, "SERIRQ"),
/openbmc/linux/drivers/pinctrl/nuvoton/
H A Dpinctrl-npcm7xx.c618 NPCM7XX_GRP(serirq), \
761 NPCM7XX_SFUNC(serirq);
879 NPCM7XX_MKFUNC(serirq),
1098 …NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DSTR(8, 12…
1342 PINCTRL_PIN(162, "GPIO162/SERIRQ"),
H A Dpinctrl-npcm8xx.c798 NPCM8XX_GRP(serirq), \
1044 NPCM8XX_SFUNC(serirq);
1266 NPCM8XX_MKFUNC(serirq),
1499 …NPCM8XX_PINCFG(168, serirq, MFSEL1, 31, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NON…
1741 PINCTRL_PIN(162, "GPIO162/SERIRQ"),
/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Dpch.c105 /* Setup SERIRQ, enable continuous mode */ in pch_misc_init()
/openbmc/obmc-console/
H A Dconsole-server.c412 warn("Invalid LPC SERIRQ: '%s'", val); in tty_init_vuart()
/openbmc/linux/drivers/pinctrl/renesas/
H A Dpfc-sh7757.c1417 GPIO_FN(SERIRQ),