pinctrl: nuvoton: npcm8xx: modify pins flags

Modify the following pins flags on the Nuvoton NPCM8XX BMC:
- Add pins 110-113, 187, 191, 192, 194-199, 202 SLEW flag
- Add pins 229 and 230 GPO flag.
-

pinctrl: nuvoton: npcm8xx: modify pins flags

Modify the following pins flags on the Nuvoton NPCM8XX BMC:
- Add pins 110-113, 187, 191, 192, 194-199, 202 SLEW flag
- Add pins 229 and 230 GPO flag.
- Remove pin 233 SLEWLPC flag.
- Remove pin 251 SLEW flag.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://lore.kernel.org/r/20240812145816.3301570-8-tmaimon77@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

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pinctrl: nuvoton: npcm8xx: modify clkrun and serirq pin configuration

Modify clkrun and serirq pin configuration on the Nuvoton NPCM8XX BMC
SoC.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Li

pinctrl: nuvoton: npcm8xx: modify clkrun and serirq pin configuration

Modify clkrun and serirq pin configuration on the Nuvoton NPCM8XX BMC
SoC.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://lore.kernel.org/r/20240812145816.3301570-7-tmaimon77@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

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pinctrl: nuvoton: npcm8xx: add pin 250 to DDR pins group

Add pin 250 to DDR pins group on the Nuvoton NPCM8xx BMC SoC.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://lore.kernel.or

pinctrl: nuvoton: npcm8xx: add pin 250 to DDR pins group

Add pin 250 to DDR pins group on the Nuvoton NPCM8xx BMC SoC.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://lore.kernel.org/r/20240812145816.3301570-6-tmaimon77@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

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pinctrl: nuvoton: npcm8xx: add gpi35 and gpi36

This patch adds support for GPIO pins GPI35 and GPI36 on the Nuvoton
NPCM8xx BMC SoC.

The pins are configured for only for input.

Signed-off-by: Tome

pinctrl: nuvoton: npcm8xx: add gpi35 and gpi36

This patch adds support for GPIO pins GPI35 and GPI36 on the Nuvoton
NPCM8xx BMC SoC.

The pins are configured for only for input.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://lore.kernel.org/r/20240812145816.3301570-5-tmaimon77@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

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pinctrl: nuvoton: npcm8xx: clear polarity before set both edge

Clear polarity before setting both edges to ensure that the polarity is
in the same state before configuring events for both edges

Sig

pinctrl: nuvoton: npcm8xx: clear polarity before set both edge

Clear polarity before setting both edges to ensure that the polarity is
in the same state before configuring events for both edges

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://lore.kernel.org/r/20240812145816.3301570-4-tmaimon77@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

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pinctrl: nuvoton: npcm8xx: remove non-existent pins, groups, functions

Remove non-existent smb4den abd lpcclk pins, groups and functions on
the Nuvoton NPCM8XX BMC SoC.

Signed-off-by: Tomer Maimon

pinctrl: nuvoton: npcm8xx: remove non-existent pins, groups, functions

Remove non-existent smb4den abd lpcclk pins, groups and functions on
the Nuvoton NPCM8XX BMC SoC.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://lore.kernel.org/r/20240812145816.3301570-3-tmaimon77@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

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pinctrl: nuvoton: add NPCM8XX pinctrl and GPIO driver

Add pinctrl and GPIO controller driver support to Arbel BMC NPCM8XX SoC.

Arbel BMC NPCM8XX pinctrl driver based on Poleg NPCM7XX, except the
pi

pinctrl: nuvoton: add NPCM8XX pinctrl and GPIO driver

Add pinctrl and GPIO controller driver support to Arbel BMC NPCM8XX SoC.

Arbel BMC NPCM8XX pinctrl driver based on Poleg NPCM7XX, except the
pin mux mapping difference the NPCM8XX GPIO supports adjust debounce
period time.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://lore.kernel.org/r/20230828140849.21724-3-tmaimon77@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>

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