1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Intel Cannon Lake PCH pinctrl/GPIO driver
4  *
5  * Copyright (C) 2017, Intel Corporation
6  * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
8  */
9 
10 #include <linux/mod_devicetable.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 
14 #include <linux/pinctrl/pinctrl.h>
15 
16 #include "pinctrl-intel.h"
17 
18 #define CNL_LP_PAD_OWN		0x020
19 #define CNL_LP_PADCFGLOCK	0x080
20 #define CNL_LP_HOSTSW_OWN	0x0b0
21 #define CNL_LP_GPI_IS		0x100
22 #define CNL_LP_GPI_IE		0x120
23 
24 #define CNL_H_PAD_OWN		0x020
25 #define CNL_H_PADCFGLOCK	0x080
26 #define CNL_H_HOSTSW_OWN	0x0c0
27 #define CNL_H_GPI_IS		0x100
28 #define CNL_H_GPI_IE		0x120
29 
30 #define CNL_GPP(r, s, e, g)				\
31 	{						\
32 		.reg_num = (r),				\
33 		.base = (s),				\
34 		.size = ((e) - (s) + 1),		\
35 		.gpio_base = (g),			\
36 	}
37 
38 #define CNL_LP_COMMUNITY(b, s, e, g)			\
39 	INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_LP)
40 
41 #define CNL_H_COMMUNITY(b, s, e, g)			\
42 	INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_H)
43 
44 /* Cannon Lake-H */
45 static const struct pinctrl_pin_desc cnlh_pins[] = {
46 	/* GPP_A */
47 	PINCTRL_PIN(0, "RCINB"),
48 	PINCTRL_PIN(1, "LAD_0"),
49 	PINCTRL_PIN(2, "LAD_1"),
50 	PINCTRL_PIN(3, "LAD_2"),
51 	PINCTRL_PIN(4, "LAD_3"),
52 	PINCTRL_PIN(5, "LFRAMEB"),
53 	PINCTRL_PIN(6, "SERIRQ"),
54 	PINCTRL_PIN(7, "PIRQAB"),
55 	PINCTRL_PIN(8, "CLKRUNB"),
56 	PINCTRL_PIN(9, "CLKOUT_LPC_0"),
57 	PINCTRL_PIN(10, "CLKOUT_LPC_1"),
58 	PINCTRL_PIN(11, "PMEB"),
59 	PINCTRL_PIN(12, "BM_BUSYB"),
60 	PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
61 	PINCTRL_PIN(14, "SUS_STATB"),
62 	PINCTRL_PIN(15, "SUSACKB"),
63 	PINCTRL_PIN(16, "CLKOUT_48"),
64 	PINCTRL_PIN(17, "SD_VDD1_PWR_EN_B"),
65 	PINCTRL_PIN(18, "ISH_GP_0"),
66 	PINCTRL_PIN(19, "ISH_GP_1"),
67 	PINCTRL_PIN(20, "ISH_GP_2"),
68 	PINCTRL_PIN(21, "ISH_GP_3"),
69 	PINCTRL_PIN(22, "ISH_GP_4"),
70 	PINCTRL_PIN(23, "ISH_GP_5"),
71 	PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
72 	/* GPP_B */
73 	PINCTRL_PIN(25, "GSPI0_CS1B"),
74 	PINCTRL_PIN(26, "GSPI1_CS1B"),
75 	PINCTRL_PIN(27, "VRALERTB"),
76 	PINCTRL_PIN(28, "CPU_GP_2"),
77 	PINCTRL_PIN(29, "CPU_GP_3"),
78 	PINCTRL_PIN(30, "SRCCLKREQB_0"),
79 	PINCTRL_PIN(31, "SRCCLKREQB_1"),
80 	PINCTRL_PIN(32, "SRCCLKREQB_2"),
81 	PINCTRL_PIN(33, "SRCCLKREQB_3"),
82 	PINCTRL_PIN(34, "SRCCLKREQB_4"),
83 	PINCTRL_PIN(35, "SRCCLKREQB_5"),
84 	PINCTRL_PIN(36, "SSP_MCLK"),
85 	PINCTRL_PIN(37, "SLP_S0B"),
86 	PINCTRL_PIN(38, "PLTRSTB"),
87 	PINCTRL_PIN(39, "SPKR"),
88 	PINCTRL_PIN(40, "GSPI0_CS0B"),
89 	PINCTRL_PIN(41, "GSPI0_CLK"),
90 	PINCTRL_PIN(42, "GSPI0_MISO"),
91 	PINCTRL_PIN(43, "GSPI0_MOSI"),
92 	PINCTRL_PIN(44, "GSPI1_CS0B"),
93 	PINCTRL_PIN(45, "GSPI1_CLK"),
94 	PINCTRL_PIN(46, "GSPI1_MISO"),
95 	PINCTRL_PIN(47, "GSPI1_MOSI"),
96 	PINCTRL_PIN(48, "SML1ALERTB"),
97 	PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),
98 	PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"),
99 	/* GPP_C */
100 	PINCTRL_PIN(51, "SMBCLK"),
101 	PINCTRL_PIN(52, "SMBDATA"),
102 	PINCTRL_PIN(53, "SMBALERTB"),
103 	PINCTRL_PIN(54, "SML0CLK"),
104 	PINCTRL_PIN(55, "SML0DATA"),
105 	PINCTRL_PIN(56, "SML0ALERTB"),
106 	PINCTRL_PIN(57, "SML1CLK"),
107 	PINCTRL_PIN(58, "SML1DATA"),
108 	PINCTRL_PIN(59, "UART0_RXD"),
109 	PINCTRL_PIN(60, "UART0_TXD"),
110 	PINCTRL_PIN(61, "UART0_RTSB"),
111 	PINCTRL_PIN(62, "UART0_CTSB"),
112 	PINCTRL_PIN(63, "UART1_RXD"),
113 	PINCTRL_PIN(64, "UART1_TXD"),
114 	PINCTRL_PIN(65, "UART1_RTSB"),
115 	PINCTRL_PIN(66, "UART1_CTSB"),
116 	PINCTRL_PIN(67, "I2C0_SDA"),
117 	PINCTRL_PIN(68, "I2C0_SCL"),
118 	PINCTRL_PIN(69, "I2C1_SDA"),
119 	PINCTRL_PIN(70, "I2C1_SCL"),
120 	PINCTRL_PIN(71, "UART2_RXD"),
121 	PINCTRL_PIN(72, "UART2_TXD"),
122 	PINCTRL_PIN(73, "UART2_RTSB"),
123 	PINCTRL_PIN(74, "UART2_CTSB"),
124 	/* GPP_D */
125 	PINCTRL_PIN(75, "SPI1_CSB"),
126 	PINCTRL_PIN(76, "SPI1_CLK"),
127 	PINCTRL_PIN(77, "SPI1_MISO_IO_1"),
128 	PINCTRL_PIN(78, "SPI1_MOSI_IO_0"),
129 	PINCTRL_PIN(79, "ISH_I2C2_SDA"),
130 	PINCTRL_PIN(80, "SSP2_SFRM"),
131 	PINCTRL_PIN(81, "SSP2_TXD"),
132 	PINCTRL_PIN(82, "SSP2_RXD"),
133 	PINCTRL_PIN(83, "SSP2_SCLK"),
134 	PINCTRL_PIN(84, "ISH_SPI_CSB"),
135 	PINCTRL_PIN(85, "ISH_SPI_CLK"),
136 	PINCTRL_PIN(86, "ISH_SPI_MISO"),
137 	PINCTRL_PIN(87, "ISH_SPI_MOSI"),
138 	PINCTRL_PIN(88, "ISH_UART0_RXD"),
139 	PINCTRL_PIN(89, "ISH_UART0_TXD"),
140 	PINCTRL_PIN(90, "ISH_UART0_RTSB"),
141 	PINCTRL_PIN(91, "ISH_UART0_CTSB"),
142 	PINCTRL_PIN(92, "DMIC_CLK_1"),
143 	PINCTRL_PIN(93, "DMIC_DATA_1"),
144 	PINCTRL_PIN(94, "DMIC_CLK_0"),
145 	PINCTRL_PIN(95, "DMIC_DATA_0"),
146 	PINCTRL_PIN(96, "SPI1_IO_2"),
147 	PINCTRL_PIN(97, "SPI1_IO_3"),
148 	PINCTRL_PIN(98, "ISH_I2C2_SCL"),
149 	/* GPP_G */
150 	PINCTRL_PIN(99, "SD3_CMD"),
151 	PINCTRL_PIN(100, "SD3_D0"),
152 	PINCTRL_PIN(101, "SD3_D1"),
153 	PINCTRL_PIN(102, "SD3_D2"),
154 	PINCTRL_PIN(103, "SD3_D3"),
155 	PINCTRL_PIN(104, "SD3_CDB"),
156 	PINCTRL_PIN(105, "SD3_CLK"),
157 	PINCTRL_PIN(106, "SD3_WP"),
158 	/* AZA */
159 	PINCTRL_PIN(107, "HDA_BCLK"),
160 	PINCTRL_PIN(108, "HDA_RSTB"),
161 	PINCTRL_PIN(109, "HDA_SYNC"),
162 	PINCTRL_PIN(110, "HDA_SDO"),
163 	PINCTRL_PIN(111, "HDA_SDI_0"),
164 	PINCTRL_PIN(112, "HDA_SDI_1"),
165 	PINCTRL_PIN(113, "SSP1_SFRM"),
166 	PINCTRL_PIN(114, "SSP1_TXD"),
167 	/* vGPIO */
168 	PINCTRL_PIN(115, "CNV_BTEN"),
169 	PINCTRL_PIN(116, "CNV_GNEN"),
170 	PINCTRL_PIN(117, "CNV_WFEN"),
171 	PINCTRL_PIN(118, "CNV_WCEN"),
172 	PINCTRL_PIN(119, "CNV_BT_HOST_WAKEB"),
173 	PINCTRL_PIN(120, "vCNV_GNSS_HOST_WAKEB"),
174 	PINCTRL_PIN(121, "vSD3_CD_B"),
175 	PINCTRL_PIN(122, "CNV_BT_IF_SELECT"),
176 	PINCTRL_PIN(123, "vCNV_BT_UART_TXD"),
177 	PINCTRL_PIN(124, "vCNV_BT_UART_RXD"),
178 	PINCTRL_PIN(125, "vCNV_BT_UART_CTS_B"),
179 	PINCTRL_PIN(126, "vCNV_BT_UART_RTS_B"),
180 	PINCTRL_PIN(127, "vCNV_MFUART1_TXD"),
181 	PINCTRL_PIN(128, "vCNV_MFUART1_RXD"),
182 	PINCTRL_PIN(129, "vCNV_MFUART1_CTS_B"),
183 	PINCTRL_PIN(130, "vCNV_MFUART1_RTS_B"),
184 	PINCTRL_PIN(131, "vCNV_GNSS_UART_TXD"),
185 	PINCTRL_PIN(132, "vCNV_GNSS_UART_RXD"),
186 	PINCTRL_PIN(133, "vCNV_GNSS_UART_CTS_B"),
187 	PINCTRL_PIN(134, "vCNV_GNSS_UART_RTS_B"),
188 	PINCTRL_PIN(135, "vUART0_TXD"),
189 	PINCTRL_PIN(136, "vUART0_RXD"),
190 	PINCTRL_PIN(137, "vUART0_CTS_B"),
191 	PINCTRL_PIN(138, "vUART0_RTSB"),
192 	PINCTRL_PIN(139, "vISH_UART0_TXD"),
193 	PINCTRL_PIN(140, "vISH_UART0_RXD"),
194 	PINCTRL_PIN(141, "vISH_UART0_CTS_B"),
195 	PINCTRL_PIN(142, "vISH_UART0_RTSB"),
196 	PINCTRL_PIN(143, "vISH_UART1_TXD"),
197 	PINCTRL_PIN(144, "vISH_UART1_RXD"),
198 	PINCTRL_PIN(145, "vISH_UART1_CTS_B"),
199 	PINCTRL_PIN(146, "vISH_UART1_RTS_B"),
200 	PINCTRL_PIN(147, "vCNV_BT_I2S_BCLK"),
201 	PINCTRL_PIN(148, "vCNV_BT_I2S_WS_SYNC"),
202 	PINCTRL_PIN(149, "vCNV_BT_I2S_SDO"),
203 	PINCTRL_PIN(150, "vCNV_BT_I2S_SDI"),
204 	PINCTRL_PIN(151, "vSSP2_SCLK"),
205 	PINCTRL_PIN(152, "vSSP2_SFRM"),
206 	PINCTRL_PIN(153, "vSSP2_TXD"),
207 	PINCTRL_PIN(154, "vSSP2_RXD"),
208 	/* GPP_K */
209 	PINCTRL_PIN(155, "FAN_TACH_0"),
210 	PINCTRL_PIN(156, "FAN_TACH_1"),
211 	PINCTRL_PIN(157, "FAN_TACH_2"),
212 	PINCTRL_PIN(158, "FAN_TACH_3"),
213 	PINCTRL_PIN(159, "FAN_TACH_4"),
214 	PINCTRL_PIN(160, "FAN_TACH_5"),
215 	PINCTRL_PIN(161, "FAN_TACH_6"),
216 	PINCTRL_PIN(162, "FAN_TACH_7"),
217 	PINCTRL_PIN(163, "FAN_PWM_0"),
218 	PINCTRL_PIN(164, "FAN_PWM_1"),
219 	PINCTRL_PIN(165, "FAN_PWM_2"),
220 	PINCTRL_PIN(166, "FAN_PWM_3"),
221 	PINCTRL_PIN(167, "GSXDOUT"),
222 	PINCTRL_PIN(168, "GSXSLOAD"),
223 	PINCTRL_PIN(169, "GSXDIN"),
224 	PINCTRL_PIN(170, "GSXSRESETB"),
225 	PINCTRL_PIN(171, "GSXCLK"),
226 	PINCTRL_PIN(172, "ADR_COMPLETE"),
227 	PINCTRL_PIN(173, "NMIB"),
228 	PINCTRL_PIN(174, "SMIB"),
229 	PINCTRL_PIN(175, "CORE_VID_0"),
230 	PINCTRL_PIN(176, "CORE_VID_1"),
231 	PINCTRL_PIN(177, "IMGCLKOUT_0"),
232 	PINCTRL_PIN(178, "IMGCLKOUT_1"),
233 	/* GPP_H */
234 	PINCTRL_PIN(179, "SRCCLKREQB_6"),
235 	PINCTRL_PIN(180, "SRCCLKREQB_7"),
236 	PINCTRL_PIN(181, "SRCCLKREQB_8"),
237 	PINCTRL_PIN(182, "SRCCLKREQB_9"),
238 	PINCTRL_PIN(183, "SRCCLKREQB_10"),
239 	PINCTRL_PIN(184, "SRCCLKREQB_11"),
240 	PINCTRL_PIN(185, "SRCCLKREQB_12"),
241 	PINCTRL_PIN(186, "SRCCLKREQB_13"),
242 	PINCTRL_PIN(187, "SRCCLKREQB_14"),
243 	PINCTRL_PIN(188, "SRCCLKREQB_15"),
244 	PINCTRL_PIN(189, "SML2CLK"),
245 	PINCTRL_PIN(190, "SML2DATA"),
246 	PINCTRL_PIN(191, "SML2ALERTB"),
247 	PINCTRL_PIN(192, "SML3CLK"),
248 	PINCTRL_PIN(193, "SML3DATA"),
249 	PINCTRL_PIN(194, "SML3ALERTB"),
250 	PINCTRL_PIN(195, "SML4CLK"),
251 	PINCTRL_PIN(196, "SML4DATA"),
252 	PINCTRL_PIN(197, "SML4ALERTB"),
253 	PINCTRL_PIN(198, "ISH_I2C0_SDA"),
254 	PINCTRL_PIN(199, "ISH_I2C0_SCL"),
255 	PINCTRL_PIN(200, "ISH_I2C1_SDA"),
256 	PINCTRL_PIN(201, "ISH_I2C1_SCL"),
257 	PINCTRL_PIN(202, "TIME_SYNC_0"),
258 	/* GPP_E */
259 	PINCTRL_PIN(203, "SATAXPCIE_0"),
260 	PINCTRL_PIN(204, "SATAXPCIE_1"),
261 	PINCTRL_PIN(205, "SATAXPCIE_2"),
262 	PINCTRL_PIN(206, "CPU_GP_0"),
263 	PINCTRL_PIN(207, "SATA_DEVSLP_0"),
264 	PINCTRL_PIN(208, "SATA_DEVSLP_1"),
265 	PINCTRL_PIN(209, "SATA_DEVSLP_2"),
266 	PINCTRL_PIN(210, "CPU_GP_1"),
267 	PINCTRL_PIN(211, "SATA_LEDB"),
268 	PINCTRL_PIN(212, "USB2_OCB_0"),
269 	PINCTRL_PIN(213, "USB2_OCB_1"),
270 	PINCTRL_PIN(214, "USB2_OCB_2"),
271 	PINCTRL_PIN(215, "USB2_OCB_3"),
272 	/* GPP_F */
273 	PINCTRL_PIN(216, "SATAXPCIE_3"),
274 	PINCTRL_PIN(217, "SATAXPCIE_4"),
275 	PINCTRL_PIN(218, "SATAXPCIE_5"),
276 	PINCTRL_PIN(219, "SATAXPCIE_6"),
277 	PINCTRL_PIN(220, "SATAXPCIE_7"),
278 	PINCTRL_PIN(221, "SATA_DEVSLP_3"),
279 	PINCTRL_PIN(222, "SATA_DEVSLP_4"),
280 	PINCTRL_PIN(223, "SATA_DEVSLP_5"),
281 	PINCTRL_PIN(224, "SATA_DEVSLP_6"),
282 	PINCTRL_PIN(225, "SATA_DEVSLP_7"),
283 	PINCTRL_PIN(226, "SATA_SCLOCK"),
284 	PINCTRL_PIN(227, "SATA_SLOAD"),
285 	PINCTRL_PIN(228, "SATA_SDATAOUT1"),
286 	PINCTRL_PIN(229, "SATA_SDATAOUT0"),
287 	PINCTRL_PIN(230, "EXT_PWR_GATEB"),
288 	PINCTRL_PIN(231, "USB2_OCB_4"),
289 	PINCTRL_PIN(232, "USB2_OCB_5"),
290 	PINCTRL_PIN(233, "USB2_OCB_6"),
291 	PINCTRL_PIN(234, "USB2_OCB_7"),
292 	PINCTRL_PIN(235, "L_VDDEN"),
293 	PINCTRL_PIN(236, "L_BKLTEN"),
294 	PINCTRL_PIN(237, "L_BKLTCTL"),
295 	PINCTRL_PIN(238, "DDPF_CTRLCLK"),
296 	PINCTRL_PIN(239, "DDPF_CTRLDATA"),
297 	/* SPI */
298 	PINCTRL_PIN(240, "SPI0_IO_2"),
299 	PINCTRL_PIN(241, "SPI0_IO_3"),
300 	PINCTRL_PIN(242, "SPI0_MOSI_IO_0"),
301 	PINCTRL_PIN(243, "SPI0_MISO_IO_1"),
302 	PINCTRL_PIN(244, "SPI0_TPM_CSB"),
303 	PINCTRL_PIN(245, "SPI0_FLASH_0_CSB"),
304 	PINCTRL_PIN(246, "SPI0_FLASH_1_CSB"),
305 	PINCTRL_PIN(247, "SPI0_CLK"),
306 	PINCTRL_PIN(248, "SPI0_CLK_LOOPBK"),
307 	/* CPU */
308 	PINCTRL_PIN(249, "HDACPU_SDI"),
309 	PINCTRL_PIN(250, "HDACPU_SDO"),
310 	PINCTRL_PIN(251, "HDACPU_SCLK"),
311 	PINCTRL_PIN(252, "PM_SYNC"),
312 	PINCTRL_PIN(253, "PECI"),
313 	PINCTRL_PIN(254, "CPUPWRGD"),
314 	PINCTRL_PIN(255, "THRMTRIPB"),
315 	PINCTRL_PIN(256, "PLTRST_CPUB"),
316 	PINCTRL_PIN(257, "PM_DOWN"),
317 	PINCTRL_PIN(258, "TRIGGER_IN"),
318 	PINCTRL_PIN(259, "TRIGGER_OUT"),
319 	/* JTAG */
320 	PINCTRL_PIN(260, "JTAG_TDO"),
321 	PINCTRL_PIN(261, "JTAGX"),
322 	PINCTRL_PIN(262, "PRDYB"),
323 	PINCTRL_PIN(263, "PREQB"),
324 	PINCTRL_PIN(264, "CPU_TRSTB"),
325 	PINCTRL_PIN(265, "JTAG_TDI"),
326 	PINCTRL_PIN(266, "JTAG_TMS"),
327 	PINCTRL_PIN(267, "JTAG_TCK"),
328 	PINCTRL_PIN(268, "ITP_PMODE"),
329 	/* GPP_I */
330 	PINCTRL_PIN(269, "DDSP_HPD_0"),
331 	PINCTRL_PIN(270, "DDSP_HPD_1"),
332 	PINCTRL_PIN(271, "DDSP_HPD_2"),
333 	PINCTRL_PIN(272, "DDSP_HPD_3"),
334 	PINCTRL_PIN(273, "EDP_HPD"),
335 	PINCTRL_PIN(274, "DDPB_CTRLCLK"),
336 	PINCTRL_PIN(275, "DDPB_CTRLDATA"),
337 	PINCTRL_PIN(276, "DDPC_CTRLCLK"),
338 	PINCTRL_PIN(277, "DDPC_CTRLDATA"),
339 	PINCTRL_PIN(278, "DDPD_CTRLCLK"),
340 	PINCTRL_PIN(279, "DDPD_CTRLDATA"),
341 	PINCTRL_PIN(280, "M2_SKT2_CFG_0"),
342 	PINCTRL_PIN(281, "M2_SKT2_CFG_1"),
343 	PINCTRL_PIN(282, "M2_SKT2_CFG_2"),
344 	PINCTRL_PIN(283, "M2_SKT2_CFG_3"),
345 	PINCTRL_PIN(284, "SYS_PWROK"),
346 	PINCTRL_PIN(285, "SYS_RESETB"),
347 	PINCTRL_PIN(286, "MLK_RSTB"),
348 	/* GPP_J */
349 	PINCTRL_PIN(287, "CNV_PA_BLANKING"),
350 	PINCTRL_PIN(288, "CNV_GNSS_FTA"),
351 	PINCTRL_PIN(289, "CNV_GNSS_SYSCK"),
352 	PINCTRL_PIN(290, "CNV_RF_RESET_B"),
353 	PINCTRL_PIN(291, "CNV_BRI_DT"),
354 	PINCTRL_PIN(292, "CNV_BRI_RSP"),
355 	PINCTRL_PIN(293, "CNV_RGI_DT"),
356 	PINCTRL_PIN(294, "CNV_RGI_RSP"),
357 	PINCTRL_PIN(295, "CNV_MFUART2_RXD"),
358 	PINCTRL_PIN(296, "CNV_MFUART2_TXD"),
359 	PINCTRL_PIN(297, "CNV_MODEM_CLKREQ"),
360 	PINCTRL_PIN(298, "A4WP_PRESENT"),
361 };
362 
363 static const struct intel_padgroup cnlh_community0_gpps[] = {
364 	CNL_GPP(0, 0, 24, 0),			/* GPP_A */
365 	CNL_GPP(1, 25, 50, 32),			/* GPP_B */
366 };
367 
368 static const struct intel_padgroup cnlh_community1_gpps[] = {
369 	CNL_GPP(0, 51, 74, 64),				/* GPP_C */
370 	CNL_GPP(1, 75, 98, 96),				/* GPP_D */
371 	CNL_GPP(2, 99, 106, 128),			/* GPP_G */
372 	CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP),	/* AZA */
373 	CNL_GPP(4, 115, 146, 160),			/* vGPIO_0 */
374 	CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP),	/* vGPIO_1 */
375 };
376 
377 static const struct intel_padgroup cnlh_community3_gpps[] = {
378 	CNL_GPP(0, 155, 178, 192),			/* GPP_K */
379 	CNL_GPP(1, 179, 202, 224),			/* GPP_H */
380 	CNL_GPP(2, 203, 215, 256),			/* GPP_E */
381 	CNL_GPP(3, 216, 239, 288),			/* GPP_F */
382 	CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP),	/* SPI */
383 };
384 
385 static const struct intel_padgroup cnlh_community4_gpps[] = {
386 	CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP),	/* CPU */
387 	CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP),	/* JTAG */
388 	CNL_GPP(2, 269, 286, 320),			/* GPP_I */
389 	CNL_GPP(3, 287, 298, 352),			/* GPP_J */
390 };
391 
392 static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
393 static const unsigned int cnlh_spi1_pins[] = { 44, 45, 46, 47 };
394 static const unsigned int cnlh_spi2_pins[] = { 84, 85, 86, 87 };
395 
396 static const unsigned int cnlh_uart0_pins[] = { 59, 60, 61, 62 };
397 static const unsigned int cnlh_uart1_pins[] = { 63, 64, 65, 66 };
398 static const unsigned int cnlh_uart2_pins[] = { 71, 72, 73, 74 };
399 
400 static const unsigned int cnlh_i2c0_pins[] = { 67, 68 };
401 static const unsigned int cnlh_i2c1_pins[] = { 69, 70 };
402 static const unsigned int cnlh_i2c2_pins[] = { 88, 89 };
403 static const unsigned int cnlh_i2c3_pins[] = { 79, 98 };
404 
405 static const struct intel_pingroup cnlh_groups[] = {
406 	PIN_GROUP("spi0_grp", cnlh_spi0_pins, 1),
407 	PIN_GROUP("spi1_grp", cnlh_spi1_pins, 1),
408 	PIN_GROUP("spi2_grp", cnlh_spi2_pins, 3),
409 	PIN_GROUP("uart0_grp", cnlh_uart0_pins, 1),
410 	PIN_GROUP("uart1_grp", cnlh_uart1_pins, 1),
411 	PIN_GROUP("uart2_grp", cnlh_uart2_pins, 1),
412 	PIN_GROUP("i2c0_grp", cnlh_i2c0_pins, 1),
413 	PIN_GROUP("i2c1_grp", cnlh_i2c1_pins, 1),
414 	PIN_GROUP("i2c2_grp", cnlh_i2c2_pins, 3),
415 	PIN_GROUP("i2c3_grp", cnlh_i2c3_pins, 2),
416 };
417 
418 static const char * const cnlh_spi0_groups[] = { "spi0_grp" };
419 static const char * const cnlh_spi1_groups[] = { "spi1_grp" };
420 static const char * const cnlh_spi2_groups[] = { "spi2_grp" };
421 static const char * const cnlh_uart0_groups[] = { "uart0_grp" };
422 static const char * const cnlh_uart1_groups[] = { "uart1_grp" };
423 static const char * const cnlh_uart2_groups[] = { "uart2_grp" };
424 static const char * const cnlh_i2c0_groups[] = { "i2c0_grp" };
425 static const char * const cnlh_i2c1_groups[] = { "i2c1_grp" };
426 static const char * const cnlh_i2c2_groups[] = { "i2c2_grp" };
427 static const char * const cnlh_i2c3_groups[] = { "i2c3_grp" };
428 
429 static const struct intel_function cnlh_functions[] = {
430 	FUNCTION("spi0", cnlh_spi0_groups),
431 	FUNCTION("spi1", cnlh_spi1_groups),
432 	FUNCTION("spi2", cnlh_spi2_groups),
433 	FUNCTION("uart0", cnlh_uart0_groups),
434 	FUNCTION("uart1", cnlh_uart1_groups),
435 	FUNCTION("uart2", cnlh_uart2_groups),
436 	FUNCTION("i2c0", cnlh_i2c0_groups),
437 	FUNCTION("i2c1", cnlh_i2c1_groups),
438 	FUNCTION("i2c2", cnlh_i2c2_groups),
439 	FUNCTION("i2c3", cnlh_i2c3_groups),
440 };
441 
442 static const struct intel_community cnlh_communities[] = {
443 	CNL_H_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
444 	CNL_H_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
445 	CNL_H_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
446 	CNL_H_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
447 };
448 
449 static const struct intel_pinctrl_soc_data cnlh_soc_data = {
450 	.pins = cnlh_pins,
451 	.npins = ARRAY_SIZE(cnlh_pins),
452 	.groups = cnlh_groups,
453 	.ngroups = ARRAY_SIZE(cnlh_groups),
454 	.functions = cnlh_functions,
455 	.nfunctions = ARRAY_SIZE(cnlh_functions),
456 	.communities = cnlh_communities,
457 	.ncommunities = ARRAY_SIZE(cnlh_communities),
458 };
459 
460 /* Cannon Lake-LP */
461 static const struct pinctrl_pin_desc cnllp_pins[] = {
462 	/* GPP_A */
463 	PINCTRL_PIN(0, "RCINB"),
464 	PINCTRL_PIN(1, "LAD_0"),
465 	PINCTRL_PIN(2, "LAD_1"),
466 	PINCTRL_PIN(3, "LAD_2"),
467 	PINCTRL_PIN(4, "LAD_3"),
468 	PINCTRL_PIN(5, "LFRAMEB"),
469 	PINCTRL_PIN(6, "SERIRQ"),
470 	PINCTRL_PIN(7, "PIRQAB"),
471 	PINCTRL_PIN(8, "CLKRUNB"),
472 	PINCTRL_PIN(9, "CLKOUT_LPC_0"),
473 	PINCTRL_PIN(10, "CLKOUT_LPC_1"),
474 	PINCTRL_PIN(11, "PMEB"),
475 	PINCTRL_PIN(12, "BM_BUSYB"),
476 	PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
477 	PINCTRL_PIN(14, "SUS_STATB"),
478 	PINCTRL_PIN(15, "SUSACKB"),
479 	PINCTRL_PIN(16, "SD_1P8_SEL"),
480 	PINCTRL_PIN(17, "SD_PWR_EN_B"),
481 	PINCTRL_PIN(18, "ISH_GP_0"),
482 	PINCTRL_PIN(19, "ISH_GP_1"),
483 	PINCTRL_PIN(20, "ISH_GP_2"),
484 	PINCTRL_PIN(21, "ISH_GP_3"),
485 	PINCTRL_PIN(22, "ISH_GP_4"),
486 	PINCTRL_PIN(23, "ISH_GP_5"),
487 	PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
488 	/* GPP_B */
489 	PINCTRL_PIN(25, "CORE_VID_0"),
490 	PINCTRL_PIN(26, "CORE_VID_1"),
491 	PINCTRL_PIN(27, "VRALERTB"),
492 	PINCTRL_PIN(28, "CPU_GP_2"),
493 	PINCTRL_PIN(29, "CPU_GP_3"),
494 	PINCTRL_PIN(30, "SRCCLKREQB_0"),
495 	PINCTRL_PIN(31, "SRCCLKREQB_1"),
496 	PINCTRL_PIN(32, "SRCCLKREQB_2"),
497 	PINCTRL_PIN(33, "SRCCLKREQB_3"),
498 	PINCTRL_PIN(34, "SRCCLKREQB_4"),
499 	PINCTRL_PIN(35, "SRCCLKREQB_5"),
500 	PINCTRL_PIN(36, "EXT_PWR_GATEB"),
501 	PINCTRL_PIN(37, "SLP_S0B"),
502 	PINCTRL_PIN(38, "PLTRSTB"),
503 	PINCTRL_PIN(39, "SPKR"),
504 	PINCTRL_PIN(40, "GSPI0_CS0B"),
505 	PINCTRL_PIN(41, "GSPI0_CLK"),
506 	PINCTRL_PIN(42, "GSPI0_MISO"),
507 	PINCTRL_PIN(43, "GSPI0_MOSI"),
508 	PINCTRL_PIN(44, "GSPI1_CS0B"),
509 	PINCTRL_PIN(45, "GSPI1_CLK"),
510 	PINCTRL_PIN(46, "GSPI1_MISO"),
511 	PINCTRL_PIN(47, "GSPI1_MOSI"),
512 	PINCTRL_PIN(48, "SML1ALERTB"),
513 	PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),
514 	PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"),
515 	/* GPP_G */
516 	PINCTRL_PIN(51, "SD3_CMD"),
517 	PINCTRL_PIN(52, "SD3_D0_SD4_RCLK_P"),
518 	PINCTRL_PIN(53, "SD3_D1_SD4_RCLK_N"),
519 	PINCTRL_PIN(54, "SD3_D2"),
520 	PINCTRL_PIN(55, "SD3_D3"),
521 	PINCTRL_PIN(56, "SD3_CDB"),
522 	PINCTRL_PIN(57, "SD3_CLK"),
523 	PINCTRL_PIN(58, "SD3_WP"),
524 	/* SPI */
525 	PINCTRL_PIN(59, "SPI0_IO_2"),
526 	PINCTRL_PIN(60, "SPI0_IO_3"),
527 	PINCTRL_PIN(61, "SPI0_MOSI_IO_0"),
528 	PINCTRL_PIN(62, "SPI0_MISO_IO_1"),
529 	PINCTRL_PIN(63, "SPI0_TPM_CSB"),
530 	PINCTRL_PIN(64, "SPI0_FLASH_0_CSB"),
531 	PINCTRL_PIN(65, "SPI0_FLASH_1_CSB"),
532 	PINCTRL_PIN(66, "SPI0_CLK"),
533 	PINCTRL_PIN(67, "SPI0_CLK_LOOPBK"),
534 	/* GPP_D */
535 	PINCTRL_PIN(68, "SPI1_CSB"),
536 	PINCTRL_PIN(69, "SPI1_CLK"),
537 	PINCTRL_PIN(70, "SPI1_MISO_IO_1"),
538 	PINCTRL_PIN(71, "SPI1_MOSI_IO_0"),
539 	PINCTRL_PIN(72, "IMGCLKOUT_0"),
540 	PINCTRL_PIN(73, "ISH_I2C0_SDA"),
541 	PINCTRL_PIN(74, "ISH_I2C0_SCL"),
542 	PINCTRL_PIN(75, "ISH_I2C1_SDA"),
543 	PINCTRL_PIN(76, "ISH_I2C1_SCL"),
544 	PINCTRL_PIN(77, "ISH_SPI_CSB"),
545 	PINCTRL_PIN(78, "ISH_SPI_CLK"),
546 	PINCTRL_PIN(79, "ISH_SPI_MISO"),
547 	PINCTRL_PIN(80, "ISH_SPI_MOSI"),
548 	PINCTRL_PIN(81, "ISH_UART0_RXD"),
549 	PINCTRL_PIN(82, "ISH_UART0_TXD"),
550 	PINCTRL_PIN(83, "ISH_UART0_RTSB"),
551 	PINCTRL_PIN(84, "ISH_UART0_CTSB"),
552 	PINCTRL_PIN(85, "DMIC_CLK_1"),
553 	PINCTRL_PIN(86, "DMIC_DATA_1"),
554 	PINCTRL_PIN(87, "DMIC_CLK_0"),
555 	PINCTRL_PIN(88, "DMIC_DATA_0"),
556 	PINCTRL_PIN(89, "SPI1_IO_2"),
557 	PINCTRL_PIN(90, "SPI1_IO_3"),
558 	PINCTRL_PIN(91, "SSP_MCLK"),
559 	PINCTRL_PIN(92, "GSPI2_CLK_LOOPBK"),
560 	/* GPP_F */
561 	PINCTRL_PIN(93, "CNV_GNSS_PA_BLANKING"),
562 	PINCTRL_PIN(94, "CNV_GNSS_FTA"),
563 	PINCTRL_PIN(95, "CNV_GNSS_SYSCK"),
564 	PINCTRL_PIN(96, "EMMC_HIP_MON"),
565 	PINCTRL_PIN(97, "CNV_BRI_DT"),
566 	PINCTRL_PIN(98, "CNV_BRI_RSP"),
567 	PINCTRL_PIN(99, "CNV_RGI_DT"),
568 	PINCTRL_PIN(100, "CNV_RGI_RSP"),
569 	PINCTRL_PIN(101, "CNV_MFUART2_RXD"),
570 	PINCTRL_PIN(102, "CNV_MFUART2_TXD"),
571 	PINCTRL_PIN(103, "GPP_F_10"),
572 	PINCTRL_PIN(104, "EMMC_CMD"),
573 	PINCTRL_PIN(105, "EMMC_DATA_0"),
574 	PINCTRL_PIN(106, "EMMC_DATA_1"),
575 	PINCTRL_PIN(107, "EMMC_DATA_2"),
576 	PINCTRL_PIN(108, "EMMC_DATA_3"),
577 	PINCTRL_PIN(109, "EMMC_DATA_4"),
578 	PINCTRL_PIN(110, "EMMC_DATA_5"),
579 	PINCTRL_PIN(111, "EMMC_DATA_6"),
580 	PINCTRL_PIN(112, "EMMC_DATA_7"),
581 	PINCTRL_PIN(113, "EMMC_RCLK"),
582 	PINCTRL_PIN(114, "EMMC_CLK"),
583 	PINCTRL_PIN(115, "EMMC_RESETB"),
584 	PINCTRL_PIN(116, "A4WP_PRESENT"),
585 	/* GPP_H */
586 	PINCTRL_PIN(117, "SSP2_SCLK"),
587 	PINCTRL_PIN(118, "SSP2_SFRM"),
588 	PINCTRL_PIN(119, "SSP2_TXD"),
589 	PINCTRL_PIN(120, "SSP2_RXD"),
590 	PINCTRL_PIN(121, "I2C2_SDA"),
591 	PINCTRL_PIN(122, "I2C2_SCL"),
592 	PINCTRL_PIN(123, "I2C3_SDA"),
593 	PINCTRL_PIN(124, "I2C3_SCL"),
594 	PINCTRL_PIN(125, "I2C4_SDA"),
595 	PINCTRL_PIN(126, "I2C4_SCL"),
596 	PINCTRL_PIN(127, "I2C5_SDA"),
597 	PINCTRL_PIN(128, "I2C5_SCL"),
598 	PINCTRL_PIN(129, "M2_SKT2_CFG_0"),
599 	PINCTRL_PIN(130, "M2_SKT2_CFG_1"),
600 	PINCTRL_PIN(131, "M2_SKT2_CFG_2"),
601 	PINCTRL_PIN(132, "M2_SKT2_CFG_3"),
602 	PINCTRL_PIN(133, "DDPF_CTRLCLK"),
603 	PINCTRL_PIN(134, "DDPF_CTRLDATA"),
604 	PINCTRL_PIN(135, "CPU_VCCIO_PWR_GATEB"),
605 	PINCTRL_PIN(136, "TIMESYNC_0"),
606 	PINCTRL_PIN(137, "IMGCLKOUT_1"),
607 	PINCTRL_PIN(138, "GPPC_H_21"),
608 	PINCTRL_PIN(139, "GPPC_H_22"),
609 	PINCTRL_PIN(140, "GPPC_H_23"),
610 	/* vGPIO */
611 	PINCTRL_PIN(141, "CNV_BTEN"),
612 	PINCTRL_PIN(142, "CNV_GNEN"),
613 	PINCTRL_PIN(143, "CNV_WFEN"),
614 	PINCTRL_PIN(144, "CNV_WCEN"),
615 	PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"),
616 	PINCTRL_PIN(146, "CNV_BT_IF_SELECT"),
617 	PINCTRL_PIN(147, "vCNV_BT_UART_TXD"),
618 	PINCTRL_PIN(148, "vCNV_BT_UART_RXD"),
619 	PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"),
620 	PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"),
621 	PINCTRL_PIN(151, "vCNV_MFUART1_TXD"),
622 	PINCTRL_PIN(152, "vCNV_MFUART1_RXD"),
623 	PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"),
624 	PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"),
625 	PINCTRL_PIN(155, "vCNV_GNSS_UART_TXD"),
626 	PINCTRL_PIN(156, "vCNV_GNSS_UART_RXD"),
627 	PINCTRL_PIN(157, "vCNV_GNSS_UART_CTS_B"),
628 	PINCTRL_PIN(158, "vCNV_GNSS_UART_RTS_B"),
629 	PINCTRL_PIN(159, "vUART0_TXD"),
630 	PINCTRL_PIN(160, "vUART0_RXD"),
631 	PINCTRL_PIN(161, "vUART0_CTS_B"),
632 	PINCTRL_PIN(162, "vUART0_RTS_B"),
633 	PINCTRL_PIN(163, "vISH_UART0_TXD"),
634 	PINCTRL_PIN(164, "vISH_UART0_RXD"),
635 	PINCTRL_PIN(165, "vISH_UART0_CTS_B"),
636 	PINCTRL_PIN(166, "vISH_UART0_RTS_B"),
637 	PINCTRL_PIN(167, "vISH_UART1_TXD"),
638 	PINCTRL_PIN(168, "vISH_UART1_RXD"),
639 	PINCTRL_PIN(169, "vISH_UART1_CTS_B"),
640 	PINCTRL_PIN(170, "vISH_UART1_RTS_B"),
641 	PINCTRL_PIN(171, "vCNV_BT_I2S_BCLK"),
642 	PINCTRL_PIN(172, "vCNV_BT_I2S_WS_SYNC"),
643 	PINCTRL_PIN(173, "vCNV_BT_I2S_SDO"),
644 	PINCTRL_PIN(174, "vCNV_BT_I2S_SDI"),
645 	PINCTRL_PIN(175, "vSSP2_SCLK"),
646 	PINCTRL_PIN(176, "vSSP2_SFRM"),
647 	PINCTRL_PIN(177, "vSSP2_TXD"),
648 	PINCTRL_PIN(178, "vSSP2_RXD"),
649 	PINCTRL_PIN(179, "vCNV_GNSS_HOST_WAKEB"),
650 	PINCTRL_PIN(180, "vSD3_CD_B"),
651 	/* GPP_C */
652 	PINCTRL_PIN(181, "SMBCLK"),
653 	PINCTRL_PIN(182, "SMBDATA"),
654 	PINCTRL_PIN(183, "SMBALERTB"),
655 	PINCTRL_PIN(184, "SML0CLK"),
656 	PINCTRL_PIN(185, "SML0DATA"),
657 	PINCTRL_PIN(186, "SML0ALERTB"),
658 	PINCTRL_PIN(187, "SML1CLK"),
659 	PINCTRL_PIN(188, "SML1DATA"),
660 	PINCTRL_PIN(189, "UART0_RXD"),
661 	PINCTRL_PIN(190, "UART0_TXD"),
662 	PINCTRL_PIN(191, "UART0_RTSB"),
663 	PINCTRL_PIN(192, "UART0_CTSB"),
664 	PINCTRL_PIN(193, "UART1_RXD"),
665 	PINCTRL_PIN(194, "UART1_TXD"),
666 	PINCTRL_PIN(195, "UART1_RTSB"),
667 	PINCTRL_PIN(196, "UART1_CTSB"),
668 	PINCTRL_PIN(197, "I2C0_SDA"),
669 	PINCTRL_PIN(198, "I2C0_SCL"),
670 	PINCTRL_PIN(199, "I2C1_SDA"),
671 	PINCTRL_PIN(200, "I2C1_SCL"),
672 	PINCTRL_PIN(201, "UART2_RXD"),
673 	PINCTRL_PIN(202, "UART2_TXD"),
674 	PINCTRL_PIN(203, "UART2_RTSB"),
675 	PINCTRL_PIN(204, "UART2_CTSB"),
676 	/* GPP_E */
677 	PINCTRL_PIN(205, "SATAXPCIE_0"),
678 	PINCTRL_PIN(206, "SATAXPCIE_1"),
679 	PINCTRL_PIN(207, "SATAXPCIE_2"),
680 	PINCTRL_PIN(208, "CPU_GP_0"),
681 	PINCTRL_PIN(209, "SATA_DEVSLP_0"),
682 	PINCTRL_PIN(210, "SATA_DEVSLP_1"),
683 	PINCTRL_PIN(211, "SATA_DEVSLP_2"),
684 	PINCTRL_PIN(212, "CPU_GP_1"),
685 	PINCTRL_PIN(213, "SATA_LEDB"),
686 	PINCTRL_PIN(214, "USB2_OCB_0"),
687 	PINCTRL_PIN(215, "USB2_OCB_1"),
688 	PINCTRL_PIN(216, "USB2_OCB_2"),
689 	PINCTRL_PIN(217, "USB2_OCB_3"),
690 	PINCTRL_PIN(218, "DDSP_HPD_0"),
691 	PINCTRL_PIN(219, "DDSP_HPD_1"),
692 	PINCTRL_PIN(220, "DDSP_HPD_2"),
693 	PINCTRL_PIN(221, "DDSP_HPD_3"),
694 	PINCTRL_PIN(222, "EDP_HPD"),
695 	PINCTRL_PIN(223, "DDPB_CTRLCLK"),
696 	PINCTRL_PIN(224, "DDPB_CTRLDATA"),
697 	PINCTRL_PIN(225, "DDPC_CTRLCLK"),
698 	PINCTRL_PIN(226, "DDPC_CTRLDATA"),
699 	PINCTRL_PIN(227, "DDPD_CTRLCLK"),
700 	PINCTRL_PIN(228, "DDPD_CTRLDATA"),
701 	/* JTAG */
702 	PINCTRL_PIN(229, "JTAG_TDO"),
703 	PINCTRL_PIN(230, "JTAGX"),
704 	PINCTRL_PIN(231, "PRDYB"),
705 	PINCTRL_PIN(232, "PREQB"),
706 	PINCTRL_PIN(233, "CPU_TRSTB"),
707 	PINCTRL_PIN(234, "JTAG_TDI"),
708 	PINCTRL_PIN(235, "JTAG_TMS"),
709 	PINCTRL_PIN(236, "JTAG_TCK"),
710 	PINCTRL_PIN(237, "ITP_PMODE"),
711 	/* HVCMOS */
712 	PINCTRL_PIN(238, "L_BKLTEN"),
713 	PINCTRL_PIN(239, "L_BKLTCTL"),
714 	PINCTRL_PIN(240, "L_VDDEN"),
715 	PINCTRL_PIN(241, "SYS_PWROK"),
716 	PINCTRL_PIN(242, "SYS_RESETB"),
717 	PINCTRL_PIN(243, "MLK_RSTB"),
718 };
719 
720 static const unsigned int cnllp_spi0_pins[] = { 40, 41, 42, 43, 7 };
721 static const unsigned int cnllp_spi0_modes[] = { 1, 1, 1, 1, 2 };
722 static const unsigned int cnllp_spi1_pins[] = { 44, 45, 46, 47, 11 };
723 static const unsigned int cnllp_spi1_modes[] = { 1, 1, 1, 1, 2 };
724 static const unsigned int cnllp_spi2_pins[] = { 77, 78, 79, 80, 83 };
725 static const unsigned int cnllp_spi2_modes[] = { 3, 3, 3, 3, 2 };
726 
727 static const unsigned int cnllp_i2c0_pins[] = { 197, 198 };
728 static const unsigned int cnllp_i2c1_pins[] = { 199, 200 };
729 static const unsigned int cnllp_i2c2_pins[] = { 121, 122 };
730 static const unsigned int cnllp_i2c3_pins[] = { 123, 124 };
731 static const unsigned int cnllp_i2c4_pins[] = { 125, 126 };
732 static const unsigned int cnllp_i2c5_pins[] = { 127, 128 };
733 
734 static const unsigned int cnllp_uart0_pins[] = { 189, 190, 191, 192 };
735 static const unsigned int cnllp_uart1_pins[] = { 193, 194, 195, 196 };
736 static const unsigned int cnllp_uart2_pins[] = { 201, 202, 203, 204 };
737 
738 static const struct intel_pingroup cnllp_groups[] = {
739 	PIN_GROUP("spi0_grp", cnllp_spi0_pins, cnllp_spi0_modes),
740 	PIN_GROUP("spi1_grp", cnllp_spi1_pins, cnllp_spi1_modes),
741 	PIN_GROUP("spi2_grp", cnllp_spi2_pins, cnllp_spi2_modes),
742 	PIN_GROUP("i2c0_grp", cnllp_i2c0_pins, 1),
743 	PIN_GROUP("i2c1_grp", cnllp_i2c1_pins, 1),
744 	PIN_GROUP("i2c2_grp", cnllp_i2c2_pins, 1),
745 	PIN_GROUP("i2c3_grp", cnllp_i2c3_pins, 1),
746 	PIN_GROUP("i2c4_grp", cnllp_i2c4_pins, 1),
747 	PIN_GROUP("i2c5_grp", cnllp_i2c5_pins, 1),
748 	PIN_GROUP("uart0_grp", cnllp_uart0_pins, 1),
749 	PIN_GROUP("uart1_grp", cnllp_uart1_pins, 1),
750 	PIN_GROUP("uart2_grp", cnllp_uart2_pins, 1),
751 };
752 
753 static const char * const cnllp_spi0_groups[] = { "spi0_grp" };
754 static const char * const cnllp_spi1_groups[] = { "spi1_grp" };
755 static const char * const cnllp_spi2_groups[] = { "spi2_grp" };
756 static const char * const cnllp_i2c0_groups[] = { "i2c0_grp" };
757 static const char * const cnllp_i2c1_groups[] = { "i2c1_grp" };
758 static const char * const cnllp_i2c2_groups[] = { "i2c2_grp" };
759 static const char * const cnllp_i2c3_groups[] = { "i2c3_grp" };
760 static const char * const cnllp_i2c4_groups[] = { "i2c4_grp" };
761 static const char * const cnllp_i2c5_groups[] = { "i2c5_grp" };
762 static const char * const cnllp_uart0_groups[] = { "uart0_grp" };
763 static const char * const cnllp_uart1_groups[] = { "uart1_grp" };
764 static const char * const cnllp_uart2_groups[] = { "uart2_grp" };
765 
766 static const struct intel_function cnllp_functions[] = {
767 	FUNCTION("spi0", cnllp_spi0_groups),
768 	FUNCTION("spi1", cnllp_spi1_groups),
769 	FUNCTION("spi2", cnllp_spi2_groups),
770 	FUNCTION("i2c0", cnllp_i2c0_groups),
771 	FUNCTION("i2c1", cnllp_i2c1_groups),
772 	FUNCTION("i2c2", cnllp_i2c2_groups),
773 	FUNCTION("i2c3", cnllp_i2c3_groups),
774 	FUNCTION("i2c4", cnllp_i2c4_groups),
775 	FUNCTION("i2c5", cnllp_i2c5_groups),
776 	FUNCTION("uart0", cnllp_uart0_groups),
777 	FUNCTION("uart1", cnllp_uart1_groups),
778 	FUNCTION("uart2", cnllp_uart2_groups),
779 };
780 
781 static const struct intel_padgroup cnllp_community0_gpps[] = {
782 	CNL_GPP(0, 0, 24, 0),				/* GPP_A */
783 	CNL_GPP(1, 25, 50, 32),				/* GPP_B */
784 	CNL_GPP(2, 51, 58, 64),				/* GPP_G */
785 	CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP),	/* SPI */
786 };
787 
788 static const struct intel_padgroup cnllp_community1_gpps[] = {
789 	CNL_GPP(0, 68, 92, 96),				/* GPP_D */
790 	CNL_GPP(1, 93, 116, 128),			/* GPP_F */
791 	CNL_GPP(2, 117, 140, 160),			/* GPP_H */
792 	CNL_GPP(3, 141, 172, 192),			/* vGPIO */
793 	CNL_GPP(4, 173, 180, 224),			/* vGPIO */
794 };
795 
796 static const struct intel_padgroup cnllp_community4_gpps[] = {
797 	CNL_GPP(0, 181, 204, 256),			/* GPP_C */
798 	CNL_GPP(1, 205, 228, 288),			/* GPP_E */
799 	CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP),	/* JTAG */
800 	CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */
801 };
802 
803 static const struct intel_community cnllp_communities[] = {
804 	CNL_LP_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
805 	CNL_LP_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
806 	CNL_LP_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
807 };
808 
809 static const struct intel_pinctrl_soc_data cnllp_soc_data = {
810 	.pins = cnllp_pins,
811 	.npins = ARRAY_SIZE(cnllp_pins),
812 	.groups = cnllp_groups,
813 	.ngroups = ARRAY_SIZE(cnllp_groups),
814 	.functions = cnllp_functions,
815 	.nfunctions = ARRAY_SIZE(cnllp_functions),
816 	.communities = cnllp_communities,
817 	.ncommunities = ARRAY_SIZE(cnllp_communities),
818 };
819 
820 static const struct acpi_device_id cnl_pinctrl_acpi_match[] = {
821 	{ "INT3450", (kernel_ulong_t)&cnlh_soc_data },
822 	{ "INT34BB", (kernel_ulong_t)&cnllp_soc_data },
823 	{ }
824 };
825 MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match);
826 
827 static INTEL_PINCTRL_PM_OPS(cnl_pinctrl_pm_ops);
828 
829 static struct platform_driver cnl_pinctrl_driver = {
830 	.probe = intel_pinctrl_probe_by_hid,
831 	.driver = {
832 		.name = "cannonlake-pinctrl",
833 		.acpi_match_table = cnl_pinctrl_acpi_match,
834 		.pm = &cnl_pinctrl_pm_ops,
835 	},
836 };
837 module_platform_driver(cnl_pinctrl_driver);
838 
839 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
840 MODULE_DESCRIPTION("Intel Cannon Lake PCH pinctrl/GPIO driver");
841 MODULE_LICENSE("GPL v2");
842 MODULE_IMPORT_NS(PINCTRL_INTEL);
843