| /openbmc/linux/Documentation/devicetree/bindings/arm/stm32/ |
| H A D | stm32.yaml | 17 - description: emtrion STM32MP1 Argon based Boards
111 - description: DH STM32MP1 SoM based Boards
118 - description: DH STM32MP1 SoM based Boards
126 - description: Engicam i.Core STM32MP1 SoM based Boards
129 - engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0
130 … - engicam,icore-stm32mp1-ctouch2-of10 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
131 … - engicam,icore-stm32mp1-edimm2.2 # STM32MP1 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit
132 - const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM
135 - description: Engicam MicroGEA STM32MP1 SoM based Boards
138 - engicam,microgea-stm32mp1-microdev2.0
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | st,stm32mp1-rcc.yaml | 4 $id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml#
7 title: STMicroelectronics STM32MP1 Reset Clock Controller
24 dt-bindings/clock/stm32mp1-clks.h header and can be used in device
38 For example on STM32MP1, for LTDC reset:
42 The list of valid indices for STM32MP1 is available in:
43 include/dt-bindings/reset-controller/stm32mp1-resets.h
59 - st,stm32mp1-rcc-secure
60 - st,stm32mp1-rcc
80 - st,stm32mp1-rcc-secure
112 #include <dt-bindings/clock/stm32mp1-clks.h>
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| /openbmc/linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | st,stm32-adc.yaml | 29 - st,stm32mp1-adc-core
39 - stm32mp1 has two separate interrupt lines, one for each ADC within
52 It's optional on stm32h7 and stm32mp1.
55 It's required on stm32h7 and stm32mp1.
72 analog input switches on stm32h7 and stm32mp1.
77 input switches on stm32mp1.
82 analog circuitry on stm32mp1.
161 const: st,stm32mp1-adc-core
239 - st,stm32mp1-adc
284 - can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
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| H A D | st,stm32-dfsdm-adc.yaml | 21 up to 4 filters on stm32h7 or 6 filters on stm32mp1.
29 - st,stm32mp1-dfsdm
94 On stm32h7 and stm32mp1:
270 const: st,stm32mp1-dfsdm
284 #include <dt-bindings/clock/stm32mp1-clks.h>
286 compatible = "st,stm32mp1-dfsdm";
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| /openbmc/linux/arch/arm/boot/dts/st/ |
| H A D | Makefile | 43 stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
44 stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
45 stm32mp157a-icore-stm32mp1-ctouch2.dtb \
46 stm32mp157a-icore-stm32mp1-ctouch2-of10.dtb \
47 stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
62 stm32mp157c-phycore-stm32mp1-3.dtb
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| H A D | stm32mp157a-icore-stm32mp1-ctouch2.dts | 10 #include "stm32mp157a-icore-stm32mp1.dtsi"
16 model = "Engicam i.Core STM32MP1 C.TOUCH 2.0";
17 compatible = "engicam,icore-stm32mp1-ctouch2",
18 "engicam,icore-stm32mp1", "st,stm32mp157";
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| H A D | stm32mp157a-microgea-stm32mp1-microdev2.0.dts | 10 #include "stm32mp157a-microgea-stm32mp1.dtsi"
16 model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 Carrier Board";
17 compatible = "engicam,microgea-stm32mp1-microdev2.0",
18 "engicam,microgea-stm32mp1", "st,stm32mp157";
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| H A D | stm32mp157a-icore-stm32mp1-edimm2.2.dts | 10 #include "stm32mp157a-icore-stm32mp1.dtsi"
16 model = "Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit";
17 compatible = "engicam,icore-stm32mp1-edimm2.2",
18 "engicam,icore-stm32mp1", "st,stm32mp157";
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| H A D | stm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 10 #include "stm32mp157a-icore-stm32mp1.dtsi"
16 model = "Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1\" Open Frame";
17 compatible = "engicam,icore-stm32mp1-ctouch2-of10",
18 "engicam,icore-stm32mp1", "st,stm32mp157";
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| H A D | stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 10 #include "stm32mp157a-microgea-stm32mp1.dtsi"
16 model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 7\" Open Frame";
17 compatible = "engicam,microgea-stm32mp1-microdev2.0-of7",
18 "engicam,microgea-stm32mp1", "st,stm32mp157";
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| /openbmc/u-boot/doc/device-tree-bindings/clock/ |
| H A D | st,stm32mp1.txt | 1 STMicroelectronics STM32MP1 clock tree initialization
8 RCC CLOCK = st,stm32mp1-rcc-clk
20 - compatible: Should be "st,stm32mp1-rcc-clk"
28 dt-bindings/clock/stm32mp1-clksrc.h: CLK_<NAME>_<SOURCE>
85 you can use associated defines from stm32mp1-clksrc.h
92 in the file dt-bindings/clock/stm32mp1-clksrc.h
103 compatible = "st,stm32mp1-rcc-clk";
179 (see LSEDRV_ define in the file dt-bindings/clock/stm32mp1-clksrc.h)
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| /openbmc/linux/Documentation/devicetree/bindings/regulator/ |
| H A D | st,stm32mp1-pwr-reg.yaml | 4 $id: http://devicetree.org/schemas/regulator/st,stm32mp1-pwr-reg.yaml#
7 title: STM32MP1 PWR voltage regulators
14 const: st,stm32mp1,pwr-reg
40 compatible = "st,stm32mp1,pwr-reg";
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| /openbmc/linux/Documentation/devicetree/bindings/crypto/ |
| H A D | st,stm32-cryp.yaml | 22 - st,stm32mp1-cryp
60 #include <dt-bindings/clock/stm32mp1-clks.h>
61 #include <dt-bindings/reset/stm32mp1-resets.h>
63 compatible = "st,stm32mp1-cryp";
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| /openbmc/u-boot/drivers/ram/stm32mp1/ |
| H A D | Kconfig | 3 bool "STM32MP1 DDR driver"
9 activate STM32MP1 DDR controller driver for STM32MP1 soc
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| /openbmc/u-boot/board/st/stm32mp1/ |
| H A D | MAINTAINERS | 1 STM32MP1 BOARD
5 F: board/st/stm32mp1
6 F: include/configs/stm32mp1.h
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| H A D | Kconfig | 4 default "stm32mp1"
10 default "stm32mp1"
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | st,stm32-fmc2-ebi.yaml | 26 const: st,stm32mp1-fmc2-ebi
67 #include <dt-bindings/clock/stm32mp1-clks.h>
68 #include <dt-bindings/reset/stm32mp1-resets.h>
72 compatible = "st,stm32mp1-fmc2-ebi";
97 compatible = "st,stm32mp1-fmc2-nfc";
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| /openbmc/linux/Documentation/devicetree/bindings/rtc/ |
| H A D | st,stm32-rtc.yaml | 17 - st,stm32mp1-rtc
93 const: st,stm32mp1-rtc
132 #include <dt-bindings/clock/stm32mp1-clks.h>
134 compatible = "st,stm32mp1-rtc";
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| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | st,stm32-fmc2-nand.yaml | 16 - st,stm32mp1-fmc2-nfc
83 const: st,stm32mp1-fmc2-nfc
105 #include <dt-bindings/clock/stm32mp1-clks.h>
106 #include <dt-bindings/reset/stm32mp1-resets.h>
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | stm32-dwmac.yaml | 24 - st,stm32mp1-dwmac
36 - st,stm32mp1-dwmac
107 #include <dt-bindings/clock/stm32mp1-clks.h>
108 #include <dt-bindings/reset/stm32mp1-resets.h>
112 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
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| /openbmc/linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | st,stm32-iwdg.yaml | 20 - st,stm32mp1-iwdg
49 #include <dt-bindings/clock/stm32mp1-clks.h>
51 compatible = "st,stm32mp1-iwdg";
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| /openbmc/linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | st,stm32-rproc.yaml | 19 const: st,stm32mp1-m4
165 #include <dt-bindings/reset/stm32mp1-resets.h>
167 compatible = "st,stm32mp1-m4";
179 #include <dt-bindings/reset/stm32mp1-resets.h>
181 compatible = "st,stm32mp1-m4";
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| /openbmc/linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | st,stm32-ipcc.yaml | 21 const: st,stm32mp1-ipcc
63 #include <dt-bindings/clock/stm32mp1-clks.h>
65 compatible = "st,stm32mp1-ipcc";
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| /openbmc/linux/Documentation/devicetree/bindings/reset/ |
| H A D | st,stm32mp1-rcc.txt | 1 STMicroelectronics STM32MP1 Peripheral Reset Controller
6 Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
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| /openbmc/u-boot/arch/arm/mach-stm32mp/ |
| H A D | Kconfig | 38 target STMicroelectronics SOC STM32MP1 family
57 source "board/st/stm32mp1/Kconfig"
|