12514c2d0SPatrick Delaunayif ARCH_STM32MP 22514c2d0SPatrick Delaunay 32514c2d0SPatrick Delaunayconfig SPL 42514c2d0SPatrick Delaunay select SPL_BOARD_INIT 52514c2d0SPatrick Delaunay select SPL_CLK 62514c2d0SPatrick Delaunay select SPL_DM 72514c2d0SPatrick Delaunay select SPL_DM_SEQ_ALIAS 8*bc06134eSPatrick Delaunay select SPL_DRIVERS_MISC_SUPPORT 92514c2d0SPatrick Delaunay select SPL_FRAMEWORK 102514c2d0SPatrick Delaunay select SPL_GPIO_SUPPORT 112514c2d0SPatrick Delaunay select SPL_LIBCOMMON_SUPPORT 122514c2d0SPatrick Delaunay select SPL_LIBGENERIC_SUPPORT 132514c2d0SPatrick Delaunay select SPL_OF_CONTROL 142514c2d0SPatrick Delaunay select SPL_OF_TRANSLATE 152514c2d0SPatrick Delaunay select SPL_PINCTRL 162514c2d0SPatrick Delaunay select SPL_REGMAP 17bfc6bae8SLey Foon Tan select SPL_DM_RESET 182514c2d0SPatrick Delaunay select SPL_SERIAL_SUPPORT 192514c2d0SPatrick Delaunay select SPL_SYSCON 2086634a93SPatrick Delaunay select SPL_DRIVERS_MISC_SUPPORT 212514c2d0SPatrick Delaunay imply SPL_LIBDISK_SUPPORT 222514c2d0SPatrick Delaunay 232514c2d0SPatrick Delaunayconfig SYS_SOC 242514c2d0SPatrick Delaunay default "stm32mp" 252514c2d0SPatrick Delaunay 262514c2d0SPatrick Delaunayconfig TARGET_STM32MP1 272514c2d0SPatrick Delaunay bool "Support stm32mp1xx" 2841c79775SPatrick Delaunay select ARCH_SUPPORT_PSCI 29acf15001SLokesh Vutla select CPU_V7A 3041c79775SPatrick Delaunay select CPU_V7_HAS_NONSEC 3141c79775SPatrick Delaunay select CPU_V7_HAS_VIRT 322514c2d0SPatrick Delaunay select PINCTRL_STM32 33d090cbabSPatrick Delaunay select STM32_RCC 342514c2d0SPatrick Delaunay select STM32_RESET 357842b6a9SAndre Przywara select SYS_ARCH_TIMER 3686634a93SPatrick Delaunay select SYSRESET_SYSCON 372514c2d0SPatrick Delaunay help 382514c2d0SPatrick Delaunay target STMicroelectronics SOC STM32MP1 family 392514c2d0SPatrick Delaunay STMicroelectronics MPU with core ARMv7 402514c2d0SPatrick Delaunay 412514c2d0SPatrick Delaunayconfig SYS_TEXT_BASE 422514c2d0SPatrick Delaunay prompt "U-Boot base address" 432514c2d0SPatrick Delaunay default 0xC0100000 442514c2d0SPatrick Delaunay help 452514c2d0SPatrick Delaunay configure the U-Boot base address 462514c2d0SPatrick Delaunay when DDR driver is used: 472514c2d0SPatrick Delaunay DDR + 1MB (0xC0100000) 482514c2d0SPatrick Delaunay 4911dfd1a3SPatrick Delaunayconfig SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 5011dfd1a3SPatrick Delaunay hex "Partition on MMC2 to use to load U-Boot from" 5111dfd1a3SPatrick Delaunay depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION 5211dfd1a3SPatrick Delaunay default 1 5311dfd1a3SPatrick Delaunay help 5411dfd1a3SPatrick Delaunay Partition on the second MMC to load U-Boot from when the MMC is being 5511dfd1a3SPatrick Delaunay used in raw mode 5611dfd1a3SPatrick Delaunay 57f8598d98SPatrick Delaunaysource "board/st/stm32mp1/Kconfig" 58f8598d98SPatrick Delaunay 59320d2663SPatrick Delaunay# currently activated for debug / should be deactivated for real product 60320d2663SPatrick Delaunayif DEBUG_UART 61320d2663SPatrick Delaunay 62320d2663SPatrick Delaunayconfig DEBUG_UART_BOARD_INIT 63320d2663SPatrick Delaunay default y 64320d2663SPatrick Delaunay 65320d2663SPatrick Delaunay# debug on UART4 by default 66320d2663SPatrick Delaunayconfig DEBUG_UART_BASE 67320d2663SPatrick Delaunay default 0x40010000 68320d2663SPatrick Delaunay 69320d2663SPatrick Delaunay# clock source is HSI on reset 70320d2663SPatrick Delaunayconfig DEBUG_UART_CLOCK 71320d2663SPatrick Delaunay default 64000000 72320d2663SPatrick Delaunayendif 73320d2663SPatrick Delaunay 742514c2d0SPatrick Delaunayendif 75