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/openbmc/linux/Documentation/infiniband/
H A Dtag_matching.rst14 The ordering rules require that when more than one pair of send and receive
16 and the earliest posted-receive is the pair that must be used to satisfy the
23 corresponding matching receive is posted. If a matching receive is posted,
44 There are two types of matching objects used, the posted receive list and the
45 unexpected message list. The application posts receive buffers through calls
46 to the MPI receive routines in the posted receive list and posts send messages
47 using the MPI send routines. The head of the posted receive list may be
50 When send is initiated and arrives at the receive side, if there is no
51 pre-posted receive for this arriving message, it is passed to the software and
54 specified receive buffer. This allows overlapping receive-side MPI tag
[all …]
/openbmc/u-boot/include/
H A Dfsl_dtsec.h23 u32 rctrl; /* Receive control register */
45 /* transmit and receive counter */
53 /* receive counters */
54 u32 rbyt; /* Receive byte counter */
55 u32 rpkt; /* Receive packet counter */
56 u32 rfcs; /* Receive FCS error */
57 u32 rmca; /* Receive multicast packet */
58 u32 rbca; /* Receive broadcast packet */
59 u32 rxcf; /* Receive control frame */
60 u32 rxpf; /* Receive pause frame */
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H A Dtsec.h215 /* Transmit and Receive Counters */
223 /* Receive Counters */
224 u32 rbyt; /* Receive Byte Counter */
225 u32 rpkt; /* Receive Packet Counter */
226 u32 rfcs; /* Receive FCS Error Counter */
227 u32 rmca; /* Receive Multicast Packet (Counter) */
228 u32 rbca; /* Receive Broadcast Packet */
229 u32 rxcf; /* Receive Control Frame Packet */
230 u32 rxpf; /* Receive Pause Frame Packet */
231 u32 rxuo; /* Receive Unknown OP Code */
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/openbmc/linux/sound/soc/fsl/
H A Dfsl_sai.h50 #define FSL_SAI_RCSR(ofs) (0x80 + ofs) /* SAI Receive Control */
51 #define FSL_SAI_RCR1(ofs) (0x84 + ofs)/* SAI Receive Configuration 1 */
52 #define FSL_SAI_RCR2(ofs) (0x88 + ofs) /* SAI Receive Configuration 2 */
53 #define FSL_SAI_RCR3(ofs) (0x8c + ofs) /* SAI Receive Configuration 3 */
54 #define FSL_SAI_RCR4(ofs) (0x90 + ofs) /* SAI Receive Configuration 4 */
55 #define FSL_SAI_RCR5(ofs) (0x94 + ofs) /* SAI Receive Configuration 5 */
56 #define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */
57 #define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */
58 #define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */
59 #define FSL_SAI_RDR3 0xac /* SAI Receive Data 3 */
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/openbmc/qemu/hw/net/fsl_etsec/
H A Dregisters.c40 {0x058, "FIFO_RX_ALARM", "FIFO receive alarm start threshold register", ACC_RW, 0x00000…
41 {0x05C, "FIFO_RX_ALARM_SHUTOFF", "FIFO receive alarm shut-off threshold register", ACC_RW, 0x00000…
80 /* eTSEC Receive Control and Status Registers */
82 {0x300, "RCTRL", "Receive control register", ACC_RW, 0x00000000},
83 {0x304, "RSTAT", "Receive status register", ACC_W1C, 0x00000000},
84 {0x310, "RXIC", "Receive interrupt coalescing register", ACC_RW, 0x00000000},
85 {0x314, "RQUEUE", "Receive queue control register.", ACC_RW, 0x00800080},
86 {0x330, "RBIFX", "Receive bit field extract control register", ACC_RW, 0x00000000},
87 {0x334, "RQFAR", "Receive queue filing table address register", ACC_RW, 0x00000000},
88 {0x338, "RQFCR", "Receive queue filing table control register", ACC_RW, 0x00000000},
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/openbmc/linux/drivers/net/ethernet/apple/
H A Dbmac.h22 # define MIIBuffDisable 0x0008 /* MII receive buffer disable */
31 #define RXFIFOCSR 0x120 /* receive FIFO control */
47 #define RXPNTR 0x1b0 /* receive pointer */
52 # define RxFrameCntExp 0x00000002 /* Receive frame counter expired */
56 # define RxOverFlow 0x00000020 /* Receive FIFO overflow */
68 # define RxNoDescriptors 0x00020000 /* No more receive descriptors */
69 # define RxDMAError 0x00040000 /* Error during receive DMA */
70 # define RxDMALateErr 0x00080000 /* Receive DMA, data late */
71 # define RxParityErr 0x00100000 /* Parity error during receive DMA */
72 # define RxTagError 0x00200000 /* Tag error during receive DMA */
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/openbmc/linux/drivers/firmware/
H A Dti_sci.h712 * UDMAP receive channels mapped to destination threads will have their
741 * UDMAP receive channels mapped to destination threads will have their
755 * struct ti_sci_msg_udmap_rx_flow_cfg - UDMAP receive flow configuration
758 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is
760 * @flow_index: UDMAP receive flow index for non-optional configuration.
761 * @rx_ch_index: Specifies the index of the receive channel using the flow_index
762 * @rx_einfo_present: UDMAP receive flow extended packet info present.
763 * @rx_psinfo_present: UDMAP receive flow PS words present.
764 * @rx_error_handling: UDMAP receive flow error handling configuration. Valid
766 * @rx_desc_type: UDMAP receive flow descriptor type. It can be one of
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/openbmc/linux/Documentation/networking/
H A Dscaling.rst17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
24 RSS: Receive Side Scaling
27 Contemporary NICs support multiple receive and transmit descriptor queues
31 of logical flows. Packets for each flow are steered to a separate receive
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
42 stores a queue number. The receive queue for a packet is determined
49 can be directed to their own receive queue. Such “n-tuple” filters can
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H A Dstrparser.rst17 The strparser works in one of two modes: receive callback or general
20 In receive callback mode, the strparser is called from the data_ready
33 functions, and a data_ready function for receive callback mode. The
48 socket associated with the stream parser for use with receive
101 maximum messages size is the limit of the receive socket
102 buffer and message timeout is the receive timeout for the socket.
144 zero) and the parser is in receive callback mode, then it will set
156 processing a timeout). In receive callback mode the default
165 by the lock callback. In receive callback mode the default
190 the TCP socket in receive callback mode. The stream parser may
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/openbmc/qemu/include/hw/net/
H A Dnpcm_gmac.h71 /* Receive Watchdog Timeout */
73 /* Receive Error */
84 /* Receive end of ring */
88 /* Receive Buffer 2 Size */
92 /* Receive Buffer 1 Size */
195 /* Receive States */
210 /* Early Receive Interrupt */
216 /* Receive Watchdog Timeout */
218 /* Receive Process Stopped */
220 /* Receive Buffer Unavailable */
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/openbmc/linux/drivers/net/ethernet/actions/
H A Dowl-emac.h35 /* Transmit/receive poll demand registers */
41 /* Receive/transmit descriptor list base address registers */
51 #define OWL_EMAC_MSK_MAC_CSR5_RS GENMASK(19, 17) /* Receive process state */
53 #define OWL_EMAC_VAL_MAC_CSR5_RS_FDES 0x01 /* Fetching receive descriptor */
54 #define OWL_EMAC_VAL_MAC_CSR5_RS_CDES 0x05 /* Closing receive descriptor */
58 #define OWL_EMAC_BIT_MAC_CSR5_ERI BIT(14) /* Early receive interrupt */
61 #define OWL_EMAC_BIT_MAC_CSR5_RPS BIT(8) /* Receive process stopped */
62 #define OWL_EMAC_BIT_MAC_CSR5_RU BIT(7) /* Receive buffer unavailable */
63 #define OWL_EMAC_BIT_MAC_CSR5_RI BIT(6) /* Receive interrupt */
73 #define OWL_EMAC_BIT_MAC_CSR6_RA BIT(30) /* Receive all */
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/openbmc/linux/drivers/net/ethernet/amd/
H A Dariadne.h78 #define CSR18 0x1200 /* Current Receive Buffer Address */
79 #define CSR19 0x1300 /* Current Receive Buffer Address */
82 #define CSR22 0x1600 /* Next Receive Buffer Address */
83 #define CSR23 0x1700 /* Next Receive Buffer Address */
84 #define CSR24 0x1800 /* - Base Address of Receive Ring */
85 #define CSR25 0x1900 /* - Base Address of Receive Ring */
86 #define CSR26 0x1a00 /* Next Receive Descriptor Address */
87 #define CSR27 0x1b00 /* Next Receive Descriptor Address */
88 #define CSR28 0x1c00 /* Current Receive Descriptor Address */
89 #define CSR29 0x1d00 /* Current Receive Descriptor Address */
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac_dma.h18 #define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
70 #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
76 #define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
77 #define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
86 #define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
87 #define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
88 #define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
90 #define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
112 #define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
116 #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/rsyslog/librelp/
H A D0001-tests-Include-missing-sys-time.h.patch11 ../../git/tests/receive.c:64:17: error: variable has incomplete type 'struct timeval'
14 ../../git/tests/receive.c:64:9: note: forward declaration of 'struct timeval'
17 ../../git/tests/receive.c:67:2: error: call to undeclared function 'select'; ISO C99 and later do n…
24 tests/receive.c | 3 ++-
27 diff --git a/tests/receive.c b/tests/receive.c
29 --- a/tests/receive.c
30 +++ b/tests/receive.c
/openbmc/linux/drivers/infiniband/hw/vmw_pvrdma/
H A Dpvrdma_srq.c56 * pvrdma_query_srq - query shared receive queue
57 * @ibsrq: the shared receive queue to query
79 "could not query shared receive queue, error: %d\n", in pvrdma_query_srq()
92 * pvrdma_create_srq - create shared receive queue
93 * @ibsrq: the IB shared receive queue
94 * @init_attr: shared receive queue attributes
116 "no shared receive queue support for kernel client\n"); in pvrdma_create_srq()
122 "shared receive queue type %d not supported\n", in pvrdma_create_srq()
130 "shared receive queue size invalid\n"); in pvrdma_create_srq()
142 "create shared receive queue from user space\n"); in pvrdma_create_srq()
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/openbmc/linux/include/uapi/rdma/
H A Dib_user_mad.h56 * @status - 0 on successful receive, ETIMEDOUT if no response
59 * @timeout_ms - Milliseconds to wait for response (unset on receive)
62 * @qkey - Remote Q_Key to be sent with (unset on receive)
67 * @gid_index - Local GID index to send with (unset on receive)
99 * @status - 0 on successful receive, ETIMEDOUT if no response
102 * @timeout_ms - Milliseconds to wait for response (unset on receive)
105 * @qkey - Remote Q_Key to be sent with (unset on receive)
110 * @gid_index - Local GID index to send with (unset on receive)
173 * @method_mask - The caller will receive unsolicited MADs for any method
175 * @mgmt_class - Indicates which management class of MADs should be receive
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/openbmc/linux/drivers/net/ethernet/freescale/fman/
H A Dfman_mac.h98 /* 10GEC, mEMAC Receive FIFO overflow interrupt */
100 /* 10GEC, mEMAC Receive frame ECC error interrupt */
102 /* 10GEC Receive jabber frame interrupt */
104 /* 10GEC Receive oversized frame interrupt */
106 /* 10GEC Receive runt frame interrupt */
108 /* 10GEC Receive fragment frame interrupt */
110 /* 10GEC Receive payload length error interrupt */
112 /* 10GEC Receive CRC error interrupt */
114 /* 10GEC Receive alignment error interrupt */
116 /* dTSEC Babbling receive error */
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/openbmc/linux/drivers/net/ethernet/sun/
H A Dsunhme.h37 #define GREG_STAT_RCNTEXP 0x00000002 /* Receive frame counter expired */
41 #define GREG_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */
52 #define GREG_STAT_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */
53 #define GREG_STAT_NORXD 0x00020000 /* No more receive descriptors */
54 #define GREG_STAT_RXERR 0x00040000 /* Error during receive dma */
55 #define GREG_STAT_RXLATERR 0x00080000 /* Late error during receive dma */
56 #define GREG_STAT_RXPERR 0x00100000 /* Parity error during receive dma */
57 #define GREG_STAT_RXTERR 0x00200000 /* Tag error during receive dma */
74 #define GREG_IMASK_RCNTEXP 0x00000002 /* Receive frame counter expired */
78 #define GREG_IMASK_RFIFOVF 0x00000020 /* Receive FIFO overflow */
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H A Dsunbmac.h16 #define GLOB_RSIZE 0x10UL /* Receive partition size */
30 #define GLOB_STAT_RX 0x00000004 /* BigMAC Receive IRQ */
63 #define CREG_STAT_RXIRQ 0x00000020 /* Receive Interrupt */
65 #define CREG_STAT_RXSMALL 0x00000008 /* Receive buffer too small */
66 #define CREG_STAT_RXLERR 0x00000004 /* Receive Late Error */
67 #define CREG_STAT_RXPERR 0x00000002 /* Receive Parity Error */
68 #define CREG_STAT_RXSERR 0x00000001 /* Receive SBUS Error ACK */
114 #define BMAC_RXPMAX 0x310UL /* Receive max pkt size */
115 #define BMAC_RXPMIN 0x314UL /* Receive min pkt size */
119 #define BMAC_FRCTR 0x324UL /* Receive frame receive counter */
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/openbmc/linux/drivers/staging/greybus/
H A Dlog.c22 struct gb_log_send_log_request *receive; in gb_log_request_handler() local
31 if (op->request->payload_size < sizeof(*receive)) { in gb_log_request_handler()
33 op->request->payload_size, sizeof(*receive)); in gb_log_request_handler()
36 receive = op->request->payload; in gb_log_request_handler()
37 len = le16_to_cpu(receive->len); in gb_log_request_handler()
38 if (len != (op->request->payload_size - sizeof(*receive))) { in gb_log_request_handler()
40 (op->request->payload_size - sizeof(*receive))); in gb_log_request_handler()
54 receive->msg[len - 1] = '\0'; in gb_log_request_handler()
60 dev_dbg(dev, "%s", receive->msg); in gb_log_request_handler()
/openbmc/linux/Documentation/networking/device_drivers/can/freescale/
H A Dflexcan.rst19 and i.MX53 SOCs) only receive RTR frames if the controller is
30 With the "rx-rtr" private flag the ability to receive RTR frames can
31 be waived at the expense of losing the ability to receive RTR
35 Receive RTR frames. (default)
37 The CAN controller can and will receive RTR frames.
39 On some IP cores the controller cannot receive RTR frames in the
45 Waive ability to receive RTR frames. (not supported on all IP cores)
/openbmc/linux/drivers/net/ethernet/moxa/
H A Dmoxart_ether.h48 #define RX_DESC0_ODD_NB 0x400000 /* receive odd nibbles */
49 #define RX_DESC0_LRS 0x10000000 /* last receive segment */
50 #define RX_DESC0_FRS 0x20000000 /* first receive segment */
122 #define NORXBUF BIT(1) /* receive buffer unavailable */
127 #define RPKT_SAV BIT(6) /* FIFO receive success */
128 #define RPKT_LOST_INT_STS BIT(7) /* FIFO full, receive failed */
172 #define RX_BROADPKT BIT(17) /* receive broadcast packets */
173 #define RX_MULTIPKT BIT(16) /* receive all multicast packets */
181 #define ENRX_IN_HALFTX BIT(6) /* enable receive in half duplex mode */
186 #define RDMA_EN BIT(1) /* enable receive DMA chan */
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/openbmc/qemu/hw/net/
H A Dallwinner-sun8i-emac.c46 REG_RX_CTL_0 = 0x0024, /* Receive Control 0 */
47 REG_RX_CTL_1 = 0x0028, /* Receive Control 1 */
48 REG_RX_DMA_DESC_LIST = 0x0034, /* Receive Descriptor List Address */
49 REG_FRM_FLT = 0x0038, /* Receive Frame Filter */
50 REG_RX_HASH_0 = 0x0040, /* Receive Hash Table 0 */
51 REG_RX_HASH_1 = 0x0044, /* Receive Hash Table 1 */
59 REG_RX_DMA_STA = 0x00C0, /* Receive DMA Status */
60 REG_RX_CUR_DESC = 0x00C4, /* Receive Current Descriptor */
61 REG_RX_CUR_BUF = 0x00C8, /* Receive Current Buffer */
157 /* Transmit/receive frame descriptor */
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dcpm_85xx.h112 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
259 ushort scc_mrblr; /* Max receive buffer length */
343 #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
355 /* Buffer descriptor control/status used by Ethernet receive.
401 ushort scc_parec; /* receive parity error counter */
402 ushort scc_frmec; /* receive framing error counter */
403 ushort scc_nosec; /* receive noise counter */
404 ushort scc_brkec; /* receive break condition counter */
418 ushort scc_rccm; /* receive control character mask */
419 ushort scc_rccr; /* receive control character register */
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/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpic-msgr.txt25 - mpic-msgr-receive-mask: Specifies what registers in the containing block
26 are allowed to receive interrupts. The value is a bit mask where a set
27 bit at bit 'n' indicates that message register 'n' can receive interrupts.
50 // Message registers 0 and 2 in this block can receive interrupts on
53 mpic-msgr-receive-mask = <0x5>;
59 // Message registers 0 and 2 in this block can receive interrupts on
62 mpic-msgr-receive-mask = <0x5>;

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