Lines Matching full:receive

35 /* Transmit/receive poll demand registers */
41 /* Receive/transmit descriptor list base address registers */
51 #define OWL_EMAC_MSK_MAC_CSR5_RS		GENMASK(19, 17)	/* Receive process state */
53 #define OWL_EMAC_VAL_MAC_CSR5_RS_FDES		0x01	/* Fetching receive descriptor */
54 #define OWL_EMAC_VAL_MAC_CSR5_RS_CDES		0x05	/* Closing receive descriptor */
58 #define OWL_EMAC_BIT_MAC_CSR5_ERI		BIT(14)	/* Early receive interrupt */
61 #define OWL_EMAC_BIT_MAC_CSR5_RPS		BIT(8)	/* Receive process stopped */
62 #define OWL_EMAC_BIT_MAC_CSR5_RU		BIT(7)	/* Receive buffer unavailable */
63 #define OWL_EMAC_BIT_MAC_CSR5_RI		BIT(6)	/* Receive interrupt */
73 #define OWL_EMAC_BIT_MAC_CSR6_RA		BIT(30)	/* Receive all */
88 #define OWL_EMAC_BIT_MAC_CSR6_SR		BIT(1)	/* Start/stop receive command */
89 #define OWL_EMAC_BIT_MAC_CSR6_HP		BIT(0)	/* Hash/perfect receive filtering mode */
97 #define OWL_EMAC_BIT_MAC_CSR7_ERE		BIT(14)	/* Early receive interrupt enable */
100 #define OWL_EMAC_BIT_MAC_CSR7_RSE		BIT(8)	/* Receive stopped enable */
101 #define OWL_EMAC_BIT_MAC_CSR7_RUE		BIT(7)	/* Receive buffer unavailable enable */
102 #define OWL_EMAC_BIT_MAC_CSR7_RIE		BIT(6)	/* Receive interrupt enable */
144 #define OWL_EMAC_OFF_MAC_CSR11_RT		20	/* Receive timer */
145 #define OWL_EMAC_OFF_MAC_CSR11_NRP		17	/* No. of receive packets */
167 #define OWL_EMAC_BIT_MAC_CSR20_RPE		BIT(28)	/* Receive Pause frames Enable */
177 /* Receive descriptor status field */
196 /* Receive descriptor control and count field */
197 #define OWL_EMAC_BIT_RDES1_RER			BIT(25)	/* Receive end of ring */