ethernet/sun/sunhme.h

37 #define GREG_STAT_RCNTEXP      0x00000002 /* Receive frame counter expired            */
41 #define GREG_STAT_RFIFOVF      0x00000020 /* Receive FIFO overflow                    */
52 #define GREG_STAT_RXTOHOST     0x00010000 /* Moved from receive-FIFO to host memory   */
53 #define GREG_STAT_NORXD        0x00020000 /* No more receive descriptors              */
54 #define GREG_STAT_RXERR        0x00040000 /* Error during receive dma                 */
55 #define GREG_STAT_RXLATERR     0x00080000 /* Late error during receive dma            */
56 #define GREG_STAT_RXPERR       0x00100000 /* Parity error during receive dma          */
57 #define GREG_STAT_RXTERR       0x00200000 /* Tag error during receive dma             */
74 #define GREG_IMASK_RCNTEXP     0x00000002 /* Receive frame counter expired            */
78 #define GREG_IMASK_RFIFOVF     0x00000020 /* Receive FIFO overflow                    */
89 #define GREG_IMASK_RXTOHOST    0x00010000 /* Moved from receive-FIFO to host memory   */
90 #define GREG_IMASK_NORXD       0x00020000 /* No more receive descriptors              */
91 #define GREG_IMASK_RXERR       0x00040000 /* Error during receive dma                 */
92 #define GREG_IMASK_RXLATERR    0x00080000 /* Late error during receive dma            */
93 #define GREG_IMASK_RXPERR      0x00100000 /* Parity error during receive dma          */
94 #define GREG_IMASK_RXTERR      0x00200000 /* Tag error during receive dma             */
145 #define ERX_CFG_DMAENABLE    0x00000001 /* Enable receive DMA        */
147 #define ERX_CFG_BYTEOFFSET   0x00000038 /* Receive first byte offset */
149 #define ERX_CFG_SIZE32       0x00000000 /* Receive ring size == 32   */
150 #define ERX_CFG_SIZE64       0x00000200 /* Receive ring size == 64   */
151 #define ERX_CFG_SIZE128      0x00000400 /* Receive ring size == 128  */
152 #define ERX_CFG_SIZE256      0x00000600 /* Receive ring size == 256  */
183 #define BMAC_RXMAX	0x310UL	/* Receive max pkt size               */
184 #define BMAC_RXMIN	0x314UL	/* Receive min pkt size               */
188 #define BMAC_FRCTR	0x324UL	/* Receive frame receive counter      */
189 #define BMAC_GLECTR	0x328UL	/* Receive giant-length error counter */
190 #define BMAC_UNALECTR	0x32cUL	/* Receive unaligned error counter    */
191 #define BMAC_RCRCECTR	0x330UL	/* Receive CRC error counter          */
209 #define BIGMAC_XCFG_MIIDISAB  0x00000008 /* MII receive buffer disable   */
224 /* BigMac receive config register. */
302  * All receive buffers must be 64 byte aligned.
496 /* We use this to acquire receive skb's that we can DMA directly into. */